Silicon carbide MOSFET structure and manufacturing method thereof
By using a combination of high-energy injection and epitaxial filling in the silicon carbide superjunction structure, a deeper P-column layer is formed, which solves the problem of insufficient depth, reduces process difficulty and leakage risks, and improves device performance and yield.
Patent Information
- Application Number
- CN202411546831.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-11
AI Technical Summary
In the silicon carbide superjunction structure, deeper P-type columns are difficult to achieve, resulting in high process complexity and difficult development, and poor matching of P and N may lead to leakage problems.
Through the combination of high-energy injection and epitaxial filling, an integral P-column layer is formed. Without increasing the depth of the trench structure, the overall depth of the P-column layer is effectively increased, process difficulty is reduced, and device yield and performance are improved.
It is achieved without increasing the trench depth, and accurately control the inclination of the trench side wall and wall deformation, improve the matching of P and N, reduce the on-resistance, and improve the device performance and yield.
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Figure CN119421467A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a silicon carbide MOSFET structure and a method for manufacturing the same. Background Art
[0002] In the field of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, Super Junction technology is a key innovation. At present, the main super junction process routes in the industry include deep trench super junction and multi-layer epitaxial super junction. The deep trench super junction process forms a P-type column through deep trench etching and epitaxial filling technology, while the multi-layer epitaxial super junction constructs a super junction structure through multiple epitaxial growth and ion implantation. However, due to the characteristics of silicon carbide (SiC) materials, such as high hardness and high thermal stability, the development and commercialization of its super junction process is more complicated and slow than that of silicon materials.
[0003] In some requirements, a deeper P-type column may be required to improve the performance of the super junction. In order to increase the depth of the P-type column into the silicon carbide N-type epitaxial layer, a deeper trench structure is generally required. After the trench structure is deepened, the inclination of its side walls and the shape of the trench walls are not easy to control, which will lead to poor matching of P and N, and leakage problems may also occur. It can be seen from this that for super junction structures using silicon carbide materials, the process complexity is high and the development difficulty is great. Summary of the invention
[0004] The purpose of the present application is to provide a silicon carbide MOSFET structure and a method for manufacturing the same, which manufactures an integral P-column layer by combining high-energy injection and epitaxial filling, effectively increasing the overall depth of the P-column layer without increasing the depth of the trench structure, reducing process difficulty, improving device yield, and improving device performance.
[0005] The present application provides a silicon carbide MOSFET structure, comprising:
[0006] A silicon carbide substrate layer, including a front side and a back side;
[0007] A silicon carbide N-type epitaxial layer is arranged on the front side of the silicon carbide substrate layer;
[0008] A trench structure is provided in the silicon carbide N-type epitaxial layer and extends from the front side of the silicon carbide N-type epitaxial layer to a predetermined depth toward the back side;
[0009] The P column layer includes a first P column layer and a second P column layer; the first P column layer is formed by high-energy implantation into the silicon carbide N-type epitaxial layer from the bottom surface of the trench structure; the second P column layer is filled in the trench structure, and its surface is flush with the surface of the silicon carbide N-type epitaxial layer;
[0010] A P-type well region is disposed on the top of the P-column layer and can completely cover the top of the P-column layer;
[0011] An N-type heavily doped region is disposed on the top of the P-type well region;
[0012] The gate structure layer is arranged on the surface of the silicon carbide N-type epitaxial layer, covering part of the P-type well region and part of the N-type heavily doped region; wherein the surfaces of the exposed N-type heavily doped region and the P-type well region form a source electrode;
[0013] A top metal layer covers the gate structure layer and the source electrode, and the top metal layer forms an electrical contact with the source electrode;
[0014] A drain electrode is formed by disposing a back metal layer on the back side of the silicon carbide substrate layer.
[0015] In an implementable solution, a silicon carbide MOSFET structure includes a pad layer and a protective insulating film; the pad layer is formed on the top metal layer for connecting to an external circuit; and the protective insulating film covers the pad layer.
[0016] In an implementable scheme, the gate structure layer includes a gate oxide layer, a polysilicon gate and an insulating layer. The gate oxide layer is arranged on the top of the silicon carbide N-type epitaxial layer, the gate oxide layer covers the silicon carbide N-type epitaxial layer, part of the P-type well region and part of the N-type heavily doped region, and a polysilicon gate is arranged directly above the gate oxide layer; the insulating layer covers the polysilicon gate and the gate oxide layer to isolate the polysilicon gate from the source and the top metal layer.
[0017] In an implementable solution, the silicon carbide MOSFET structure further includes a JFET region, which is disposed on the top of the silicon carbide N-type epitaxial layer and contacts the bottom surface of the gate structure layer.
[0018] In an implementable solution, the depth of the groove structure is 4-7 um.
[0019] In an implementable solution, the depth of the first P column layer is 2-4 um.
[0020] In a second aspect, the present application provides a method for manufacturing a silicon carbide MOSFET structure, comprising:
[0021] S1. providing a silicon carbide substrate layer, and forming a silicon carbide N-type epitaxial layer on the silicon carbide substrate layer;
[0022] S2, etching a groove structure on the silicon carbide N-type epitaxial layer;
[0023] S3, performing high energy implantation at the bottom of the trench structure to form a first P column layer implanted with high energy;
[0024] S4, epitaxially filling a P-type epitaxial material in the trench structure, and grinding the surface flat to form an epitaxially filled second P column layer;
[0025] S5, forming a P-type well region in a portion of the silicon carbide N-type epitaxial layer at the top of the second P column layer and around it;
[0026] S6, forming an N-type heavily doped region in the P-type well region;
[0027] S7, forming a gate structure layer on the surface of the silicon carbide N-type epitaxial layer; the gate structure layer covers part of the P-type well region and part of the N-type heavily doped region; wherein the exposed surfaces of the N-type heavily doped region and the P-type well region form a source electrode;
[0028] S8, forming a top metal layer on the surface of the gate structure layer and the surface of the source electrode; the top metal layer forms electrical contact with the source electrode;
[0029] S9. Form a back metal layer on the back side of the silicon carbide substrate layer to serve as a drain.
[0030] In an practicable solution, after step S8 and before step S9, the following steps are included:
[0031] S81, forming a pad layer and a protective insulating film covering the pad layer on the top metal layer.
[0032] In an practicable solution, after step S1 and before step S2, the following steps are further included:
[0033] S11. Form a JFET region on the silicon carbide N-type epitaxial layer; the JFET region is located at the bottom side of the gate structure layer and contacts the bottom surface of the gate structure layer.
[0034] In an implementable solution, in step S7, the step of forming a gate structure layer on the surface of the silicon carbide N-type epitaxial layer includes:
[0035] S71, forming a gate oxide layer on the surface of the silicon carbide N-type epitaxial layer;
[0036] S72, forming a polysilicon gate layer on the surface of the gate oxide layer;
[0037] S73, etching away the polysilicon gate layer and the gate oxide layer located on the upper side of the P column layer, forming a polysilicon gate from the polysilicon gate layer, and exposing the surface of a portion of the N-type heavily doped region and the P-type well region;
[0038] S74, forming an insulating layer on the surface of the polysilicon gate and the exposed N-type heavily doped region and P-type well region;
[0039] S75, etching away the insulating layer located on the upper side of the P column layer until the surface of a portion of the N-type heavily doped region and the P-type well region is exposed, and ensuring that the sidewall and top surface of the polysilicon gate are covered by the insulating layer.
[0040] Compared with the prior art, the beneficial effects of the present application include at least the following:
[0041] In this application, an innovative technology is used to construct the P column layer of the silicon carbide MOSFET structure. Specifically, the first P column layer is formed by high-energy implantation of the silicon carbide N-type epitaxial layer at the bottom of the trench structure, and the second P column layer is formed by epitaxial filling in the trench structure. The two together constitute the P column layer, thereby effectively increasing the overall depth of the P column layer without increasing the depth of the trench structure.
[0042] First, not further increasing the depth of the groove structure helps to more accurately control the inclination and wall deformation of the sidewall of the groove structure, which is beneficial to ensure good matching between P and N, and also reduces the technical difficulty in the manufacturing process.
[0043] In addition, the first P column layer formed by high-energy implantation makes the control of implantation depth and concentration more precise, which helps to reduce on-resistance and improve the matching of P and N, thereby improving the overall performance of the device and reducing the difficulty of the manufacturing process.
[0044] In addition, better control over the sidewall inclination and wall deformation of the trench structure is beneficial to controlling the sidewall thickness of the insulating layer that subsequently covers the gate, thereby avoiding leakage problems. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0046] Figure 1 A schematic diagram of a silicon carbide MOSFET structure according to an embodiment of the present application;
[0047] Figure 2 A flow chart of a method for manufacturing a silicon carbide MOSFET structure according to an embodiment of the present application;
[0048] Figure 3 A schematic diagram of forming a silicon carbide N-type epitaxial layer on the surface of a silicon carbide substrate layer;
[0049] Figure 4 A schematic diagram of forming a JFET region in a silicon carbide N-type epitaxial layer;
[0050] Figure 5 is a schematic diagram of forming a trench structure in a silicon carbide N-type epitaxial layer;
[0051] Figure 6 A schematic diagram of forming a first P column layer by high energy implantation at the bottom of the trench structure;
[0052] Figure 7 is a schematic diagram of forming a second P column layer after epitaxial filling and grinding in a trench structure;
[0053] Figure 8 A schematic diagram of forming a P-type well region and an N-type heavily doped region in a silicon carbide N-type epitaxial layer and a P-pillar layer;
[0054] Figures 9a to 9e A diagram showing the manufacturing process steps of the gate structure layer;
[0055] Fig.10 This is the structural diagram after making the top metal layer.
[0056] In the figure: 1. Silicon carbide substrate layer; 2. Silicon carbide N-type epitaxial layer; 3. Trench structure; 4. P-column layer; 41. First P-column layer; 42. Second P-column layer; 5. P-type well region; 6. N-type heavily doped region; 7. Gate structure layer; 71. Gate oxide layer; 72. Polysilicon gate; 702. Polysilicon gate layer; 73. Insulating layer; 8. Source; 9. Top metal layer; 10. Drain; 11. Pad layer; 12. Protective insulating film; 13. JFET region. DETAILED DESCRIPTION
[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0058] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0059] Due to the characteristics of silicon carbide (SiC) materials, such as high hardness and high thermal stability, the super junction process becomes more difficult and it is difficult to improve the performance of silicon carbide super junction with existing technologies.
[0060] In particular, in some development requirements, a deeper P-type column may be required to improve the performance of the super junction. In order to increase the depth of the P-type column into the silicon carbide N-type epitaxial layer, the existing process increases the depth of the P-type column by making a deeper trench structure in the hope of meeting performance requirements. However, the inventors found that after the trench structure is deepened, the inclination of the side wall of the trench structure, the deformation of the wall of the trench, etc. are not easy to control, which will lead to poor matching of the P and N super junctions, and leakage problems may also occur, resulting in a decrease in yield. It can be seen from this that for super junction structures using silicon carbide materials, the process complexity is high and the development difficulty is great.
[0061] In order to solve the above problems, the present application provides the following embodiments.
[0062] like Figure 1 As shown, the present application first provides an embodiment of a silicon carbide MOSFET structure, including a silicon carbide substrate layer 1, a silicon carbide N-type epitaxial layer 2, a trench structure 3, a P-column layer 4, a P-type well region 5, an N-type heavily doped region 6, a gate structure layer 7, a top metal layer 9 and a drain 10.
[0063] The silicon carbide substrate layer 1 includes a front side and a back side, and the silicon carbide N-type epitaxial layer 2 is arranged on the front side of the silicon carbide substrate layer 1. The number of the groove structures 3 can be one, or two or more. When there are multiple groove structures 3, the groove structures 3 are arranged in the silicon carbide N-type epitaxial layer 2 in an intermittent arrangement, and the groove structures 3 extend from the front side of the silicon carbide N-type epitaxial layer 2 to a predetermined depth to the back side.
[0064] A P column layer 4 is provided in each trench structure 3. The P column layer 4 includes a first P column layer 41 and a second P column layer 42. The first P column layer 41 is formed by high-energy implantation into the silicon carbide N-type epitaxial layer 2 from the bottom surface of the trench structure 3. The second P column layer 42 is filled in the trench structure 3, and its surface is flush with the surface of the silicon carbide N-type epitaxial layer 2. After the trench structure 3 is manufactured, it is equivalent to forming an N column layer in the silicon carbide N-type epitaxial layer 2. After all the P column layers 4 are manufactured, an alternating P-type and N-type columnar structure is formed, which can significantly reduce the on-resistance of the device while maintaining high withstand voltage characteristics.
[0065] In addition, the P-type well region 5 (P-well region) is arranged at the top of the P-column layer 4 and can completely cover the top of the P-column layer 4. The N-type heavily doped region 6 is arranged at the top of the P-type well region 5. The gate structure layer 7 is arranged on the surface of the silicon carbide N-type epitaxial layer 2 and is located on both sides of the P-column layer 4. The gate structure layer 7 covers part of the P-type well region 5 and part of the N-type heavily doped region 6. The exposed N-type heavily doped region 6 and the surface of the P-type well region 5 form a source 8. The source 8 and the gate structure layer 7 are arranged in an alternating manner. The top metal layer 9 covers the gate structure layer 7 and the source 8, and the top metal layer 9 forms an electrical contact with the source 8. The drain 10 is provided with a back metal layer on the back of the silicon carbide substrate layer 1 to form the drain 10.
[0066] In this embodiment, an innovative technology is used to construct the P column layer 4 of the silicon carbide MOSFET structure. Specifically, the first P column layer 41 is formed by high-energy implantation of the silicon carbide N-type epitaxial layer 2 at the bottom of the trench structure 3, and the second P column layer 42 is formed by epitaxial filling in the trench structure 3. The two together constitute the P column layer 4, thereby effectively increasing the overall depth of the P column layer 4 without increasing the depth of the trench structure 3.
[0067] First, not further increasing the depth of the groove structure 3 helps to more accurately control the inclination and wall deformation of the sidewall of the groove structure 3, which is beneficial to ensure good matching of P and N, and also reduces the technical difficulty in the manufacturing process.
[0068] Furthermore, the first P column layer 41 formed by high-energy implantation makes the implantation depth and concentration more precisely controlled, which helps to reduce the on-resistance and improve the matching of P and N, thereby improving the overall performance of the device and reducing the difficulty of the manufacturing process.
[0069] In addition, better control of the sidewall inclination and wall deformation of the trench structure 3 is beneficial to controlling the sidewall thickness of the insulating layer covering the gate in the future, thereby avoiding leakage problems.
[0070] It should be noted that high-energy implantation can also be called ion implantation, which is just a different name for the same process as ion implantation. It is a technology used to dope semiconductor materials by accelerating and implanting charged impurity atoms (ions) into semiconductor materials to change their electrical properties. The process of high-energy implantation allows precise control of doping depth and concentration, which is achieved by adjusting the energy and dose of the implanted ions. The implanted ions are accelerated to high energy levels, usually between tens of kiloelectronvolts (keV) and millions of electronvolts (MeV), allowing them to penetrate the surface of the semiconductor material and reach the desired depth. The purpose of ion implantation is to create PN junctions, form highly doped regions (such as source and drain), and adjust the conductivity type of the semiconductor. This process is carried out in a specialized ion implanter that can generate, accelerate and precisely direct ion beams. After ion implantation, an annealing (or activation) process is usually required to repair lattice damage and move the doped atoms to the appropriate position of the lattice to activate their electrical activity.
[0071] In one embodiment, the silicon carbide MOSFET structure includes a pad layer 11 and a protective insulating film 12. The pad layer 11 is formed on the top metal layer 9 for connecting to an external circuit, and the protective insulating film 12 covers the pad layer 11.
[0072] Among them, the pad layer 11 usually adopts metal materials with good electrical conductivity, such as copper (Cu), aluminum (Al) or gold (Au), which not only have good electrical conductivity, but also can provide stable electrical connection. Copper is the preferred material for the pad layer due to its low resistivity and high thermal conductivity, while aluminum is widely used due to its good adhesion and low cost. Gold is often used in occasions requiring higher reliability and durability due to its excellent chemical stability and corrosion resistance. The protective insulating film 12 is made of materials with good electrical insulation properties and chemical stability to ensure that the pad layer is protected from environmental influences and physical damage. Common protective insulating film materials include silicon nitride (SiNx), silicon oxide (SiO2) and photoresist.
[0073] In one embodiment, the gate structure layer 7 includes a gate oxide layer 71, a polysilicon gate 72 and an insulating layer 73. The gate oxide layer 71 is arranged on the top of the silicon carbide N-type epitaxial layer 2. The gate oxide layer 71 covers the silicon carbide N-type epitaxial layer 2, part of the P-type well region 5 and part of the N-type heavily doped region 6. A polysilicon gate 72 is arranged directly above the gate oxide layer 71; the insulating layer 73 covers the polysilicon gate 72 and the gate oxide layer 71 to isolate the polysilicon gate 72 from the source 8 and the top metal layer 9.
[0074] It should be noted that not further increasing the depth of the trench structure 3 helps to more accurately control the inclination and wall deformation of the sidewall of the trench structure 3, so that the thickness of the insulating layer 73 covering the sidewall of the polysilicon gate 72 can be better controlled.
[0075] In one embodiment, the silicon carbide MOSFET structure may further include a JFET region 13, which is disposed on the top of the silicon carbide N-type epitaxial layer 2 and contacts the bottom surface of the gate structure layer 7. The JFET region, i.e., the junction field effect transistor region, the full name of which is Junction Field-Effect Transistor, helps to enhance the control capability of the gate, especially under high voltage conditions, more effectively regulating the current flow between the source and the drain, thereby improving the performance of the device.
[0076] In one embodiment, the depth of the trench structure 3 may be 4-7 um, for example, 4 um, 5 um, 6 um, 7 um, etc.
[0077] In one embodiment, the depth of the first P column layer 41 may be 2-4 um, for example, 2 um, 3 um, 4 um, etc.
[0078] like Figure 2 As shown, the present application also provides a method for manufacturing a silicon carbide MOSFET structure, which can manufacture the aforementioned silicon carbide MOSFET structure, and the manufacturing method includes:
[0079] S1. providing a silicon carbide substrate layer, and forming a silicon carbide N-type epitaxial layer on the silicon carbide substrate layer;
[0080] S2, etching a groove structure on the silicon carbide N-type epitaxial layer;
[0081] S3, performing high energy implantation at the bottom of the trench structure to form a first P column layer implanted with high energy;
[0082] S4, epitaxially filling a P-type epitaxial material in the trench structure, and grinding the surface flat to form an epitaxially filled second P column layer;
[0083] S5, forming a P-type well region in a portion of the silicon carbide N-type epitaxial layer at the top of the second P column layer and around it;
[0084] S6, forming an N-type heavily doped region in the P-type well region;
[0085] S7, forming a gate structure layer on the surface of the silicon carbide N-type epitaxial layer; the gate structure layer covers part of the P-type well region and part of the N-type heavily doped region; wherein the exposed surfaces of the N-type heavily doped region and the P-type well region form a source electrode;
[0086] S8, forming a top metal layer on the surface of the gate structure layer and the surface of the source electrode; the top metal layer forms electrical contact with the source electrode;
[0087] S9. Form a back metal layer on the back side of the silicon carbide substrate layer to serve as a drain.
[0088] The following is a more detailed explanation of the steps in conjunction with the MOSFET structure diagram in the process steps.
[0089] Specifically, Figure 3 As shown, in step S1 , a silicon carbide N-type epitaxial layer 2 can be formed on the silicon carbide substrate layer 1 by high energy implantation (ie, ion implantation).
[0090] like Figure 4 As shown, after forming the silicon carbide N-type epitaxial layer 2 in step S1, before making the trench structure 3 in step S2, the following steps may be further included: S11, forming a JFET region 13 on the silicon carbide N-type epitaxial layer 2 by high energy implantation. Figure 1 It can be seen that the JFET region 13 is located at the bottom side of the gate structure layer 7 and contacts the bottom surface of the gate structure layer 7. Figure 4 As shown, a plurality of JFET regions 13 are generally provided and arranged in an alternating manner.
[0091] like Figure 5 As shown, in step S2, a groove structure 3 of a predetermined depth (e.g., 4 to 7 um) is etched on the silicon carbide N-type epitaxial layer 2 according to actual needs. The number of the groove structures 3 can be one, or two or more. When there are multiple groove structures 3, the groove structures 3 and the JFET regions 13 are arranged in the silicon carbide N-type epitaxial layer 2 in an alternating manner.
[0092] like Figure 6 As shown, in step S3, the first P column layer 41 is formed at the bottom of each trench structure 3 by high energy injection, and the doping depth and concentration can be more accurately controlled, which is beneficial to improving device performance. It should be noted that the first P column layer 41 may need to reach a deeper depth in some cases. At this time, the high energy injection process for forming the first P column layer 41 generally requires higher energy than the high energy injection for forming other doping regions.
[0093] like Figure 7 As shown, in step S4, after the first P column layer 41 is produced, the P-type epitaxial material is filled in the trench structure 3 through an epitaxial filling process. The filled material generally protrudes out of the silicon carbide N-type epitaxial layer 2. After that, the surfaces of both are generally polished and flattened through a chemical mechanical polishing (CMP) process. At this time, the material layer in the trench structure 3 is the second P column layer 42, and the entire P column layer 4 is completed.
[0094] In addition, after the trench structure 3 is formed, an N column layer is formed in the areas on both sides of the trench structure 3 (i.e., below the JFET area 13), thereby forming an alternating P-type and N-type columnar structure, which can significantly reduce the on-resistance of the device while maintaining high voltage resistance characteristics.
[0095] like Figure 8 As shown, the P-type well region 5 in step S5 is formed by high-energy implantation, which is formed by implanting downwards the P-column layer 4 and the silicon N-type epitaxial layer 2 around the P-column layer 4. In the projection of the P-column layer 4 and the P-type well region 5 onto the silicon carbide substrate layer 1, the boundary of the P-column layer 4 is located within the boundary of the P-type well region 5. The N-type heavily doped region 6 in step S6 is formed by high-energy implantation, which is formed by implanting downwards from the surface of the P-type well region 5.
[0096] In one embodiment, in step S7, the step of forming a gate structure layer 7 on the surface of the silicon carbide N-type epitaxial layer 2 includes:
[0097] S71, such as Figure 9a As shown, a gate oxide layer 71 is formed on the surface of the silicon carbide N-type epitaxial layer 2;
[0098] S72, such as Figure 9b As shown, a polysilicon gate layer 702 is formed on the surface of the gate oxide layer 71;
[0099] S73, such as Fig.9c As shown, the polysilicon gate layer 702 and the gate oxide layer 71 located on the upper side of the P column layer 4 are etched away, and the polysilicon gate layer 702 forms a polysilicon gate 72, and partially exposes the surface of the N-type heavily doped region 6 and the P-type well region 5;
[0100] S74, such as Figure 9d As shown, an insulating layer 73 is formed on the surface of the polysilicon gate 72 and the exposed N-type heavily doped region 6 and the P-type well region 5;
[0101] S75, such as Fig.9e As shown, the insulating layer 73 located on the upper side of the P column layer 4 is etched away until the surfaces of a portion of the N-type heavily doped region 6 and the P-type well region 5 are exposed, and the sidewalls and top surface of the polysilicon gate 72 are covered by the insulating layer 73 .
[0102] like Fig.10 As shown, the top metal layer 9 in step S8 is generally formed by a deposition process.
[0103] Afterwards, if Figure 1 As shown, after step S8 and before step S9, the following steps are included:
[0104] S81 , forming a pad layer 11 and a protective insulating film 12 covering the pad layer 11 on the top metal layer 9 .
[0105] Finally, see Figure 1 A back metal layer serving as a drain electrode 10 is fabricated on the back side of the silicon carbide substrate layer 1 .
[0106] The above description is only a partial embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A silicon carbide MOSFET structure, characterized in that: include: A silicon carbide substrate layer, including a front side and a back side; A silicon carbide N-type epitaxial layer, arranged on the front side of the silicon carbide substrate layer; A trench structure is provided in the silicon carbide N-type epitaxial layer and extends from the front side of the silicon carbide N-type epitaxial layer to a predetermined depth toward the back side; The P column layer comprises a first P column layer and a second P column layer; the first P column layer is formed by high-energy implantation of the bottom surface of the groove structure into the silicon carbide N-type epitaxial layer; the second P column layer is filled in the groove structure, and its surface is flush with the surface of the silicon carbide N-type epitaxial layer; A P-type well region is disposed on the top of the P column layer and can completely cover the top of the P column layer; An N-type heavily doped region, disposed on the top of the P-type well region; A gate structure layer is disposed on the surface of the silicon carbide N-type epitaxial layer, covering a portion of the P-type well region and a portion of the N-type heavily doped region; wherein the exposed surfaces of the N-type heavily doped region and the P-type well region form a source electrode; A top metal layer, covering the gate structure layer and the source electrode, and the top metal layer forms an electrical contact with the source electrode; A drain electrode is formed by disposing a back metal layer on the back side of the silicon carbide substrate layer.
2. The silicon carbide MOSFET structure according to claim 1, characterized in that: It includes a pad layer and a protective insulating film; the pad layer is formed on the top metal layer and is used for connecting with an external circuit; the protective insulating film covers the pad layer.
3. The silicon carbide MOSFET structure according to claim 1, characterized in that: The gate structure layer includes a gate oxide layer, a polysilicon gate and an insulating layer, wherein the gate oxide layer is arranged on top of the silicon carbide N-type epitaxial layer, the gate oxide layer covers the silicon carbide N-type epitaxial layer, part of the P-type well region and part of the N-type heavily doped region, and the polysilicon gate is arranged directly above the gate oxide layer; the insulating layer covers the polysilicon gate and the gate oxide layer to isolate the polysilicon gate from the source and the top metal layer.
4. The silicon carbide MOSFET structure according to claim 3, characterized in that: It also includes a JFET region, which is arranged on the top of the silicon carbide N-type epitaxial layer and contacts the bottom surface of the gate structure layer.
5. The silicon carbide MOSFET structure according to any one of claims 1 to 4, characterized in that: The depth of the groove structure is 4-7 um.
6. The silicon carbide MOSFET structure according to any one of claims 1 to 4, characterized in that: The depth of the first P column layer is 2-4 um.
7. A method for manufacturing a silicon carbide MOSFET structure, characterized in that: include: S1. providing a silicon carbide substrate layer, and forming a silicon carbide N-type epitaxial layer on the silicon carbide substrate layer; S2, etching a groove structure on the silicon carbide N-type epitaxial layer; S3, performing high energy implantation at the bottom of the trench structure to form a first P column layer implanted with high energy; S4, epitaxially filling a P-type epitaxial material in the trench structure, and grinding the surface flat to form an epitaxially filled second P column layer; S5, forming a P-type well region in a portion of the silicon carbide N-type epitaxial layer at the top of the second P column layer and around it; S6, forming an N-type heavily doped region in the P-type well region; S7, forming a gate structure layer on the surface of the silicon carbide N-type epitaxial layer; The gate structure layer covers part of the P-type well region and part of the N-type heavily doped region; wherein the exposed surfaces of the N-type heavily doped region and the P-type well region form a source electrode; S8, forming a top metal layer on the surface of the gate structure layer and the surface of the source electrode; the top metal layer forms electrical contact with the source electrode; S9. Form a back metal layer on the back side of the silicon carbide substrate layer to serve as a drain.
8. The method for manufacturing a silicon carbide MOSFET structure according to claim 7, characterized in that: After step S8 and before step S9, the method includes: S81, forming a pad layer and a protective insulating film covering the pad layer on the top metal layer.
9. The method for manufacturing a silicon carbide MOSFET structure according to claim 7, characterized in that: After step S1 and before step S2, the method further includes: S11. Forming a JFET region on the silicon carbide N-type epitaxial layer; the JFET region is located at the bottom side of the gate structure layer and contacts the bottom surface of the gate structure layer.
10. The method for manufacturing a silicon carbide MOSFET structure according to claim 7, characterized in that: In the step S7, the step of forming a gate structure layer on the surface of the silicon carbide N-type epitaxial layer includes: S71, forming a gate oxide layer on the surface of the silicon carbide N-type epitaxial layer; S72, forming a polysilicon gate layer on the surface of the gate oxide layer; S73, etching away the polysilicon gate layer and the gate oxide layer located on the upper side of the P column layer, forming a polysilicon gate from the polysilicon gate layer, and exposing the surface of a portion of the N-type heavily doped region and the P-type well region; S74, forming an insulating layer on the surface of the polysilicon gate and the exposed N-type heavily doped region and P-type well region; S75, etching away the insulating layer located on the upper side of the P column layer until the surfaces of a portion of the N-type heavily doped region and the P-type well region are exposed, and ensuring that the sidewall and top surface of the polysilicon gate are covered by the insulating layer.