Array substrate and display panel

Abstract

According to the array substrate and the display panel, the array substrate comprises the first area and the second area surrounding the first area, and the edge, away from the first area, of the second area is reused as the edge of the array substrate. The array substrate further comprises first wires and second wires, and the second ends of at least part of the second wires coincide with the edge of the array substrate. A first insulating layer is arranged between the first wire and the second wire. Wherein the first wire comprises a first gap; and / or the second wire comprises a second gap. According to the invention, the accuracy of signal transmission of the first wire and the second wire is ensured through the first gap and the second gap. Besides, when the array substrates with different shapes are prepared, all the film layers of the array substrate with the public version size can be prevented from being developed again, the development time and cost of the array substrate are reduced, conditions are provided for achieving arbitrary cutting to a certain degree, and the efficiency of preparing the array substrates with different shapes is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the advancement of display technology, the market has more requirements for the structural form of display panels. In the process of cutting and preparing special-shaped display panels, due to the presence of adjacent film layers inside the display panel, when arbitrarily cutting according to the shape of the panel, it is easy for the adjacent film layers to be adhered together due to cutting, causing part of the wiring at the cutting edge to short-circuit between different wirings. Therefore, in order to avoid this situation, it is necessary to develop a separate public panel before preparing the special-shaped panel, and perform a separate avoidance design near the cutting edge, so that the wiring is located in the cutting area and the wiring is kept at a certain safe distance from the cutting edge. In this way, when the avoidance design is performed for each film layer of each panel, the preparation cost and efficiency of the display panel are greatly affected. Summary of the invention

[0003] In view of this, the present application provides an array substrate and a display panel to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, comprising a first area and a second area surrounding the first area, wherein an edge of the second area away from the first area is reused as an edge of the array substrate; the array substrate comprises:

[0005] substrate;

[0006] A first wiring line is located at one side of the substrate, and a first end of at least part of the first wiring line coincides with an edge of the array substrate;

[0007] The second routing line is located on a side of the film layer where the first routing line is located away from the substrate, and at least a portion of the second end of the second routing line overlaps with an edge of the array substrate; a first insulating layer is included between the first routing line and the second routing line; along a direction perpendicular to the plane where the array substrate is located, at least a portion of the first end overlaps with at least a portion of the second end;

[0008] Wherein, the first routing includes a first portion and a second portion extending in the same direction and not connected, the first portion is at least partially located in the first area, the second portion is located in the second area, and a first gap is included between the first portion and the second portion; and / or, the second routing includes a third portion and a fourth portion extending in the same direction and not connected, the third portion is at least partially located in the first area, the fourth portion is located in the second area, and a second gap is included between the third portion and the fourth portion.

[0009] In a second aspect, an embodiment of the present application provides a display panel, comprising an array substrate provided in the first aspect.

[0010] In the embodiment of the present application, the first routing line includes a first gap, and / or the second routing line includes a second gap, so that if the first end of the first routing line overlaps with the second end of the second routing line at the edge of the array substrate and there is a metal residue to produce a short circuit, it is beneficial to prevent the signal on the second routing line from being transmitted to the first part of the first routing line through the first gap, and it is beneficial to prevent the signal on the first routing line from being transmitted to the first part of the second routing line through the second gap. Thus, it is beneficial to ensure the accuracy of the signal transmitted between the first part of the first routing line and the third part of the second routing line. In addition, when preparing array substrates of different shapes, it is possible to avoid redeveloping all the film layers of the public size array substrate, reducing the development time and cost of the array substrate, providing conditions for achieving arbitrary cutting to a certain extent, and improving the efficiency of preparing array substrates of different shapes. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0012] Figure 1 A schematic plan view of an array substrate provided in an embodiment of the present application;

[0013] Figure 2 A schematic plan view of a public version array substrate provided in an embodiment of the present application;

[0014] Figure 3 A cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application;

[0015] Figure 4 A method provided in the embodiment of the present application Figure 1 Schematic diagram of the cross section along the A-A' direction;

[0016] Figure 5 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0017] Figure 6 A method provided in the embodiment of the present application Figure 5 Schematic diagram of the cross section along the B-B' direction;

[0018] Figure 7 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0019] Figure 8 A method provided in the embodiment of the present application Figure 7 Schematic diagram of the cross section along the C-C' direction;

[0020] Fig. 9 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0021] Fig.10 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application;

[0022] Fig.11 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0023] Fig.12 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0024] Fig.13 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0025] Fig.14 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction;

[0026] Fig.15 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction;

[0027] Fig.16 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction;

[0028] Fig.17 A schematic plan view of another array substrate provided in an embodiment of the present application;

[0029] Fig.18 A schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0032] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0033] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0034] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0035] It should be understood that although the terms first, second, etc. may be used to describe areas, parts, gaps, routing, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish areas, parts, gaps, routing, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first area may also be referred to as the second area, and similarly, the second area may also be referred to as the first area. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0036] Figure 1 A schematic plan view of an array substrate provided in an embodiment of the present application, Figure 2 A schematic plan view of a public version array substrate provided in an embodiment of the present application, Figure 3 A cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application, Figure 4 A method provided in the embodiment of the present application Figure 1 Schematic diagram of the cross section along the A-A' direction, Figure 5 A schematic plan view of another array substrate provided in an embodiment of the present application, Figure 6 A method provided in the embodiment of the present application Figure 5 Schematic diagram of the cross section along the B-B' direction, Figure 7 A schematic plan view of another array substrate provided in an embodiment of the present application, Figure 8 A method provided in the embodiment of the present application Figure 7 Schematic diagram of the cross section along the C-C' direction.

[0037] The present application embodiment provides an array substrate 100, such as Figure 1 As shown, the array substrate 100 includes a first area A0 and a second area B0 surrounding the first area A0, and the edge of the second area B0 away from the first area A0 is reused as the edge P1 of the array substrate 100. When preparing array substrates 100 of different sizes and shapes, Figure 2As shown, the array substrate 100 ′ of the standard size needs to be cut, and the cut edge P2 is the edge P1 of the array substrate 100 .

[0038] The array substrate 100 includes a substrate 10, and other film layers are prepared on the basis of the substrate 10. The array substrate 100 also includes a first trace 20, and the first trace 20 is located on one side of the substrate 10, and the first end 201 of at least part of the first trace 20 coincides with the edge of the array substrate 100. When preparing the first trace 20, the first trace 20 is prepared on the entire surface of the public size array substrate 100', so when the array substrate 100 is obtained along the cutting edge P2, there is a situation where the cutting edge P1 passes through the first trace 20, and then the first end 201 of at least part of the first trace 20 in the array substrate 100 cut along the cutting edge P1 will coincide with the edge P2 of the array substrate 100.

[0039] The second routing line 30 is located on the side of the film layer where the first routing line 20 is located away from the substrate 10, and the second end 301 of at least part of the second routing line 30 coincides with the edge P1 of the array substrate 100. Similarly, when preparing the second routing line 30, the second routing line 30 is prepared on the entire surface of the public size array substrate 100', so when the array substrate 100 is obtained along the cutting edge P2, there is a situation where the cutting edge P2 passes through the second routing line 30, and then the second end 301 of at least part of the second routing line 30 in the array substrate 100 cut along the cutting edge P2 will coincide with the edge of the array substrate 100.

[0040] A first insulating layer 40 is included between the first wiring 20 and the second wiring 30. The first wiring 20 and the second wiring 30 are located in two adjacent film layers. The first insulating layer 40 is used to prevent short circuits between the first wiring 20 and the second wiring 30. In a direction perpendicular to the plane where the array substrate 100 is located, at least a portion of the first end 201 overlaps at least a portion of the second end 301.

[0041] When the public size array substrate 100' is cut arbitrarily to obtain a special-shaped array substrate 100, since the first wiring 20 and the second wiring 30 between different film layers have overlapping parts in the direction perpendicular to the plane where the array substrate 100 is located, and the overlapping part of the wiring coincides with the cutting edge P2, after cutting along the cutting edge P2, the first end 201 of part of the first wiring 20 and the second end 301 of part of the second wiring 30 overlap, as shown in FIG. Figure 3 As shown, there is a risk of material residue at the cutting edge P2 between the first end 201 and the second end 301 due to cutting factors, which may cause a short circuit between the first routing 20 and the second routing 30 located in different film layers, resulting in a deviation in the transmission signal between the first routing 20 and the second routing 30, causing the risk of equipment failure.

[0042] In order to avoid the signal crosstalk problem caused by the short circuit between the first wiring 20 and the second wiring 30, Figure 1 , Figure 4 As shown, the technical solution of the present application proposes to set the first routing line 20 to include a first portion 20A and a second portion 20B that have the same extension direction and are not connected, the first portion 20A is at least partially located in the first area A0, the second portion 20B is located in the second area B0, the first portion 20A and the second portion 20B are aligned in the extension direction of the first portion 20A, and a first gap 20C is included between the first portion 20A and the second portion 20B. If the first portion 20A and the second portion 20B of the first routing line 20 include a first gap 20C, the first routing line 20 is a discontinuous routing line, and the signal transmitted on the first routing line 20 will be disconnected between the first portion 20A and the second portion 20B, so that when the second portion 20B of the first routing line 20 close to the edge is short-circuited, the accuracy of the signal transmission of the first portion 20A will not be affected, which provides conditions for arbitrarily cutting the public version size array substrate 100' and reducing the risk of routing short circuit.

[0043] The first gap 20C is located between the first portion 20A and the second portion 20B, and the first gap 20C may be located in a portion of the first area A0 close to the second area B0, or the first gap 20C may be located in a portion of the second area B0 close to the first area A0. Optionally, the first gap 20C is located in the second area B0, and the first gap 20C is adjacent to an edge of the first area A0 in the extension direction of the first portion 20A.

[0044] Or, combined Figure 5 , Figure 6 As shown, the second routing line 30 includes a third portion 30A and a fourth portion 30B which extend in the same direction and are not connected, the third portion 30A is at least partially located in the first area A0, the fourth portion 30B is located in the second area B0, and a second gap 30C is included between the third portion 30A and the fourth portion 30B. At this time, there is a second gap 30C on the second routing line 30, and there is no gap on the first routing line 20, and the first routing line 20 is a continuous routing line. Similarly, the second gap 30C is included between the third portion 30A and the fourth portion 30B of the second routing line 30, then the second routing line 30 is a discontinuous routing line, and the signal transmitted on the second routing line 30 will be disconnected between the third portion 30A and the fourth portion 30B, so that when there is a short circuit in the fourth portion 30B near the edge of the second routing line 30, the accuracy of the signal transmission of the third portion 30A will not be affected, which provides conditions for arbitrarily cutting the array substrate of standard size and reducing the risk of routing short circuit.

[0045] The second gap 30C is located between the third portion 30A and the fourth portion 30B, and the second gap 30C may be located in a portion of the first area A0 close to the second area B0, or the second gap 30C may be located in a portion of the second area B0 close to the first area A0. Optionally, the second gap 30C is located in the second area B0, and the second gap 30C is adjacent to the edge of the first area A0 in the extension direction of the third portion 30A.

[0046] In addition, combined Figure 7 , Figure 8 As shown, the array substrate 100 is provided to include a first gap 20C and a second gap 30C. The first wiring 20 is provided to include a first portion 20A and a second portion 20B, and the first portion 20A and the second portion 20B include a first gap 20C. At the same time, the second wiring 30 is provided to include a third portion 30A and a fourth portion 30B, and the third portion 30A and the fourth portion 30B include a second gap 30C. This is conducive to further improving and reducing the risk of inaccurate signal transmission caused by short circuits between the first wiring 20 and the second wiring 30 after cutting.

[0047] As can be seen from the above content, in order to avoid the short circuit problem caused by cutting the public version size array substrate 100' affecting the signal transmission accuracy of the first routing line 20 and the second routing line 30, the first gap 20C is set in the first routing line 20 and / or the second gap 30C is set in the second routing line 30. At this time, when the first gap 20C and / or the second gap 30C are arbitrarily cut at a position away from the first area A0, the signal transmission problem caused by the cutting short circuit can be avoided, which is conducive to providing conditions for realizing the arbitrary cutting of the public version size array substrate 100' to obtain an array substrate 100 with various shapes and stable working performance. In addition, when adjusting the public version size array substrate 100', only the film layer where one of the routing lines is located (the film layer where the first routing line 20 is located or the film layer where the second routing line 30 is located) can be adjusted, and there is no need to redevelop all the film layers of the public version size array substrate 100', and there is no need to design the routing lines of multiple film layers to avoid cutting along the cutting edge P2.

[0048] In the embodiment of the present application, the first line 20 is provided to include a first gap 20C, and / or the second line 30 is provided to include a second gap 30C, so that if the first end 201 of the first line 20 and the second end 301 of the second line 30 overlap at the edge of the array substrate 100 and there is a short circuit caused by metal residue, it is beneficial to prevent the signal on the second line 30 from being transmitted to the first portion 20A of the first line 20 through the first gap 20C, and it is beneficial to prevent the signal on the first line 20 from being transmitted to the first portion 30A of the second line 30 through the second gap 30C. Therefore, it is beneficial to ensure the accuracy of the signal transmission from the first portion 20A of the first line 20 to the third portion 30A of the second line 30. In addition, when preparing array substrates 100 of different shapes, it is possible to avoid redeveloping all the film layers of the public size array substrate 100', reducing the development time and cost of the array substrate 100, providing conditions for achieving arbitrary cutting to a certain extent, and improving the efficiency of preparing array substrates 100 of different shapes.

[0049] In one embodiment of the present application, continue to refer to Figure 1 , Figure 5 , Figure 7 As shown, a plurality of first gaps 20C are arranged along the extending direction of the edge P1 of the array substrate 100 ; and / or a plurality of second gaps 30C are arranged along the extending direction of the edge P1 of the array substrate 100 .

[0050] In the embodiment of the present application, the first gap 20C and / or the second gap 30C are arranged in the extending direction of the edge P1 of the array substrate 100, which is conducive to making the first gap 20C and / or the second gap 30C located near the edge P1. Optionally, the first gap 20C and / or the second gap 30C are both located in the second area B0, which is conducive to avoiding the first gap 20C and / or the second gap 30C being closer to the middle position of the first area A0, thereby causing the first portion 20A of the effective signal transmission part in the first wiring 20 to be shorter, or causing the third portion 30A of the effective signal transmission part in the second wiring 30 to be shorter, resulting in a smaller area range in the array substrate 100 that can work normally. Therefore, preparing the first gap 20C and the second gap 30C along the edge of the array substrate 100 is conducive to increasing the area range in the array substrate 100 that can work normally, thereby improving the display effect of the display panel prepared by the array substrate 100.

[0051] In addition, the first gap 20C and / or the second gap 30C are arranged along the extension direction of the edge P1 of the array substrate 100, that is, along the cutting edge P2 of the public size array substrate 100', which is conducive to ensuring that the first gap 20C and / or the second gap 30C are located on the side of the cutting edge P2 close to the array substrate 100, avoiding the gap being mistakenly cut off during cutting due to improper positioning, ensuring its effectiveness in cutting off signal crosstalk, and thus ensuring the stable operation of the cut array substrate 100.

[0052] Fig. 9 A schematic plan view of another array substrate provided in an embodiment of the present application.

[0053] In one embodiment of the present application, Figure 7 , Fig. 9 As shown, the array substrate 100 includes a first gap 20C and a second gap 30C.

[0054] In the embodiments of the present application, Figure 7 As shown, in the direction perpendicular to the plane where the array substrate 100 is located, part of the first gap 20C overlaps part of the second gap 30C, and part of the first gap 20C does not overlap part of the second gap 30C. The first gap 20C and the second gap 30C can be adaptively set according to the extension direction of the cutting edge P2 and the positions of the first routing line 20 and the second routing line 30 through which the cutting edge P2 passes. Setting part of the first gap 20C and part of the second gap 30C to overlap is conducive to reducing the number of crossover overlaps between the first routing line 20 and the second routing line 30 near the cutting edge P2, thereby reducing the risk of short circuit between the first routing line 20 and the second routing line 30. Setting part of the first gap 20C and part of the second gap 30C to not overlap is conducive to dispersing the gaps, increasing the probability of being able to cut off the crosstalk signal, and improving the efficiency of using the gaps.

[0055] or, as Fig. 9 As shown, in a direction perpendicular to the plane where the array substrate 100 is located, the first gap 20C and the second gap 30C are arranged without overlap, which is beneficial to increase the area of ​​the multiple gaps for wiring isolation on the plane parallel to the array substrate 100, thereby increasing the ability of the gaps to isolate crosstalk signals, improving the availability of the gaps, and improving the reliability of the array substrate 100 with stable functions obtained by cutting the public version size array substrate 100' at will.

[0056] In one embodiment of the present application, continue to refer to Figure 1 , Figure 5 , Figure 7As shown, on a plane parallel to the array substrate 100, the extension directions of the first routing line 20 and the second routing line 30 intersect. The first routing line 20 and the second routing line 30 are located in two adjacent film layers, and setting the extension directions of the first routing line 20 and the second routing line 30 to intersect is conducive to reducing the overlapping area between the first routing line 20 and the second routing line 30, thereby reducing electromagnetic interference and crosstalk between the routing lines, and is also conducive to reducing the risk of short circuit between the first routing line 20 and the second routing line 30 between the film layers.

[0057] In addition, if the extension directions of the first line 20 and the second line 30 are arranged to intersect, the first line 20 and the second line 30 overlap at the intersection position of the first line 20 and the second line 30, and the area where the first line 20 and the second line 30 do not intersect only includes the first line 20 or the second line, and the edge P1 of the array substrate 100 is likely to short-circuit the first line 20 and the second line 30 when passing through the intersection position, but it is not easy to short-circuit the first line 20 and the second line 30 when passing through other non-intersecting areas. Therefore, setting the extension directions of the first line 20 and the second line 30 to intersect is conducive to having a partial non-intersecting area between the first line 20 and the second line 30, so that the area where the edge P1 of the array substrate 100 passes includes a non-intersecting area, thereby reducing the risk of the short circuit of the intersection of the first line 20 and the second line 30 affecting the working performance of the array substrate 100.

[0058] In some other embodiments, the extension directions of the first wiring 20 and the second wiring 30 may be set to be the same and parallel to the plane where the array substrate 100 is located.

[0059] Fig.10 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application.

[0060] In one embodiment of the present application, Fig.10 As shown, the array substrate 100 includes a transistor M1, the transistor M1 includes a gate G1, and the first wiring 20 and the gate G1 are located in the same film layer. The first wiring 20 can be used to transmit a control signal to the gate of the transistor M1, and optionally, the first wiring 20 includes a gate scanning line.

[0061] Usually, the power lines in the array substrate 100 are distributed in a mesh shape. Optionally, the first wiring 20 also includes a first power line PVDD and a second power line PVEE. The first power line PVDD can provide a positive driving voltage for the array substrate 100, and the second power line PVEE can provide a negative driving voltage for the array substrate 100.

[0062] The transistor M1 further includes a source S1 and a drain D1, and the second wiring 30 is electrically connected to the source S1 or the drain D1 of the transistor M1. The source S1 and the drain D1 of the transistor M1 are usually used to input and output signals. Optionally, the second wiring 30 includes a data line, and the data line is electrically connected to one of the source S1 or the drain D1 of the transistor M1. The other of the source S1 or the drain D1 of the transistor M1 is electrically connected to the light-emitting device D2 in the display panel to drive the light-emitting device D2 to emit light.

[0063] As can be seen from the above content, the power lines in the array substrate 100 are distributed in a mesh shape, and the extension directions of the first wiring 20 and the second wiring 30 intersect. Optionally, the second wiring 30 also includes a first power line PVDD and a second power line PVEE. The first power line PVDD can provide a positive driving voltage for the array substrate 100 to work, and the second power line PVEE can provide a negative driving voltage for the array substrate 100 to work.

[0064] Fig.11 A schematic plan view of another array substrate provided in an embodiment of the present application, Fig.12 A schematic plan view of another array substrate provided in an embodiment of the present application is shown in FIG. Fig.13 A schematic plan view of another array substrate provided in an embodiment of the present application.

[0065] In one embodiment of the present application, Fig.11 As shown, the gate G1 of the transistor M1 in the first area A0 is connected to the first portion 20A of the first wiring 20, and the gate G1 of the transistor M1 in the second area B0 is connected to the second portion B0 of the same first wiring 20. The array substrate 100 includes a plurality of transistors M1, including a plurality of transistors M1 electrically connected to the same first wiring 20. When the first wiring 20 includes the first gap 20C, the first wiring 20 is divided into a first portion 20A and a second portion 20B, so that the plurality of transistors M1 arranged along the extension direction of the first wiring 20 and electrically connected to the same first wiring 20 are electrically connected to the first portion 20A and the second portion 20B, respectively.

[0066] On the first wiring 20, optionally, the first portion 20A of the first wiring 20 can transmit normal working signals, while the second portion 20B cannot transmit normal working signals. Then, the plurality of transistors M1 electrically connected to the first portion 20A can receive working signals and work, while the transistors M1 electrically connected to the second portion 20B cannot work normally.

[0067] Furthermore, the source S1 or the drain D1 of the transistor M1 in the first area A0 is electrically connected to the third portion 30A of the second routing line 30, and the source S1 or the drain D1 of the transistor M1 in the second area B09 is electrically connected to the fourth portion 30B of the second routing line 30. The array substrate 100 includes a plurality of transistors M1, including a plurality of transistors M1 electrically connected to the same second routing line 30. When the second routing line 30 includes a second gap 30C, the second routing line 30 is divided into a third portion 30A and a fourth portion 30B, so that the source S1 or the drain D1 of the plurality of transistors M1 arranged along the extension direction of the second routing line 30 and electrically connected to the same second routing line 30 are electrically connected to the third portion 30A and the fourth portion 30B, respectively.

[0068] On the second wiring 30, the third portion 30A of the second wiring 30 can transmit normal working signals, while the fourth portion 30B cannot transmit normal working signals. Then, the plurality of transistors M1 electrically connected to the third portion 30A can receive accurate signals for transmission, while the transistor M1 electrically connected to the second portion 30B may receive inaccurate signals for transmission, but such inaccurate signals will be blocked by the gap from being transmitted to the third portion 30A.

[0069] like Fig.12 As shown, the gate G1 of the transistor M1 in the first area A0 is connected to the first portion 20A of the first wiring 20, and the gate G1 of the transistor M1 in the second area B0 is connected to the second portion B0 of the same first wiring 20. In addition, the source S1 and the drain D1 of some transistors M1 in the first area A0 and the second area B0 are electrically connected to the continuous second wiring 30.

[0070] like Fig.13 As shown, the source S1 or drain D1 of the transistor M1 in the first area A0 is electrically connected to the third portion 30A of the second wiring 30, and the source S1 or drain D1 of the transistor M1 in the second area B09 is electrically connected to the fourth portion 30B of the second wiring 30. In addition, the gates G1 of some transistors M1 in the first area A0 and the second area BO are electrically connected to the continuous first wiring 20.

[0071] In one embodiment of the present application, continue to refer to Figure 1 As shown, the shift register circuit 200 is located in the first area A0. The shift register circuit 200 can transmit a control signal to the array substrate 100. The signal transmitted by the shift register circuit 200 can control the on-off state of the transistor M1, thereby controlling the operation of the array substrate 100. Figure 2 As shown, the public size array substrate 100 ′ includes a border during preparation, and a driving chip is included in the border. The driving chip can control multiple cascaded shift register circuits 200 to start in sequence and output control signals.

[0072] In the related art, the shift register circuit is usually prepared near the edge of the public size array substrate 100'. When the public size array substrate 100' is cut to obtain a special-shaped array substrate, there is a risk of cutting and removing the shift register circuit located at the frame position, resulting in the obtained special-shaped array substrate having no shift register drive control and being unable to work normally.

[0073] In the embodiment of the present application, the first area A0 in the cut array substrate 100 is a reserved area, and the first wiring 20 and the second wiring 30 in the first area A0 are continuous wirings, so the signal transmission capability remains normal, so that the first area A0 can be an area for normal display work. The shift register circuit 200 is arranged in the first area A0, which is conducive to avoiding the shift register circuit 200 from being removed during cutting, thereby ensuring that the cut array substrate 100 can work normally under the driving control of the shift register circuit 200, and ensuring the product yield of the array substrate 100.

[0074] In one embodiment of the present application, continue to refer to Figure 1 As shown, the array substrate 100 includes a first symmetry axis X1, and the extension direction of the first symmetry axis X1 is the same as the extension direction of the second wiring 20. The areas of the two opposite sides of the array substrate 100 relative to the first symmetry axis X1 are similar. It can be seen from the above embodiment that the second wiring 30 can be used to transmit data voltage signals, and the first wiring 20 can be used to transmit scanning signals and other signals for controlling the on-off of the transistor M1. Optionally, the output end of the shift register circuit 200 is electrically connected to the first wiring 20, and the signal transmitted by the first wiring 20 can be obtained from the shift register circuit 200.

[0075] In the embodiment of the present application, the first symmetry axis X1 is set to pass through the area where the shift register circuit 200 is located, so that the shift register circuit 200 can be arranged in sequence in the direction of the second wiring 20, which is conducive to allowing multiple shift register circuits 200 to transmit scanning signals, etc. to the first wiring 20 arranged in sequence along the extension direction of the second wiring 20. In addition, the first symmetry axis X1 is set to pass through the area where the shift register 200 is located, which is conducive to ensuring that the shift register circuit 200 is located in the first area A0, and further, it is conducive to allowing the shift register circuit 200 to be located as much as possible in the middle of the array substrate 100, thereby further avoiding the shift register circuit 200 located in the first area A0 from being cut.

[0076] In one embodiment of the present application, continue to refer to Figure 4 , Figure 6 , Figure 8As shown, along the direction perpendicular to the plane where the array substrate 100 is located, the thickness H1 of the first insulating layer 40 is less than or equal to 10μm. It can be seen from the above embodiment that the first insulating layer 40 is located between the film layers where the first wiring 20 and the second wiring 30 are located, and can be used to ensure interlayer insulation between adjacent wirings. When the first insulating layer 40 between the film layers where two adjacent wirings are located is small, when the public size array substrate 100' is cut to obtain an irregular array substrate 100, the cutting action is likely to cause part of the wiring material at the first end 201 of the first wiring 20 to remain, and the residual material extends toward the second end 301 of the second wiring 30, or it is likely to cause part of the wiring material at the second end 301 of the second wiring 30 to remain, and the residual material extends toward the first end 201 of the first wiring 20. Furthermore, if the film thickness between the first routing line 20 and the second routing line 30 is relatively small, it is easy for the residual material after cutting to contact each other, causing the first end 201 of the first routing line 20 to contact and electrically connect with the second end 301 of the second routing line 30, thereby causing the risk of electrical connection between the first routing line 20 and the second routing line 30, resulting in signal transmission errors.

[0077] In the embodiment of the present application, when the thickness of the first insulating layer 40 is less than or equal to 10 μm, a first gap 20C may be provided on the first wiring 20, and / or a second gap 30C may be provided on the second wiring 30, so as to reduce the influence of the first wiring 20 and the second wiring 30 on the transmission of the signal after being electrically connected at the cutting edge. At this time, providing the first gap 20C and / or the second gap 30C is conducive to cutting off the electrical connection path between the first wiring 20 and the second wiring 30, and avoiding signal crosstalk. The embodiment of the present application is also conducive to providing certain reference conditions for the implementation of the technical solution of the present application, and is conducive to improving the availability of the technical solution.

[0078] Fig.14 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction, Fig.15 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction, Fig.16 Another embodiment provided in this application is Figure 1 Schematic diagram of the cross section along the A-A' direction.

[0079] In one embodiment of the present application, Fig.14 As shown, the array substrate 100 further includes a second insulating layer 50, and the second insulating layer 50 is located on a side of the second wiring 30 away from the substrate 10, or as shown in FIG. Fig.15 As shown, the array substrate 100 includes a third insulating layer 60 , and the third insulating layer 60 is located on a side of the first trace 20 facing the substrate 10 .

[0080] Or, if Fig.16As shown, the array substrate 100 further includes a second insulating layer 50 and a third insulating layer 60 . The second insulating layer 50 is located on a side of the second wiring 30 away from the substrate 10 , and the third insulating layer 60 is located on a side of the first wiring 20 toward the substrate 10 .

[0081] Optionally, the second insulating layer 50 may be located between the second routing line 30 and the film layer where other routing lines are located. Optionally, the third insulating layer 60 may be located between the first routing line 20 and the film layer where other routing lines on the side facing the substrate 10 are located. Thus, the first insulating layer 40 and the second insulating layer 50 and the third insulating layer 60 can all ensure that the routing lines are insulated between the film layers.

[0082] refer to Fig.14 As shown, along the direction perpendicular to the plane where the array substrate 100 is located, the thickness H1 of the first insulating layer 40 is less than the thickness H2 of the second insulating layer 50. Fig.15 As shown, along the direction perpendicular to the plane where the array substrate 100 is located, the thickness H1 of the first insulating layer 40 is less than the thickness H3 of the third insulating layer 60. Fig.16 As shown, the array substrate 100 includes a second insulating layer 50 and a third insulating layer 60 . Along a direction perpendicular to the plane where the array substrate 100 is located, a thickness H1 of the first insulating layer 40 is smaller than a thickness H2 of the second insulating layer 50 and smaller than a thickness H3 of the third insulating layer 60 .

[0083] Optionally, the array substrate 100 includes a second insulating layer 50 and a third insulating layer 60 , and along a direction perpendicular to the plane of the array substrate 100 , a thickness H1 of the first insulating layer 40 is smaller than a thickness H2 of the second insulating layer 50 and a thickness H3 of the third insulating layer 60 .

[0084] It can be seen from this that when the thickness of the first insulating layer 40 is smaller than at least one of the second insulating layer 50 and the third insulating layer 60, the thickness of the first insulating layer 40 is relatively small at this time, and a first gap 20C and / or a second gap 30C can be set on the second routing 20 and the third routing 30, which is beneficial to avoid signal crosstalk between the first routing 20 and the third routing 30 and reduce the risk of malfunction of the array substrate 100.

[0085] Optionally, in a direction perpendicular to the plane of the array substrate 100, the wiring on opposite sides of the second insulating layer 50 can be set to be discontinuous, and a gap is set when the wiring extends to the second area B0, so as to avoid signal crosstalk between the second wiring 30 and other wirings.

[0086] Optionally, in a direction perpendicular to the plane of the array substrate 100, the wiring on opposite sides of the third insulating layer 60 can be set to be discontinuous, and a gap is set when the wiring extends to the second area B0, so as to avoid signal crosstalk between the first wiring 20 and other wirings.

[0087] In the embodiment of the present application, when the first insulating layer 40 is smaller than at least one of the second insulating layer 50 and the third insulating layer 60, a first gap 20C and / or a second gap 30C are provided at the first wiring 20 and the second wiring 30 on opposite sides of the first insulating layer 40, which is conducive to ensuring signal crosstalk between the first wiring 20 and the second wiring 30. In addition, the embodiment of the present application is conducive to providing reference conditions for the execution of the solution, thereby improving the availability of the technical solution of the present application.

[0088] In one embodiment of the present application, Figure 1 As shown, the array substrate 100 includes the first gap 20C but does not include the second gap 30C. In the extension direction of the first portion 20A, the length of the second portion 20B is L1, and L1 ≥ 100 μm. Figure 5 As shown, the array substrate 100 includes the second gap 30C but does not include the first gap 20C. In the extension direction of the third portion 30A, the length of the fourth portion 30B is L2, and L2 ≥ 100 μm.

[0089] Or, if Figure 7 As shown, the array substrate 100 includes a first gap 20C and a second gap 30C. In the extension direction of the first portion 20A, the length of the second portion 20B is L1, L1≥100μm, and in the extension direction of the third portion 30A, the length of the fourth portion 30B is L2, L2≥100μm.

[0090] In the embodiment of the present application, the length of the second portion 20B is the distance between the first gap 20C and the edge of the array substrate 100 in the extension direction of the first portion 20A, and the length of the fourth portion 30B is the distance between the second gap 30C and the edge of the array substrate 100 in the extension direction of the third portion 30A. As can be seen from the above content, the array substrate 100 is obtained by cutting on the public size array substrate 100', and the edge P1 of the array substrate 100 is the cutting edge P2. In the process of cutting the array substrate 100, the cutting edge P2 can be first determined according to the target shape on the public size array substrate 100', and then the film layer where the first wiring 20 is located and / or the second wiring 30 are disconnected, that is, the first gap is set at a position at least 100μm away from the cutting edge on the first wiring 20, and / or the second gap 30C is set at a position at least 100μm away from the cutting edge on the second wiring 30. In this way, when preparing the special-shaped array substrate 100, it is only necessary to change the film layer where one routing line is located to avoid the signal crosstalk problem between the first routing line 20 and the second routing line 30. Compared with the related technology of avoiding routing lines on the film layer where multiple routing lines are located according to the cutting edge P2, the work efficiency when cutting the array substrate 100 is improved.

[0091] In addition, setting the length L1 of the second portion 20B and / or the length L2 of the fourth portion 30B to be greater than or equal to 100 μm helps reduce the possibility of cutting the first portion 20A or the third portion 30A due to errors during cutting, thereby helping to ensure the effectiveness of the first gap 20C and / or the second gap 30C.

[0092] In one embodiment of the present application, referring to 1, the array substrate 100 includes the first gap 20C but does not include the second gap 30C, and the length of the first gap 20C corresponding to the first portion 20A is W1; W1 ≥ 2 μm. Figure 5 As shown, the array substrate 100 includes the second gap 30C but does not include the first gap 20C. In the extension direction of the third portion 30A, the length of the second gap 30C corresponding to the third portion 30A is W2; W2 ≥ 2 μm.

[0093] Or, continue to refer to Figure 7 As shown, the array substrate 100 includes a first gap 20C and a second gap 30C, the length of the first gap 20C corresponding to the first portion 20A is W1; W1≥2μm, and in the extension direction of the third portion 30A, the length of the second gap 30C corresponding to the third portion 30A is W2; W2≥2μm.

[0094] In the embodiment of the present application, insulating material is included at the first gap 20C and the second gap 30C, and the length W1 of the first gap 20C and / or the length W2 of the second gap 30C are set to be greater than or equal to 2μm, which is beneficial to avoid the distance between the first part 20A and the second part 20B being too close to cause a short circuit, and is beneficial to ensure the effectiveness of the first gap 20C, so that the first part 20A and the second part 20B are electrically insulated; and / or, it is beneficial to avoid the distance between the third part 30A and the fourth part 30B being too close to cause a short circuit, and is beneficial to ensure the effectiveness of the second gap 30C, so that the third part 30A and the fourth part 30B are electrically insulated.

[0095] In one embodiment of the present application, continue to refer to Figure 1 As shown, the array substrate 100 includes the first gap 20C but does not include the second gap 30C, and the distance between two adjacent second wirings 30 is S1; S1 ≥ 10 μm. Figure 5 As shown, the array substrate 100 includes the second gap 30C but does not include the first gap 20C, and the distance between two adjacent first wirings 20 is S2, where S2 ≥ 10 μm.

[0096] Or, continue to refer to Figure 7As shown, the array substrate 100 includes a first gap 20C and a second gap 30C, the distance between two adjacent second wirings 30 is S1; S1 ≥ 10 μm, and the distance between two adjacent first wirings 20 is S2, S2 ≥ 10 μm.

[0097] like Figure 1 As shown, when the first line 20 includes the first gap 20C, if the cutting position falls into the first gap 20C due to the cutting error, although there is no first line 20 at the first gap 20C, the second line 30 will be cut, and part of the material of the second line 30 may remain and extend into the first gap 20C, thereby causing the risk of short circuit between the second line 30 and the first part 20A of the first line 20. Therefore, setting the distance S1 between two adjacent second lines 30 ≥ 10μm is conducive to reducing the situation where the second line 30 intersecting the extension direction of the first line 20 falls into the first gap 20C, and reducing the short circuit risk caused by the overlap between the first gap 20C and the second line 30 and the cutting error. It is conducive to further reducing the risk of signal crosstalk between the first line 20 and the second line 30 during cutting, and improving the product yield of the array substrate 100.

[0098] Likewise, if Figure 5 As shown, when the second line 30 includes the second gap 30C, if the cutting position falls into the second gap 30C due to cutting error, although there is no second line 30 at the second gap 30C, the first line 20 will be cut, and part of the material of the first line 20 may remain and extend into the second gap 30C, thereby causing the risk of short circuit between the first line 20 and the first part 30A of the third line 30. Setting the distance S2 between two adjacent first lines 20 ≥ 10μm is conducive to reducing the situation where the first line 20 intersecting the extension direction of the second line 30 falls into the second gap 30C, and reducing the short circuit risk caused by the overlap and cutting between the second gap 30C and the first line 20.

[0099] In the embodiment of the present application, the distance between two adjacent second routings 30 is set to S1, S1 ≥ 10 μm, and / or the distance between two adjacent first routings 20 is set to S2, S2 ≥ 10 μm, which is beneficial to further reduce the risk of crosstalk between the signals of the first routing 20 and the second routing 30, and is also beneficial to make the distance between the two adjacent first routings 20 a safe distance, and the distance between the two adjacent second routings 30 a safe distance, thereby reducing the risk of short circuit between the two adjacent first routings 20, and reducing the risk of short circuit between the two adjacent second routings 30.

[0100] Fig.17 A schematic plan view of another array substrate provided in an embodiment of the present application.

[0101] In the technical solution of the present application, the first gap 20C and the second gap 30C set in the embodiment of the present application realize a certain degree of arbitrary cutting on the public version size array substrate 100', and can effectively ensure the normal operation of the array substrate 100 after cutting. It should be noted that, if Fig.17 As shown, array substrates 100 of different shapes can also be obtained by splicing multiple array substrates 100 , and the multiple array substrates 100 can be cut on a public array substrate 100 ′ according to the solution of the embodiment of the present application and then spliced.

[0102] Fig.18 A schematic diagram of a display panel provided in an embodiment of the present application.

[0103] The present application embodiment provides a display panel 300, such as Fig.18 As shown, the display panel 300 includes the array substrate 100 provided in the above embodiment. The display panel 300 can be used for display work, and the display panel 300 can be applied to devices including display functions such as televisions, computers, and mobile phones.

[0104] In the display panel 300, the first wiring 20 is provided to include a first gap 20C, and / or the second wiring 30 is provided to include a second gap 30C, so that if the first end 201 of the first wiring 20 and the second end 301 of the second wiring 30 overlap at the edge of the array substrate 100 and there is a short circuit caused by metal residue, it is beneficial to prevent the signal on the second wiring 30 from being transmitted to the first portion 20A of the first wiring 20 through the first gap 20C, and it is beneficial to prevent the signal on the first wiring 20 from being transmitted to the first portion 30A of the second wiring 30 through the second gap 30C. Therefore, it is beneficial to ensure the accuracy of the signal transmission from the first portion 20A of the first wiring 20 to the third portion 30A of the second wiring 30. In addition, when preparing array substrates 100 of different shapes, it is possible to avoid redeveloping all the film layers of the public size array substrate 100', reducing the development time and cost of the array substrate 100, providing conditions for achieving arbitrary cutting to a certain extent, and improving the efficiency of preparing array substrates 100 of different shapes.

[0105] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a first area and a second area surrounding the first area, wherein an edge of the second area away from the first area is reused as an edge of the array substrate; the array substrate comprises: substrate; A first routing line is located at one side of the substrate, and a first end of at least part of the first routing line coincides with an edge of the array substrate; The second routing line is located on a side of the film layer where the first routing line is located away from the substrate, and at least a portion of the second end of the second routing line overlaps with an edge of the array substrate; a first insulating layer is included between the first routing line and the second routing line; along a direction perpendicular to the plane where the array substrate is located, at least a portion of the first end overlaps with at least a portion of the second end; The first wiring includes a first portion and a second portion extending in the same direction and being unconnected, the first portion is at least partially located in the first area, the second portion is located in the second area, and a first gap is included between the first portion and the second portion; and / or, The second trace includes a third portion and a fourth portion extending in the same direction and not connected, the third portion is at least partially located in the first area, the fourth portion is located in the second area, and a second gap is included between the third portion and the fourth portion.

2. The array substrate according to claim 1, characterized in that: A plurality of the first gaps are arranged along an extension direction of an edge of the array substrate; and / or a plurality of the second gaps are arranged along an extension direction of an edge of the array substrate.

3. The array substrate according to claim 1, characterized in that: The array substrate includes the first gap and the second gap; wherein, in a direction perpendicular to the plane where the array substrate is located, part of the first gap overlaps with part of the second gap, and part of the first gap does not overlap with part of the second gap; or, in a direction perpendicular to the plane where the array substrate is located, the first gap does not overlap with the second gap.

4. The array substrate according to claim 1, characterized in that: On a plane parallel to the array substrate, the extension directions of the first routing line and the second routing line intersect with each other.

5. The array substrate according to claim 1, characterized in that: The array substrate includes a transistor, the transistor includes a gate, and the first wiring and the gate are located in the same film layer; The transistor further includes a source and a drain, and the second wiring is electrically connected to the source or the drain of the transistor.

6. The array substrate according to claim 5, characterized in that: The gate of the transistor in the first region is connected to the first portion of the first routing line, and the gate of the transistor in the second region is connected to the second portion of the same first routing line; And / or, the source or drain of the transistor in the first region is electrically connected to the third portion of the second routing line, and the source or drain of the transistor in the second region is electrically connected to the fourth portion of the second routing line.

7. The array substrate according to claim 1, characterized in that: The shift register circuit is located in the first area.

8. The array substrate according to claim 7, characterized in that: The array substrate comprises a first symmetry axis, and an extension direction of the first symmetry axis is the same as an extension direction of the second wiring; wherein the first symmetry axis passes through a region where the shift register circuit is located.

9. The array substrate according to claim 1, characterized in that: Along a direction perpendicular to the plane where the array substrate is located, the thickness of the first insulating layer is less than or equal to 10 μm.

10. The array substrate according to claim 1, characterized in that: The array substrate further includes a second insulating layer, which is located on a side of the second wiring away from the substrate, and / or the array substrate further includes a third insulating layer, which is located on a side of the first wiring facing the substrate; In which, along a direction perpendicular to the plane where the array substrate is located, the thickness of the first insulating layer is less than the thickness of the second insulating layer, and / or, along a direction perpendicular to the plane where the array substrate is located, the thickness of the first insulating layer is less than the thickness of the third insulating layer.

11. The array substrate according to claim 1, characterized in that: In the extension direction of the first portion, the length of the second portion is L1, L1≥100 μm, and / or, in the extension direction of the third portion, the length of the fourth portion is L2, L2≥100 μm.

12. The array substrate according to claim 1, characterized in that: In the extension direction of the first portion, the length of the first gap corresponding to the first portion is W1; W1≥2 μm, and / or, in the extension direction of the third portion, the length of the second gap corresponding to the third portion is W2; W2≥2μm.

13. The array substrate according to claim 12, characterized in that: The distance between two adjacent second routing lines is S1; S1 ≥ 10 μm, and / or the distance between two adjacent first routing lines is S2, S2 ≥ 10 μm.

14. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 13.

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