Method, system and device for optimizing ReLee filtering algorithm based on CUDA (Compute Unified Device Architecture) platform

Abstract

The invention discloses an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform, and relates to the technical field of signal processing.The optimization method comprises the following steps that a first memory and a second memory are applied in a global memory of a GPU, image data to be filtered in a memory of a CPU is copied to the first memory, and the second memory is copied to the second memory; according to the to-be-filtered image data layout block stored in the first memory, after a CUDA kernel function is started, all threads in the block are allowed to execute the kernel function so as to obtain a filtering result, the filtering result is stored in the second memory, and the filtering result is copied to the memory of the CPU. Through the steps, the optimization method is favorable for improving the calculation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform. Background Art

[0002] The ReLee filter algorithm usually refers to a variant or improved scheme of the Lee filter used in SAR (synthetic aperture sonar) image processing. The ReLee filter is a statistical method widely used in SAR image denoising, which aims to reduce speckle noise while maintaining image edges and details. Although it performs well in denoising, it has some problems in computational performance. The ReLee filter algorithm requires statistical analysis of the neighborhood around each pixel, calculating the local variance and mean to determine the weighting coefficient. This process is repeated for each pixel, resulting in a large overall amount of calculation, especially when processing high-resolution SAR images, the required computing resources and time are significantly increased. In addition, in order to calculate the filtering result of each pixel, the algorithm usually needs to store the pixel values ​​in its neighborhood, which takes up a considerable amount of memory space. For large-scale images, memory requirements may become a limiting factor. Summary of the invention

[0003] One object of the present invention is to provide an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform, wherein the optimization method is calculated in a GPU, with shorter calculation time and higher efficiency, and the calculation process does not need to occupy too many CPU resources.

[0004] An object of the present invention is to provide a method, system and device for optimizing a ReLee filtering algorithm based on a CUDA platform, wherein the optimization method allows a large number of threads to calculate simultaneously with a high degree of parallelism.

[0005] One object of the present invention is to provide an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform, wherein the calculation process of the optimization method is performed in a shared memory, and the calculation process does not require multiple reading and writing of the global memory, so the optimization method makes the calculation more efficient.

[0006] In order to achieve at least one of the above purposes, the technical solution adopted by the present invention is to provide an optimization method of the ReLee filtering algorithm based on the CUDA platform, wherein the optimization method comprises the following steps: S1, apply for the first memory and the second memory in the global memory of the GPU; S2, copying the image data to be filtered in the memory of the CPU to the first memory; S3, arranging blocks according to the image data to be filtered stored in the first memory; S4, after the CUDA kernel function is started, allowing all threads in each of the blocks to execute the kernel function to obtain filtering results, wherein the filtering results are stored in the second memory; S5, copying the filtering result to the memory of the CPU.

[0007] As a further improvement of the technical solution of the present invention, step S4 includes the following steps: S4.1, find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; S4.2, divide the n×n matrix into 9 m×m matrices, where m is an odd number; S4.3, respectively calculate the average of the pixel values ​​of the 9 m×m matrices; S4.4, combine the 9 means into a 3×3 matrix; S4.5, the combined 3×3 matrix is ​​respectively combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; S4.6, Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; S4.7, substitute the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; S4.8, write the filtering result into the second memory to store the filtering result in the second memory.

[0008] As a further improvement of the technical solution of the present invention, before step S4.1, step S4 also includes a shared memory allocation step for allocating shared memory to each of the blocks.

[0009] As a further improvement of the technical solution of the present invention, in the shared memory allocation step, the shared memory is allocated to the block based on the size of the block.

[0010] As a further improvement of the technical solution of the present invention, the shared memory allocation step includes the following steps: first, determining the edge pixels of the block, and second, expanding outward by 3 pixels from the edge pixels.

[0011] According to another aspect of the present invention, the present invention further provides an optimization system for the ReLee filtering algorithm based on the CUDA platform, comprising: An application unit, used for applying for a first memory and a second memory in a global memory of a GPU; A copy unit, used for copying data between the memory of the CPU and the first memory and the second memory; a layout unit, configured to layout blocks according to the image data to be filtered stored in the first memory, wherein the image data to be filtered is copied from the memory of the CPU into the first memory by the copy unit; The execution unit is used to allow all threads in each of the blocks to execute the kernel function after the CUDA kernel function is started to obtain a filtering result, wherein the filtering result is stored in the second memory, and the copy unit is used to copy the filtering result from the second memory to the memory of the CPU.

[0012] As a further improvement of the technical solution of the present invention, the execution unit performs the following operations when executing the kernel function: Find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; Divide the n×n matrix into 9 m×m matrices, where m is an odd number; Calculate the average of the pixel values ​​of the 9 m×m matrices respectively; Combine the 9 means into a 3×3 matrix; The combined 3×3 matrix is ​​combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; Substituting the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; The filtering result is written into the second memory to store the filtering result in the second memory.

[0013] As a further improvement of the technical solution of the present invention, the execution unit performs the following operations when executing the kernel function: allocating shared memory for each of said blocks; Find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; Divide the n×n matrix into 9 m×m matrices, where m is an odd number; Calculate the average of the pixel values ​​of the 9 m×m matrices respectively; Combine the 9 means into a 3×3 matrix; The combined 3×3 matrix is ​​combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; Substituting the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; The filtering result is written into the second memory to store the filtering result in the second memory.

[0014] As a further improvement of the technical solution of the present invention, the execution unit allocates the shared memory to the block based on the size of the block.

[0015] According to another aspect of the present invention, the present invention further provides a computing device, comprising a processor and a memory coupled to the processor, wherein the memory is used to store program instructions, and the processor is used to execute the program instructions. When the program instructions are executed, the computing device executes an optimization method for a ReLee filtering algorithm based on a CUDA platform, wherein the optimization method comprises the following steps: S1, apply for the first memory and the second memory in the global memory of the GPU; S2, copying the image data to be filtered in the memory of the CPU to the first memory; S3, arranging blocks according to the image data to be filtered stored in the first memory; S4, after the CUDA kernel function is started, allowing all threads in each of the blocks to execute the kernel function to obtain filtering results, wherein the filtering results are stored in the second memory; S5, copying the filtering result to the memory of the CPU.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: First, the optimization method of the present invention copies the image data to be filtered in the memory of the CPU to the first memory of the GPU to perform calculations in the GPU. Compared with the method of calculating in the CPU, the optimization method of the present invention takes less time and is more efficient, and the calculation process does not need to occupy too much CPU resources. Second, the specific steps performed by the optimization method of the present invention when executing the kernel function enable a large number of threads to calculate simultaneously, with high parallelism; Third, the optimization method of the present invention includes the step of allocating shared memory, so that the calculation process is performed in the shared memory. In this way, there is no need to read and write the global memory multiple times during the calculation process, so the optimization method of the present invention has higher calculation efficiency; Fourthly, the optimization method of the present invention expands the edge of the block outward by 3 pixels when performing the shared memory allocation step. In this way, the optimization method can ensure that each pixel in the image data to be filtered participates in the calculation to ensure the optimization quality.

[0017] Other beneficial effects of the optimization method and the optimization system of the present invention will be further disclosed in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of an optimization method of a ReLee filtering algorithm based on a CUDA platform of the present invention.

[0019] Figure 2 It is a schematic diagram of the application environment of the optimization method of the present invention.

[0020] Figure 3 It is a schematic diagram of the relationship between the block and the shared memory of the present invention.

[0021] Figure 4 It is a schematic diagram of the matrix conversion process of the present invention.

[0022] Figure 5 It is a schematic diagram of the applicable conditions of each template of the present invention and the corresponding template.

[0023] Figure 6 It is a block diagram of an optimization system of a ReLee filtering algorithm based on a CUDA platform of the present invention.

[0024] Figure 7 It is a block diagram of a computing device of the present invention.

[0025] In the figure: 101, first memory; 102, second memory; 103, block; 104, grid; 105, shared memory; 10. Optimization system; 11. Application unit; 12. Copy unit; 13. Layout unit; 14. Execution unit; 20. Computing device; 21. Processor; 22. Memory; 23. Input device; 24. Output device. DETAILED DESCRIPTION

[0026] Before describing in detail any embodiment of the present invention, it should be understood that the present invention is not limited in its application to the construction and arrangement details of the components described below or illustrated in the following figures. The present invention can have other embodiments and can be practiced or carried out in various ways. In addition, it should be understood that the words and terms used here are for descriptive purposes and should not be considered restrictive. The use of "including" or "having" and its variations herein is intended to cover the items and their equivalents and additional items displayed below. Unless otherwise specified or limited, the terms "install", "connect", "support" and "couple" and their variations are widely used and cover direct installation and indirect installation, connection, support and connection. In addition, "connect" and "couple" are not limited to physical or mechanical connections or connections.

[0027] Furthermore, on the first aspect, in the disclosure of the present invention, the orientations or positional relationships indicated by terms such as “longitudinal”, “transverse”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside” and “outside” are based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore the above terms cannot be understood as limitations on the present invention; on the second aspect, the term “one” should be understood as “at least one” or “one or more”, that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term “one” cannot be understood as a limitation on the quantity.

[0028] Application Overview The ReLee filter algorithm is needed for SAR image denoising. Since the existing ReLee filter algorithm needs to perform statistical analysis on the neighborhood around each pixel, calculate the local variance and mean to determine the weighting coefficient, the calculation process needs to be repeated for each pixel, resulting in a large amount of overall calculation. Especially when processing high-resolution SAR images, the computing resources occupied by the calculation process and the computing time spent are significantly increased.

[0029] Based on this, the basic concept of the optimization method of the ReLee filtering algorithm based on the CUDA platform of the present invention (hereinafter referred to as the "optimization method") is to first copy the image data to be filtered in the memory of the CPU to the memory of the GPU, and then design a CUDA kernel function in the GPU to perform calculations, and then copy the obtained filtering results to the CPU.

[0030] Exemplary Methods Reference Figure 1 and Figure 2 The optimization method of the present invention comprises the following steps: S1, applying for a first memory 101 and a second memory 102 in the global memory of the GPU; S2, copying the image data to be filtered in the memory of the CPU to the first memory 101; S3, laying out a block (Block) 103 according to the image data to be filtered stored in the first memory 101; S4, after the CUDA kernel function is started, allowing all threads in the block 103 to execute the kernel function to obtain the filtering result, wherein the filtering result is stored in the second memory 102; S5, copying the filtering result to the memory of the CPU.

[0031] Compared with the prior art, the optimization method of the present invention executes steps S1 to S5. On the one hand, the calculation time of the optimization method of the present invention is shorter and the efficiency is higher. On the other hand, the calculation process of the optimization method of the present invention is performed in the GPU, which is beneficial to reducing the utilization rate of the CPU. Therefore, the optimization method of the present invention allows the CPU to process other tasks while performing calculations. On the other hand, the memory overhead in the calculation process is stored in the GPU, so the calculation process does not need to occupy too many CPU resources.

[0032] Specifically, Figure 1 and Figure 2 As shown, in step S1 and step S2, the optimization method applies for two memories in the GPU, one memory is the first memory 101, which is used to store the image data to be filtered copied from the memory of the CPU, and the other memory is the second memory 102, which is used to store the filtering result.

[0033] After the optimization method of the present invention applies for the first memory 101 and the second memory 102 in the GPU, the optimization method further copies the image data to be filtered in the memory of the CPU to the first memory 101 of the GPU for subsequent calculation in the GPU to realize filtering, and the filtering result is stored in the second memory 102 of the GPU.

[0034] In other words, in the optimization method of the present invention, the purpose of applying for the first memory 101 and the second memory 102 in the GPU is to perform calculations in the GPU to achieve filtering and ensure that the memory overhead in the calculation process is stored in the GPU. Therefore, it is not only beneficial to reduce the utilization rate of the CPU, but also the calculation process does not need to occupy too many CPU resources.

[0035] Continue to refer to the attached Figure 1 and Figure 2 In the step S3, the optimization method arranges the blocks 103 according to the image data to be filtered stored in the first memory 101 of the GPU. It can be understood that the blocks 103 form a grid 104.

[0036] Specifically, the total number of threads in the GPU required for filtering the image data to be filtered is determined by the product of the size of the block 103 and the size of the grid 104. Since the upper limit of the number of threads in each block 103 is usually 1024, it is necessary to first determine the size of the block 103, and then calculate the size of the grid 104 according to the size of the block 103. Under the SIMT (single instruction multiple thread) architecture of the GPU, warp (thread bundle) is the basic unit of scheduling, which usually contains 32 threads. Therefore, in order to ensure that work can be evenly distributed on each SM (streaming multiprocessor) of the GPU and avoid resource limitations or excessive competition, it is necessary to ensure that the size of the block 103 is an integer multiple of 32 and cannot exceed the upper limit (that is, cannot exceed 1024), and at the same time, the number of threads in the block 103 should be as large as possible to improve the hardware occupancy rate. In addition, since the image processed by the optimization method of the present invention is a two-dimensional image, the block 103 is a two-dimensional structure, and the size of the block 103 is set to be 32 in both length and width.

[0037] Continue to refer to the attached Figure 1 and Figure 2 In step S4, after the CUDA kernel function is started, the optimization method allows all threads in each block 103 to execute the kernel function to obtain the filtering result.

[0038] Specifically, in order to increase the speed of reading data from the memory of the GPU, in a specific example of the optimization method of the present invention, the optimization method can allocate a shared memory 105 for each block 103. The shared memory technology of the CUDA platform enables the GPU to access the shared memory 105 within 4 clock cycles, which is much lower than the 400-600 clock cycles of the global memory of the GPU. Since each thread is responsible for calculating a pixel, and the value of each pixel depends on the surrounding pixels within a range of n×n, where n is an odd number greater than or equal to 3, in a specific example of the present invention, Figure 3 As shown, the optimization method of the present invention applies for a uint8 type shared memory 105 for each block 103, and the size of the shared memory 105 is 3 pixels extended outward from the edge pixels of the block 103. For example, if the size of the block 103 is 32×32, the size of the shared memory 105 is 38×38, and then the values ​​of the pixels in the range after the edge pixels of the block 103 are extended outward by 3 pixels are read into the shared memory 105. In this case, when each block 103 runs 1024 threads, the shared memory 105 used by the block 103 is only 1444 bytes, which will not exceed the maximum limit of the shared memory 105.

[0039] More specifically, the following steps need to be performed in the CUDA kernel function.

[0040] First, the shared memory 105 is allocated to the block 103 , and the thread reads the corresponding pixel value from the first memory 101 to the shared memory 105 .

[0041] Secondly, first find the n×n matrix of pixels corresponding to the thread, where n is an odd number greater than or equal to 3, and then divide the n×n matrix into 9 m×m matrices, where m is an odd number, and then calculate the mean of the pixel values ​​of the 9 m×m matrices respectively, and combine the 9 mean values ​​into a 3×3 matrix. For example, in a specific example of the optimization method of the present invention, Figure 4 As shown, the 7×7 matrix of pixels corresponding to the thread can be found first, and then the 7×7 matrix is ​​divided into 9 3×3 matrices, and then the average of the pixel values ​​of the 9 3×3 matrices is calculated respectively, and the 9 averages are combined into 1 3×3 matrix. Optionally, in another specific example of the optimization method of the present invention, the 5×5 matrix of pixels corresponding to the thread can be found first, and then the 5×5 matrix is ​​divided into 9 3×3 matrices, and then the average of the pixel values ​​of the 9 3×3 matrices is calculated respectively, and the 9 averages are combined into 1 3×3 matrix.

[0042] Third, combine the combined 3×3 matrix with the 4 matrices , , , The dot product gives 4 values , , and , where the matrix , , , They are: ; ; ; .

[0043] Since the matrix , , , There are many 0 values ​​in the matrix, and the matrix size is not large. In order to save the storage matrix , , , The extra memory overhead and redundant calculations and avoiding for loops, 4 values , , and can be written directly as: ; ; ; ; in , , , , , , , and They correspond one-to-one to each pixel in the combined 3×3 matrix.

[0044] Fourth, Figure 5 The white areas in the 8 templates in the , respectively, correspond to a summation function, and then select the corresponding template according to whether the n×n matrix satisfies the conditions, and then call the summation function corresponding to the template to sum the white areas of the n×n matrix corresponding to the template, and divide the sum by Get the mean of the white area of ​​the template in the n×n matrix, where Satisfy the formula In a specific example of the optimization method of the present invention, if the n×n matrix of pixels corresponding to the thread is a 7×7 matrix, a corresponding template is selected according to whether the 7×7 matrix satisfies a condition, and then a summation function corresponding to the template is called to sum the portion of the white area of ​​the 7×7 matrix corresponding to the template, and the sum is divided by 28 to obtain the mean value of the portion of the white area of ​​the 7×7 matrix corresponding to the template.

[0045] For example, Figure 5 As shown, the optimization method of the present invention presets 8 templates, which are the first template, the second template, the third template, the fourth template, the fifth template, the sixth template, the seventh template and the eighth template. The white areas of the first template, the second template, the third template, the fourth template, the fifth template, the sixth template, the seventh template and the eighth template correspond to a summation function respectively. The condition for applying the first template is and , the conditions for applying the second template are and , the conditions for applying the third template are and , the conditions for applying the fourth template are and , the conditions for applying the fifth template are and , the conditions for applying the sixth template are and , the conditions for applying the seventh template are and , the conditions for applying the eighth template are and If a 7×7 matrix satisfies the condition and , then call the sum function corresponding to the first template to sum the pixel values ​​of the four left columns in the 7×7 matrix, and divide the sum by 28 to get the mean value of the white area of ​​the 7×7 matrix corresponding to the template. If the 7×7 matrix meets the condition and , then call the summation function corresponding to the sixth template to sum the pixel values ​​of the lower four rows in the 7×7 matrix, and divide the sum by 28 to obtain the mean value of the white area of ​​the 7×7 matrix corresponding to the template.

[0046] Fifth, find the variance of the surrounding n×n matrix.

[0047] Sixth, substitute the variance and mean into a set of formulas: , obtain the filtering result, and store the filtering result in the second memory 102 of the GPU.

[0048] That is, in a specific example of the optimization method of the present invention, the step S4 includes the following steps: S4.0, for allocating the shared memory 105 to each of the blocks 103; S4.1, for finding the surrounding n×n matrix of the pixel corresponding to each thread in the block 103, where n is an odd number greater than or equal to 3; S4.2, for dividing the n×n matrix into 9 m×m matrices, where m is an odd number; S4.3, for averaging the pixel values ​​of the 9 m×m matrices respectively; S4.4, for combining the 9 averages into a 3×3 matrix; S4.5, for combining the combined 3×3 matrix with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; S4.6, Find the value , , and The maximum value of , judge the relationship in the combined 3×3 matrix, and according to the judgment result, select the corresponding template and calculate the variance and mean of the white area of ​​the corresponding template in the n×n matrix; S4.7, substitute the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; S4.8, writing the filtering result into the second memory 102 to store the filtering result in the second memory 102. In this way, the calculation process in the step S4 of the optimization method of the present invention does not need to read and write in the global memory of the GPU, but only needs to read and write in the shared memory 105, which makes the access speed faster and can ensure that a large number of threads are calculated at the same time with high parallelism, which is conducive to improving the calculation efficiency of the optimization method.

[0049] It is understandable that, in another specific example of the optimization method of the present invention, the optimization method may not allocate the shared memory 105 for the block 103, that is, the optimization method does not include the shared memory allocation step, and only includes the steps S4.1 to S4.9. In this embodiment, the calculation process in step S4 of the optimization method needs to read and write in the global memory of the GPU, and the way of reading and writing in the global memory of the GPU does not affect the optimization method's ability to perform calculations on a large number of threads at the same time. In other words, even if the shared memory 105 is not allocated to the block 103, executing steps S4.1 to S4.9 in step S4 still has the advantages of simultaneous calculations of a large number of threads and high parallelism.

[0050] In the shared memory allocation step, the optimization method allocates the shared memory 105 to the block 103 based on the size of the block 103, so that each of the blocks 103 can read and write data in the shared memory 105 during calculation, without the need to read and write data in the global memory of the GPU. Specifically, the step of allocating the shared memory 105 to the block 103 based on the size of the block 103 includes: first, determining the edge pixels of the block 103, and secondly, allocating the shared memory 105 by expanding 3 pixels outward from the edge pixels to ensure that the edge pixels of the block 103 can participate in the calculation, thereby ensuring the optimization effect of the optimization method of the present invention.

[0051] Exemplary Systems Figure 6The present invention shows an optimization system 10 of the ReLee filtering algorithm based on the CUDA platform according to another preferred embodiment of the present invention, wherein the optimization system 10 includes an application unit 11, a copy unit 12, a layout unit 13 and an execution unit 14. The application unit 11 is used to apply for the first memory 101 and the second memory 102 in the global memory of the GPU, the copy unit 12 is used to copy data between the memory of the CPU and the first memory 101 and the second memory 102, the layout unit 13 is used to layout blocks according to the image data to be filtered stored in the first memory 101, wherein the image data to be filtered is copied from the memory of the CPU to the first memory 101 by the copy unit 12, and the execution unit 14 is used to allow all threads in each of the blocks 103 to execute the kernel function after the CUDA kernel function is started to obtain the filtering result, wherein the filtering result is stored in the second memory 102, and the copy unit 12 is used to copy the filtering result from the second memory 102 to the memory of the CPU. In this way, on the one hand, the calculation time of the optimization system 10 of the present invention is shorter and more efficient. On the other hand, the calculation process of the optimization system 10 of the present invention is performed in the GPU, which is beneficial to reducing the utilization rate of the CPU. Therefore, the optimization system 10 of the present invention allows the CPU to process other tasks while performing calculations. On the other hand, the memory overhead in the calculation process is stored in the GPU, so the calculation process does not need to occupy too many CPU resources.

[0052] In a specific example of the optimization system 10 of the present invention, the execution unit 14 performs the following operations when executing the kernel function: find the surrounding n×n matrix of the pixel corresponding to each thread in the block 103, where n is an odd number greater than or equal to 3; divide the n×n matrix into 9 m×m matrices, where m is an odd number; calculate the average of the pixel values ​​of the 9 m×m matrices respectively; combine the 9 averages into a 3×3 matrix; and compare the combined 3×3 matrix with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Find value , , and The maximum value of , judge the relationship in the combined 3×3 matrix, and according to the judgment result, select the corresponding template and calculate the variance and mean of the white area of ​​the corresponding template in the n×n matrix; substitute the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; and the filtering result is written into the second memory 102 to store the filtering result in the second memory 102. In this way, the optimization system 10 of the present invention allows a large number of threads to calculate simultaneously, and has a high degree of parallelism, so as to improve the calculation efficiency of the optimization system 10.

[0053] In another specific example of the optimization system 10 of the present invention, the execution unit 14 performs the following operations when executing the kernel function: allocate the shared memory 105 to each of the blocks 103; find the surrounding n×n matrix of the pixel corresponding to each thread in the block 103, where n is an odd number greater than or equal to 3; divide the n×n matrix into 9 m×m matrices, where m is an odd number; calculate the average of the pixel values ​​of the 9 m×m matrices respectively; combine the 9 averages into a 3×3 matrix; and compare the combined 3×3 matrix with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Find value , , and The maximum value of , judge the relationship in the combined 3×3 matrix, and according to the judgment result, select the corresponding template and calculate the variance and mean of the white area of ​​the corresponding template in the n×n matrix; substitute the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; and the filtering result is written into the second memory 102 to store the filtering result in the second memory 102. In this way, the optimization system 10 of the present invention does not need to read and write in the global memory of the GPU, but only needs to read and write in the shared memory 105, which makes the access speed faster and can ensure that a large number of threads are calculated at the same time with high parallelism, which is conducive to improving the calculation efficiency of the optimization method.

[0054] Exemplary Devices like Figure 7 As shown, a computing device 20 according to a preferred embodiment of the present invention includes one or more processors 21 and one or more memories 22 connected to the processors 21 .

[0055] The processor 21 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the computing device 20 to perform desired functions.

[0056] The memory 22 may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 21 may execute the program instructions to implement the optimization method of the present invention described above and / or other desired functions.

[0057] Specifically, when the processor 21 executes the program instructions stored in the memory 22, the computing device 20 executes the optimization method, wherein the optimization method includes the following steps: applying for a first memory 101 and a second memory 102 in the global memory of the GPU; copying the image data to be filtered in the memory of the CPU to the first memory 101; laying out the block 103 according to the image data to be filtered stored in the first memory 101; after the CUDA kernel function is started, allowing all threads in the block 103 to execute the kernel function to obtain the filtering result, wherein the filtering result is stored in the second memory 102; copying the filtering result to the memory of the CPU. In this way, on the one hand, the computing time of the computing device 20 of the present invention is shorter and more efficient, on the other hand, the computing process of the computing device 20 of the present invention is performed in the GPU, which is conducive to reducing the utilization rate of the CPU, so the computing device 20 of the present invention allows the CPU to process other tasks while performing the calculation, on the other hand, the memory overhead in the calculation process is stored in the GPU, so the calculation process does not need to occupy too much of the CPU resources.

[0058] In a specific example of the computing device 20 of the present invention, the computing device 20 may also include an input device 23 and an output device 24, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown). The input device 23 may include, for example, a keyboard, a mouse, etc. The output device 24 may output various information to the outside. The output device 24 may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0059] It should be understood by those skilled in the art that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The purpose of the present invention has been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments, and the embodiments of the present invention may be modified or altered in any way without departing from the principles.

Claims

1. The optimization method of ReLee filtering algorithm based on CUDA platform is characterized in that: The optimization method comprises the following steps: S1, apply for the first memory and the second memory in the global memory of the GPU; S2, copying the image data to be filtered in the memory of the CPU to the first memory; S3, arranging blocks according to the image data to be filtered stored in the first memory; S4, after the CUDA kernel function is started, allowing all threads in each of the blocks to execute the kernel function to obtain filtering results, wherein the filtering results are stored in the second memory; S5, copying the filtering result to the memory of the CPU.

2. The optimization method according to claim 1, characterized in that: The step S4 comprises the following steps: S4.1, find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; S4.2, divide the n×n matrix into 9 m×m matrices, where m is an odd number; S4.3, respectively calculate the average of the pixel values ​​of the 9 m×m matrices; S4.4, combine the 9 means into a 3×3 matrix; S4.5, the combined 3×3 matrix is ​​respectively combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; S4.6, Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; S4.7, substitute the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; S4.8, write the filtering result into the second memory to store the filtering result in the second memory.

3. The optimization method according to claim 2, characterized in that: Before step S4.1, step S4 also includes a shared memory allocation step for allocating a shared memory to each of the blocks.

4. The optimization method according to claim 3, characterized in that: In the shared memory allocation step, the shared memory is allocated to the block based on the size of the block.

5. The optimization method according to claim 4, characterized in that: The shared memory allocation step includes the following steps: first, determining edge pixels of the block, and second, expanding outward by 3 pixels from the edge pixels.

6. The optimization system of ReLee filtering algorithm based on CUDA platform is characterized by: include: An application unit, used for applying for a first memory and a second memory in a global memory of a GPU; A copy unit, used for copying data between the memory of the CPU and the first memory and the second memory; a layout unit, configured to layout blocks according to the image data to be filtered stored in the first memory, wherein the image data to be filtered is copied from the memory of the CPU into the first memory by the copy unit; The execution unit is used to allow all threads in each of the blocks to execute the kernel function after the CUDA kernel function is started to obtain a filtering result, wherein the filtering result is stored in the second memory, and the copy unit is used to copy the filtering result from the second memory to the memory of the CPU.

7. The optimization system according to claim 6, characterized in that: The execution unit performs the following operations when executing the kernel function: Find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; Divide the n×n matrix into 9 m×m matrices, where m is an odd number; Calculate the average of the pixel values ​​of the 9 m×m matrices respectively; Combine the 9 means into a 3×3 matrix; The combined 3×3 matrix is ​​combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; Substituting the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; The filtering result is written into the second memory to store the filtering result in the second memory.

8. The optimization system according to claim 6, characterized in that: The execution unit performs the following operations when executing the kernel function: allocating shared memory for each of said blocks; Find the surrounding n×n matrix of the pixel corresponding to each thread in the block, where n is an odd number greater than or equal to 3; Divide the n×n matrix into 9 m×m matrices, where m is an odd number; Calculate the average of the pixel values ​​of the 9 m×m matrices respectively; Combine the 9 means into a 3×3 matrix; The combined 3×3 matrix is ​​combined with the matrix ,matrix ,matrix and matrix Dot product, get the value , , and ; Finding Values , , and The maximum value of the combined 3×3 matrix is ​​determined, and according to the determination result, the corresponding template is selected and the variance and mean of the white area of ​​the corresponding template in the n×n matrix are calculated; Substituting the variance and mean into a set of formulas: , and obtain the filtering result, where the parameters Represents the gray value of the pixel before filtering, parameter The mean value of the white area of ​​the template, parameter Represents the variance of the white area of ​​the template, parameter is the number of image pixels, and the parameter is the gray value after filtering; The filtering result is written into the second memory to store the filtering result in the second memory.

9. The optimization system according to claim 8, characterized in that: The execution unit allocates the shared memory for the block based on the size of the block.

10. A computing device, characterized in that The computing device comprises a processor and a memory coupled to the processor, wherein the memory is used to store program instructions, and the processor is used to execute the program instructions. When the program instructions are executed, the computing device executes the optimization method according to any one of claims 1 to 5.

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