SOI-LIGBT device introducing deep groove and self-biased PMOS

Abstract

The invention relates to an SOI-LIGBT (Silicon On Insulator-Lateral Insulated Gate Bipolar Translator) device introducing a deep groove and a self-biased PMOS (P-channel Metal Oxide Semiconductor), and belongs to The device comprises a cathode P + region, a cathode P-well region, a cathode N + region, a drift region, a P-buffer region, an anode N-buffer region, an anode P + region, a main gate oxide layer, a polycrystalline silicon main gate, a deep trench oxide layer, a deep trench oxide layer, a polycrystalline silicon auxiliary gate, a silicon dioxide buried oxide layer and a substrate. According to the device, a self-biased PMOS (P-channel Metal Oxide Semiconductor) is integrated at a cathode, an extraction channel of excess carriers is provided during turn-off, the working frequency of the device in the application process is improved, saturation current is reduced during forward conduction of the device, the short-circuit safe working time of the device is prolonged, and the reliability and the safety of the device are improved; and the PMOS integrated with the cathode does not need to be controlled by an additional circuit, so that the feasibility of the device in the actual application process is improved, and the design difficulty of the driving circuit is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a SOI-LIGBT device with a deep trench and a self-biased PMOS. Background Art

[0002] Insulated gate bipolar transistor (IGBT) is a power semiconductor device that plays a key role in modern power electronics technology. From the development background, as power electronics technology develops towards high voltage, high current and high frequency, traditional power transistors (such as bipolar junction transistor BJT) and power field effect transistors (MOSFET) have gradually exposed their limitations in some application scenarios. For example, BJT has problems such as large driving current and insufficient switching speed, while MOSFET has a large on-resistance when used in high voltage and high current applications. Under such technological development needs, IGBT came into being. IGBT combines the advantages of MOSFET's high input impedance, voltage-controlled drive and BJT's low on-state voltage drop. It appeared in the 1980s and has developed rapidly since then.

[0003] In the industrial field, with the continuous improvement of the degree of automated production, applications such as motor speed regulation and inverter power supply require more efficient power control components, and IGBT can meet these needs well. In the energy field, whether it is the power conversion link in traditional thermal power generation and hydropower generation, or the inverter and other equipment in emerging renewable energy power generation systems such as solar energy and wind energy, IGBT has played an important role. Moreover, in the field of transportation, such as the motor drive and charging system of electric vehicles, the high performance of IGBT is crucial to improving energy utilization efficiency and vehicle performance. In short, the emergence of IGBT meets the urgent needs of the power electronics industry for high-performance power devices and has promoted technological innovation and development in many fields.

[0004] Due to the bipolar conductive characteristics of IGBT, although IGBT has good conduction advantages, it also brings a series of reliability problems such as low switching frequency, high saturation current and easy latching. Solving these problems can broaden the application scenarios of IGBT, which is of great significance to IGBT. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a SOI-LIGBT device that introduces deep trenches and self-biased PMOS to improve reliability. In the structure of a traditional IGBT device, a deep trench oxide layer and a self-biased PMOS are introduced to provide a hole carrier extraction channel when the device is turned off, so that when the device is turned off, the excess hole carriers in the drift region can be quickly extracted to achieve rapid shutdown of the device. This structure improves the shutdown speed of the IGBT device while also reducing the saturation current of the IGBT, thereby improving the short-circuit safe operating area and anti-latch capability of the device, and improving the reliability of the device.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A SOI-LIGBT device with deep trench and self-biased PMOS, comprising:

[0008] substrate;

[0009] a buried silicon dioxide layer located on the surface of the substrate;

[0010] A drift region located on the surface of the silicon dioxide buried layer;

[0011] A main gate oxide layer located on the surface of the silicon dioxide buried layer and adjacent to the drift region;

[0012] A polysilicon main gate located in the main gate oxide layer and wrapped by the main gate oxide layer;

[0013] A P-buried region located in the middle region of the drift region;

[0014] a deep trench oxide layer located in the P-buried region and extending upwardly out of the P-buried region;

[0015] A polysilicon auxiliary gate located in the deep trench oxide layer and wrapped by the deep trench oxide layer;

[0016] A cathode P-well region located on the surface of the drift region and distributed on one side of the deep trench oxide layer;

[0017] A cathode P+ region and a cathode N+ region located on the surface of the cathode P-well region and between the deep trench oxide layer and the silicon dioxide buried layer;

[0018] An anode N-buffer region located on the surface of the drift region and distributed on the other side of the deep trench oxide layer;

[0019] an anode P+ region located in the anode N-buffer region and surrounded by the anode N-buffer region;

[0020] an emitter electrode located on the surface of the cathode N+ region, the cathode P+ region and the polysilicon auxiliary gate; and

[0021] A collector electrode is located on the surface of the anode P+ region.

[0022] The anode P+ region, the anode N-buffer region, the drift region and the cathode P-well region constitute the first anode region PNP transistor of the device. When the device is forward-conducted, the first anode region PNP transistor is used to provide holes.

[0023] In the first anode region PNP transistor, the emitter is the anode P+ region, the base is the anode N-buffer region and the drift region, and the collector is the cathode P-well region.

[0024] The anode P+ region, anode N-buffer region, drift region and low-doped P-buried region constitute the second anode region PNP transistor of the device. When the device is forward-conducted, the second anode region PNP transistor is used to provide holes.

[0025] In the second anode region PNP transistor, the emitter is the anode P+ region, the base is the anode N-buffer region and the drift region, and the collector is the low-doped P-buried region.

[0026] The P-buried region, drift region, cathode P-well region, cathode P+ region, deep trench oxide layer and polysilicon auxiliary gate constitute the self-biased PMOS of the cathode of the device. The deep trench oxide layer is the gate oxide layer of the self-biased PMOS, the P-buried region is the source of the self-biased PMOS, the drift region is the substrate of the self-biased PMOS, the cathode P-well region and the cathode P+ region are the drain of the self-biased PMOS, and the polysilicon auxiliary gate is the gate of the self-biased PMOS.

[0027] Furthermore, the self-biased PMOS is used to control the on and off of the device and provide an additional hole channel to reduce energy loss when the device is turned off and reduce the saturation current to improve the short-circuit safe operating area and anti-latch capability of the device.

[0028] The beneficial effect of the present invention is that: on the basis of the traditional LIGBT device, the present invention introduces a deep trench oxide layer, so that the carriers no longer simply migrate from left to right or from right to left, thereby increasing the carrier path without increasing the chip area, saving more silicon wafer area, and allowing the structure to have a higher power density. The breakdown voltage is greatly improved compared with the traditional structure, and the withstand voltage performance is improved by 51.1% compared with the traditional LIGBT device.

[0029] At the same time, the present invention also introduces a self-biased PMOS. When the device is turned off or the forward voltage is large, the potential of the source of the self-biased PMOS will become higher, and the gate of the self-biased PMOS is short-circuited with the emitter of the device and grounded. When the difference between the gate potential and the source potential of the self-biased PMOS is less than the threshold voltage of the PMOS, the PMOS is turned on to extract holes, providing an additional channel for hole carriers, which can not only reduce the energy loss of the device when it is turned off, but also reduce the saturation current to improve the short-circuit safe working area and anti-latch capability of the device. Among them, the short-circuit safe working time of the present invention is about 3.2 times that of traditional devices.

[0030] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0032] Figure 1 A schematic diagram of the structure of a PDP-LIGBT device provided in Example 1 of the present invention;

[0033] Figure 2 for Figure 1 Equivalent circuit diagram of the device shown;

[0034] Figure 3 Optimization diagram of breakdown voltage of Embodiment 1 of the present invention, CONV-LIGBT (conventional SOI-LIGBT) and DOT-LIGBT (SOI-LIGBT with only deep trench oxide layer introduced);

[0035] Figure 4 It is a comparison diagram of the forward blocking curves of Example 1 of the present invention, CONV-LIGBT and DOT-LIGBT;

[0036] Figure 5 This is a comparison diagram of the forward conduction performance of Embodiment 1 of the present invention, CONV-LIGBT and DOT-LIGBT;

[0037] Figure 6 This is a comparison chart of the short-circuit safety working performance of Embodiment 1 of the present invention, CONV-LIGBT and DOT-LIGBT;

[0038] Figure 7 It is a comparison diagram of the turn-off curves of Embodiment 1 of the present invention, CONV-LIGBT and DOT-LIGBT;

[0039] Figure numerals: cathode P+ region 1, cathode N+ region 2, cathode P-well region 3, polysilicon main gate 4, main gate oxide layer 5, drift region 6, silicon dioxide buried oxide layer 7, P-type substrate 8, low-doped P-buried region 9, deep trench oxide layer 10, anode buffer layer 11, anode P+ region 12, polysilicon auxiliary gate 13. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0042] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0043] Embodiment 1:

[0044] like Figure 1As shown, this embodiment improves the traditional SOI-LIGBT device to obtain a SOI-LIGBT device with deep trench and self-biased PMOS, which includes a cathode P+ region 1, a cathode N+ region 2, a cathode P-well region 3, a polysilicon main gate 4, a main gate oxide layer 5, a drift region 6, a silicon dioxide buried oxide layer 7, a P-type substrate 8, a low-doped P-buried region 9, a deep trench oxide layer 10, an anode buffer layer 11, an anode P+ region 12, and a polysilicon auxiliary gate 13.

[0045] Among them, the cathode P+ region 1, the cathode N+ region 2, the cathode P-well region 3, the drift region 6, the main gate oxide layer 5, and the polysilicon main gate 4 constitute the common MOS region of the device. The cathode P+ region 1 is adjacent to the cathode N+ region 2, and they are located above the cathode P-well region 3; the drift region 6 is below the cathode P-well region 3; the main gate oxide layer 5 is adjacent to the cathode P-well region 3, the drift region 6, and the cathode N+ region 2; the main polysilicon gate 4 is completely wrapped by the main gate oxide layer 5 below, on the left and on the right.

[0046] The anode P+ region 12, the anode N-buffer region 11, the drift region 6, and the cathode P-well region 3 constitute the first anode region PNP transistor of the device. Among them, the anode P+ region 12 is completely wrapped by the anode N-buffer region 11, and the lower side of the anode N-buffer region 11 is wrapped by the drift region 6; the lower side of the cathode P-well region 3 is wrapped by the drift region 6. When forward conducting, the first anode region PNP transistor mainly plays the role of providing holes.

[0047] Among them, the anode P+ region 12 serves as the emitter of the first anode region PNP transistor, the anode N-buffer region 11 and the drift region 6 serve as the base of the first anode region PNP transistor, and the cathode P-well3 region serves as the collector of the first anode region PNP transistor.

[0048] The anode P+ region 12, the anode N-buffer region 11, the drift region 6, and the low-doped P-buried region 9 constitute the second anode region PNP transistor of the device. Among them, the low-doped P-buried region 9 is located in the middle of the drift region 6. When forward conducting, the second anode region PNP transistor mainly plays the role of providing holes.

[0049] The anode P+ region 12 serves as the emitter of the second anode region PNP transistor, the anode N-buffer region 11 and the drift region 6 serve as the base of the second anode region PNP transistor, and the P-buried region serves as the collector of the second anode region PNP transistor.

[0050] The low-doped P-buried region 9, the drift region 6, the cathode P-well region 3, the cathode P+ region 1, the deep trench oxide layer 10, and the polysilicon auxiliary gate 13 constitute the cathode self-biased PMOS of the device. The deep trench oxide layer 10 serves as the gate oxide layer of the PMOS, the low-doped P-buried region 9 serves as the source of the PMOS, the drift region 6 serves as the substrate of the PMOS, and the cathode P-well region 3 and the cathode P+ region 1 serve as the drain of the PMOS. Among them, the polysilicon auxiliary gate 13 serves as the gate of the self-biased PMOS, and the polysilicon auxiliary gate 13 is short-circuited with the emitter of the IGBT part.

[0051] When the device is working in forward conduction, the working state of the device of the present invention is consistent with that of an ordinary IGBT, wherein the gate voltage of the cathode MOS gradually increases, and electrons begin to be injected into the drift region. As the anode voltage increases, the self-biased PMOS integrated in the device gradually turns on, providing an additional hole path for the IGBT in forward conduction or short-circuit operation, reducing the saturation current of the device, improving the reliability of the device, extracting excess hole carriers in the drift region when the device is turned off, and improving the high-frequency characteristics of the device.

[0052] Example 2

[0053] This embodiment uses SENTAURUS simulation software to perform performance simulation analysis on the SOI-LIGBT device described in Example 1, analyze its mechanism, and perform electrical simulation. During the simulation process, the simulation parameters of the device in Example 1 are consistent with those of the traditional device and DOT-LIGBT, where the carrier lifetime is 10 μs and the ambient temperature is 300K.

[0054] like Figure 2 The figure shows an equivalent circuit diagram of the device of Example 1, wherein the IGBT is equivalent to a PNP transistor controlled by an NMOS; on this basis, Example 1 integrates a self-biased P-type MOS tube and an additional PNP triode, and does not require additional electrical signal control, so no additional control circuit is required in actual application.

[0055] like Figure 3 The figure shows the trend comparison of the breakdown voltage of the embodiment 1 device when the total length is 16 μm as the drift region doping concentration changes. It can be seen that under the same chip size, the embodiment 1 device greatly improves the device's voltage resistance and drift region doping, thereby improving the device's reliability and application range.

[0056] like Figure 4 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3Comparing the breakdown voltage curve below with that of DOT-LIGBT and traditional SOI-LIGBT, it can be seen that the breakdown voltage of this device is increased by 51.1% compared with the traditional SOI-LIGBT device.

[0057] like Figure 5 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 The forward conduction performance of Example 1 is compared with that of DOT-LIGBT and traditional SOI-LIGBT. It can be clearly seen from the forward conduction curve that the saturation current of Example 1 has a greater advantage over traditional SOI-LIGBT and DOT-LIGBT, and it can be seen that the current at this time has two paths, one is the traditional IGBT path, and the other is the self-bias PMOS path. The self-bias PMOS integrated in Example 1 plays a good shunting role.

[0058] like Figure 6 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 By comparing the short-circuit safety working performance under the conditions of DOT-LIGBT and traditional SOI-LIGBT, it can be seen that the self-biased PMOS of the device in Example 1 has an obvious shunting effect. The short-circuit safety working time of the device is about 3.2 times that of the traditional device, which greatly improves the reliability of the device.

[0059] like Figure 7 The figure shows the total length of the device in Example 1, which is 18 μm and the doping concentration of the drift region is 6.0×10 15 cm -3 Compared with the turn-off curves of DOT-LIGBT and traditional SOI-LIGBT, the turn-off time of the device in Example 1 is significantly reduced compared with DOT-LIGBT due to the carrier extraction effect of the self-biased PMOS, but the turn-off time is longer than that of the traditional SOI-LIGBT. The reason is that the carrier path of the traditional device is shorter and the amount of excess carriers is smaller. However, the reliability of traditional IGBT devices is poor and the breakdown voltage is low, which will cause reliability problems.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A SOI-LIGBT device with deep trench and self-biased PMOS, characterized in that: The device includes: substrate; a buried silicon dioxide layer located on the surface of the substrate; A drift region located on the surface of the silicon dioxide buried layer; A main gate oxide layer located on the surface of the silicon dioxide buried layer and adjacent to the drift region; A polysilicon main gate located in the main gate oxide layer and wrapped by the main gate oxide layer; A P-buried region located in the middle region of the drift region; a deep trench oxide layer located in the P-buried region and extending upwardly out of the P-buried region; A polysilicon auxiliary gate located in the deep trench oxide layer and wrapped by the deep trench oxide layer; A cathode P-well region located on the surface of the drift region and distributed on one side of the deep trench oxide layer; A cathode P+ region and a cathode N+ region located on the surface of the cathode P-well region and between the deep trench oxide layer and the silicon dioxide buried layer; An anode N-buffer region located on the surface of the drift region and distributed on the other side of the deep trench oxide layer; an anode P+ region located in the anode N-buffer region and surrounded by the anode N-buffer region; an emitter electrode located on the surface of the cathode N+ region, the cathode P+ region and the polysilicon auxiliary gate; and A collector electrode is located on the surface of the anode P+ region.

2. The SOI-LIGBT device according to claim 1, characterized in that: The anode P+ region, the anode N-buffer region, the drift region and the cathode P-well region constitute the first anode region PNP transistor of the device. When the device is forward-conducted, the first anode region PNP transistor is used to provide holes.

3. The SOI-LIGBT device according to claim 1, characterized in that: The anode P+ region, the anode N-buffer region, the drift region and the low-doped P-buried region constitute the second anode region PNP transistor of the device. When the device is forward-conducted, the second anode region PNP transistor is used to provide holes.

4. The SOI-LIGBT device according to claim 1, characterized in that: The P-buried region, the drift region, the cathode P-well region, the cathode P+ region, the deep trench oxide layer and the polysilicon auxiliary gate constitute a self-biased PMOS at the cathode of the device, wherein the deep trench oxide layer is the gate oxide layer of the self-biased PMOS, the P-buried region is the source of the self-biased PMOS, the drift region is the substrate of the self-biased PMOS, the cathode P-well region and the cathode P+ region are the drain of the self-biased PMOS, and the polysilicon auxiliary gate is the gate of the self-biased PMOS; the self-biased PMOS is used to control the opening and closing of the device, and provides an additional hole channel to reduce the energy loss when the device is turned off.

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