Integrated circuit standard sample wafer and test method thereof

Abstract

The invention belongs to the field of microelectronic metering testing, and particularly discloses an integrated circuit standard sample wafer and a testing method thereof, and the standard sample wafer comprises a substrate, and a system-on-chip SoC, an analog-to-digital converter, a digital-to-analog converter, a reference source and a data selector which are mounted on the top surface of the substrate; the SoC is used for controlling the output, acquisition and feedback control of a standard signal; the analog-to-digital converter is used for realizing acquisition and closed-loop feedback of standard signals; the digital-to-analog converter is used for realizing output and closed-loop feedback of a standard signal; the reference source is used for providing a reference voltage of the analog-to-digital converter and a reference voltage of the digital-to-analog converter; and the data selector is used for realizing channel switching of the data test system so as to realize multi-channel test of a single standard sample. According to the invention, the test work efficiency of the integrated circuit test system can be improved.

Description

Technical Field

[0001] The present application belongs to the field of microelectronics measurement and testing, and more specifically, relates to an integrated circuit standard sample and a testing method thereof. Background Art

[0002] As the core measurement equipment in the packaging and testing link of the integrated circuit manufacturing process, the integrated circuit test system plays an extremely important role in integrated circuit performance testing, yield improvement, identification and finalization, and is widely used in semiconductor packaging and testing companies, research institutes, universities and other units. According to its function, it can be divided into digital integrated circuit test system, analog integrated circuit test system, hybrid integrated circuit test system and SoC integrated circuit test system. According to the test content, it can be divided into functional test, structural test and parameter test. Parameter test is mainly divided into DC parameter test and AC parameter test. Whether the performance of the integrated circuit test system is good will directly affect the production of integrated circuits, so it must be calibrated regularly to ensure that the performance of the integrated circuit test system meets the use requirements during use.

[0003] At present, there are three main calibration methods for integrated circuit test systems: the first is to purchase integrated circuit test system calibration equipment from the equipment manufacturer and calibrate the equipment regularly. The problem is that the manufacturer's calibration equipment is bulky and usually built with several instruments. It is bulky and time-consuming and labor-intensive to carry out calibration work; the second is to use self-developed calibration equipment to calibrate the test system from the test channels of the test surface. The problem is that the test channels of large integrated circuit test systems range from hundreds to thousands, which is not suitable for actual calibration work; the third is to achieve it by studying parameter standards. Although the size of the device is greatly reduced and in-situ measurement is achieved, there is also the problem of low multi-channel calibration efficiency.

[0004] In summary, the current integrated circuit test system measurement method has the problems of large calibration device size, low working efficiency and inability to meet the multi-channel calibration of the integrated circuit test system. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of the present application is to provide an integrated circuit standard sample and a testing method thereof, aiming to solve the problem of low working efficiency of the current integrated circuit test system measurement method.

[0006] The present application provides an integrated circuit standard sample, comprising: a substrate, and a system-on-chip SoC, an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate;

[0007] The system-on-chip SoC is used to control the output, collection and feedback control of standard signals;

[0008] The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal;

[0009] The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback;

[0010] The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter;

[0011] The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample.

[0012] The present application integrates multiple functional modules such as analog-to-digital converter AD, digital-to-analog converter DA, reference source Source, system-on-chip SoC, etc. on the same substrate, which reduces the complexity of external connections, reduces signal transmission delay, and improves overall work efficiency. The introduction of data selectors makes multi-channel testing more flexible, and switching of different channels can be achieved through a single standard sample, reducing the number and complexity of test equipment, thereby improving test efficiency.

[0013] Optionally, a transfer board is mounted on the top surface of the substrate, and the transfer board is connected to the substrate via solder balls;

[0014] The analog-to-digital converter, digital-to-analog converter and reference source are formed into a first component by 3D stacking and mounted on the adapter board. The pins of the analog-to-digital converter, digital-to-analog converter and reference source are interconnected with the system-on-chip SoC through the adapter board.

[0015] Optionally, a plurality of data selectors are formed into a second component by 3D stacking and mounted on the adapter board, the pins of the data selector are interconnected with the system-on-chip SoC through the adapter board, and the other pins of the data selector are connected to the substrate through solder balls.

[0016] Optionally, it also includes a heat sink arranged in partitions, and a thermal conductive adhesive is provided between the heat sink and the first component and the system-on-chip SoC;

[0017] The data selector is arranged on the side of the heat sink and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

[0018] The design of the heat sink of the present application effectively manages the heat of the device, avoids performance degradation due to overheating, ensures that the system can still operate efficiently under high load, and improves working stability.

[0019] Optionally, the analog-to-digital converter cooperates with a system-on-chip (SoC) to specifically:

[0020] Collect high-precision standard signals;

[0021] Based on the standard signal, the pressure measurement, current measurement, current measurement, current measurement, and pressure measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

[0022] Optionally, the digital-to-analog converter cooperates with a system-on-chip (SoC) to specifically:

[0023] A high-precision standard signal is output to implement calibration of the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

[0024] The closed-loop feedback function of the analog-to-digital converter and digital-to-analog converter of the present application can monitor and adjust the signal in real time, so that the accuracy and stability of the system's standard signal acquisition and output are enhanced, the overall performance and response speed of the test system are improved, and the system can be ensured to respond quickly to changes during operation, thereby improving the dynamic performance and work efficiency of the system.

[0025] Optionally, the top surface of the substrate is used for mounting a bare chip, and the bottom surface of the substrate is provided with solder balls for introducing signals;

[0026] The bare chips are connected via through silicon vias, and the through silicon vias are used for signal transmission between the bare chips.

[0027] Optionally, the top surface of the substrate is also used for mounting active devices and passive devices, and a filtering circuit is built based on the active devices or passive devices to improve signal interference during signal transmission.

[0028] Optionally, the chip is packaged in a BGA format to reduce the chip area.

[0029] The present application also provides a standard sample testing method, including:

[0030] Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters;

[0031] The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions;

[0032] Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance;

[0033] Run standard samples in an accelerated aging environment to evaluate long-term reliability;

[0034] Conduct leak tests on standard samples to ensure there is no leakage during use;

[0035] All test results are tested for repeatability and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

[0036] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0037] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0038] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0039] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0040] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0041] (1) The present application integrates multiple functional modules such as analog-to-digital converter AD, digital-to-analog converter DA, reference source Source, system-on-chip SoC, etc. on the same substrate, which reduces the complexity of external connections, reduces signal transmission delay, and improves overall work efficiency. The introduction of data selectors makes multi-channel testing more flexible, and switching between different channels can be achieved through a single standard sample, reducing the number and complexity of test equipment, thereby improving test efficiency.

[0042] (2) The closed-loop feedback function of the analog-to-digital converter and digital-to-analog converter of the present application can monitor and adjust the signal in real time, so that the accuracy and stability of the system's standard signal acquisition and output are enhanced, the overall performance and response speed of the test system are improved, and the system can be ensured to respond quickly to changes during operation, thereby improving the dynamic performance and work efficiency of the system.

[0043] (3) The design of the heat sink of the present application effectively manages the heat of the device, avoids performance degradation due to overheating, ensures that the system can still operate efficiently under high load, and improves working stability.

[0044] (4) The present application uses chiplet technology to develop standard samples of integrated circuit test systems, which can calibrate the pressure measurement, pressure measurement, current measurement, current measurement, pressure measurement, power supply board, and voltage and current measurement functions in the precision test unit of the integrated circuit test system, so as to realize the chip-based and miniaturized integrated circuit test system calibration device, improve the measurement efficiency, and significantly increase the number of calibration channels. In addition, by adopting a closed-loop control method, the signal transmission line can be shortened to improve the measurement accuracy of the standard sample. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a complete structural schematic diagram of the standard sample provided in the embodiment of the present application;

[0046] Figure 2 It is a connection diagram of AD, DA, Source and adapter board provided in an embodiment of the present application;

[0047] Figure 3 It is a connection diagram of a data connector and an adapter board provided in an embodiment of the present application;

[0048] Figure 4 is a connection diagram of the Source bare chip and the adapter board provided in an embodiment of the present application;

[0049] Figure 5 It is a connection diagram of the AD bare chip and the adapter board provided in the embodiment of the present application;

[0050] Figure 6 It is a connection diagram of the DA bare chip and the adapter board provided in the embodiment of the present application;

[0051] Figure 7 It is a connection diagram of a data selector bare chip and an adapter board provided in an embodiment of the present application;

[0052] Figure 8 It is a flow chart of the standard sample testing method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0055] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0056] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0057] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0058] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0059] The present application provides an integrated circuit standard sample, comprising: a substrate, and a system-on-chip SoC, an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate;

[0060] The system-on-chip SoC is used to control the output, collection and feedback control of standard signals;

[0061] The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal;

[0062] The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback;

[0063] The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter;

[0064] The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample.

[0065] Furthermore, the analog-to-digital converter cooperates with the system-on-chip (SoC) to specifically:

[0066] Collect high-precision standard signals;

[0067] Based on the standard signal, the pressure measurement, current measurement, current measurement, current measurement, and pressure measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

[0068] Optionally, the digital-to-analog converter cooperates with a system-on-chip (SoC) to specifically:

[0069] A high-precision standard signal is output to implement calibration of the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

[0070] Specifically, refer to Figure 1 , Figure 1 It is a complete structural diagram of a standard sample. The integrated circuit standard sample mainly consists of a substrate 1, a first component 2 (including AD, DA, Source), a SoC 3, a data selector 4, a heat sink 5, a thermal conductive adhesive 6 and a solder ball 7.

[0071] In this embodiment, the substrate is the basis of the entire standard sample, and the structure is designed to carry various integrated circuit components. The top surface of the substrate is used to mount system-level chip SoC, analog-to-digital converter, digital-to-analog converter, reference source and data selector components, while the bottom surface is provided with solder balls to realize signal introduction.

[0072] The bare chips (unpackaged chips) on the substrate are connected by through-silicon vias, allowing signals to be efficiently transmitted between the bare chips.

[0073] The system-on-chip (SoC) is mainly responsible for controlling the output, acquisition and feedback control of standard signals. It integrates the control logic of the system and improves the efficiency and reliability of signal processing.

[0074] Analog-to-digital converter and digital-to-analog converter. The analog-to-digital converter is used for high-precision standard signal acquisition and closed-loop feedback to ensure signal accuracy. The digital-to-analog converter outputs high-precision standard signals for DC parameter calibration of the test system.

[0075] The reference source provides a stable reference voltage for analog-to-digital and digital-to-analog converters to ensure the accuracy of signal processing and conversion.

[0076] The data selector can realize channel switching of multi-channel testing and can select different test signal paths as needed, thus improving test flexibility and efficiency.

[0077] Optionally, a transfer board is mounted on the top surface of the substrate, and the transfer board is connected to the substrate via solder balls;

[0078] The analog-to-digital converter, digital-to-analog converter and reference source are formed into a first component by 3D stacking and mounted on the adapter board. The pins of the analog-to-digital converter, digital-to-analog converter and reference source are interconnected with the system-on-chip SoC through the adapter board.

[0079] Furthermore, a plurality of data selectors are formed into a second component by 3D stacking and mounted on the adapter board, the pins of the data selector are interconnected with the system-on-chip SoC through the adapter board, and the other pins of the data selector are connected to the substrate through solder balls.

[0080] Furthermore, it also includes a heat sink arranged in partitions, and a thermal conductive adhesive is provided between the heat sink and the first component and the system-on-chip SoC;

[0081] The data selector is arranged on the side of the heat sink and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

[0082] Reference Figure 2 , Figure 2 This is the connection diagram of AD, DA, Source and adapter board;

[0083] The adapter board 8 is connected to the substrate through solder balls 9. Source 21, AD22, and DA23 of the first component are mounted on the adapter board 8 in a 3D stacked form. The capacitor 10 and the filter 11 are arranged on the adapter board; and the through silicon via 12 is arranged on the first component.

[0084] Reference Figure 3 , Figure 3 It is a connection diagram of the data connector and the adapter board;

[0085] The adapter board 8 is connected to the substrate via solder balls 9 , the data selector 4 is mounted on the adapter board 8 by 3D stacking, and the through silicon via 12 is arranged on the data selector 4 .

[0086] The AD, DA, Source and data selector in this embodiment are mounted on the adapter board through the 3D stacking technology, the relevant pins are interconnected with the SoC through the adapter board, and the remaining pins are led out to the solder balls through the substrate. Multiple selectors are mounted on the adapter board through the 3D stacking technology, the relevant pins are interconnected with the SoC through the adapter board, and the remaining pins are led out to the solder balls through the substrate. The multi-channel test function of the standard sample is realized through this structure, and the partitioned independent heat dissipation method is adopted. Thermal conductive glue and heat dissipation cover are used for the SoC and AD / DA with high power consumption.

[0087] Specifically, the first component in this embodiment is composed of an analog-to-digital converter, a digital-to-analog converter and a reference source, which are mounted on the adapter board in a 3D stacking manner. The second component is composed of a plurality of data selectors stacked and independently mounted on the adapter board to facilitate effective signal switching in a complex signal environment.

[0088] On the one hand, the 3D stacking technology is used to maximize the space utilization of the analog-to-digital converter, the digital-to-analog converter and the reference source, while ensuring short-path signal connection and efficient transmission between the various components. The stacking design makes the signal transmission between AD, DA and Source faster and more stable, reducing signal delay and interference.

[0089] The adapter board is responsible for interconnecting the related pins of AD, DA and Source with the system-on-chip (SoC) to realize signal conversion, processing and transmission. The design of the adapter board ensures the reliability of electrical connection and signal integrity. The adapter board allows the selection of different signal sources and paths, and can flexibly switch signal states when performing multi-channel testing.

[0090] On the other hand, multiple data selectors are also implemented by vertical stacking, which saves board space and improves signal transmission efficiency. The stacking structure allows more selectors to be integrated in a limited space, enhancing the functionality of the system. The pins of each selector are interconnected with the system-on-chip (SoC) through an adapter board, thereby achieving flexible switching and management of signals.

[0091] The adapter board forms an electrical connection between the selector and the SoC, ensuring the effective transmission of different signal paths. Each selector can select a different signal source to facilitate multi-channel testing. The design of the adapter board is optimized to reduce signal interference and transmission delay, ensuring signal clarity between selectors.

[0092] In addition, the remaining pins of the selector and the adapter board lead out solder balls through the substrate and are connected to the external circuit. The solder balls provide reliable physical and electrical connections to ensure that the signal can be efficiently transmitted to the external test equipment. The structure of this embodiment supports testing multiple channels at the same time. By quickly switching the selector, real-time monitoring and control of different signal paths can be achieved to meet complex testing requirements. In addition, the 3D stacking technology makes full use of the vertical space, improves the integration, and reduces the occupied area of ​​the overall system.

[0093] The design of the heat sink takes thermal management into consideration and is connected to the first component and SoC through thermal conductive glue to reduce the operating temperature and prevent overheating to protect the device performance. A heat sink is set on the side of the data selector to ensure that it does not affect the temperature management of other modules.

[0094] The partition design of the heat sink classifies different components (such as analog-to-digital converters, digital-to-analog converters, and reference sources) to help optimize the heat dissipation performance of each module. Each partition can be appropriately designed according to its power consumption and heat generation, ensuring that each component can maintain an appropriate operating temperature under high load conditions.

[0095] Thermal conductive adhesive is used between the heat sink and the first component and the system-on-chip (SoC) to enhance thermal conductivity and ensure that heat can be quickly and effectively transferred from the components to the heat sink. This structural design can reduce the risk of performance degradation or failure caused by excessive temperature.

[0096] The data selector is arranged on the side of the heat sink, independent of the analog-to-digital converter, the digital-to-analog converter and the reference source, which helps to better isolate the signal, reduce possible interference and maintain signal integrity.

[0097] In this embodiment, the thermal management capability of the system in high-load scenarios is significantly improved by using heat sink partitions and thermal conductive adhesive. This will help extend component life, improve system stability, and reduce the probability of failure due to overheating. The independent setting of components not only optimizes heat dissipation and signal processing, but also increases the scalability and flexibility of the system.

[0098] Optionally, the top surface of the substrate is used for mounting a bare chip, and the bottom surface of the substrate is provided with solder balls for introducing signals;

[0099] Each bare chip is connected by a through silicon via, which is used to transmit signals between the bare chips. Through silicon vias are vertical channels formed by drilling holes in silicon wafers and filling them with conductive materials (such as copper or aluminum), allowing signals and power to be transmitted between different layers. Therefore, through silicon vias have an actual physical form and are an important component for achieving high-density interconnection in integrated circuits.

[0100] Reference Figure 4-Figure 7 , Figure 4 This is the connection diagram of the Source bare chip and the adapter board;

[0101] The Source 21 bare chip is connected to the adapter board 8 through the through silicon via 12 .

[0102] Figure 5 This is the connection diagram of the AD bare chip and the adapter board;

[0103] The AD22 bare chip is connected to the adapter board 8 through the through silicon via 12 .

[0104] Figure 6 This is the connection diagram of the DA bare chip and the adapter board;

[0105] The DA23 bare chip is connected to the adapter board 8 through the through silicon via 12;

[0106] Figure 7 This is a connection diagram of the data selector bare chip and the adapter board;

[0107] The bare chip of the data selector 4 is connected to the adapter board 8 through a through silicon via 12 .

[0108] The bare chip in this embodiment refers to a bare die, which is an integrated circuit chip that has not been packaged. It is usually a silicon chip processed by the wafer manufacturing process, including circuits and functions, but without any external packaging protection.

[0109] The characteristics of a bare die are as follows:

[0110] Directly exposed chip: Since there is no package, the bare die is directly exposed to the outside, which allows for higher density arrangement and more effective thermal management.

[0111] Connection method: During the manufacturing process, these bare dies can be directly mounted to the substrate by welding or bonding, usually using solder balls or conductive glue.

[0112] Application scenarios: Bare dies are widely used in high-performance and high-frequency electronic devices, such as RFID, communication equipment, microprocessors and sensors.

[0113] Advantages: Using bare die can reduce size, weight and increase signal transmission speed while reducing packaging costs and latency.

[0114] By mounting the die directly on the substrate, more compact designs and higher integration levels can be achieved.

[0115] Optionally, the top surface of the substrate is also used for mounting active devices and passive devices, and a filtering circuit is built based on the active devices or passive devices to improve signal interference during signal transmission.

[0116] Specifically, the top surface of the substrate is used to mount active devices (such as amplifiers, oscillators, etc.) and passive devices (such as resistors, capacitors, etc.). This design enables signal processing and filtering circuits to be compactly integrated, reducing the path length of signal transmission, thereby reducing signal loss and interference.

[0117] Filter circuits based on active and passive components can effectively suppress interference during signal transmission. Filter circuits can selectively pass signals of specific frequencies and block unnecessary noise and interference signals, thereby improving the signal quality of the system. By properly selecting active and passive components, different types of filter circuits (such as low-pass, high-pass, band-pass, etc.) can be designed according to specific application requirements to meet different signal processing requirements.

[0118] In addition, the combination of heat sink and active components ensures that the components can effectively dissipate heat under high load conditions to prevent overheating and performance degradation. The use of thermal conductive adhesive further enhances the heat dissipation effect and ensures the stability of signal processing. By integrating active and passive components on the same substrate, the overall integration of the system is improved and the complexity of external connections is reduced.

[0119] This embodiment effectively improves the anti-interference ability of the signal during transmission by mounting active and passive components on the top surface of the substrate and building a filtering circuit. At the same time, combined with heat dissipation management and independent arrangement of data selectors, the overall system shows significant advantages in performance, stability and flexibility.

[0120] Furthermore, the chip is packaged in a BGA format to reduce the chip area.

[0121] This embodiment reduces the chip area by adopting the BGA packaging form, which helps to improve the layout density and reduce the interference during signal transmission. The filter circuit built based on active devices and passive devices significantly improves the anti-interference ability of the signal during transmission and improves the overall performance of the system.

[0122] This embodiment is packaged in the form of BGA (ball grid array), which can effectively reduce the chip area and improve integration and performance. BGA packaging reduces the space required for traditional pin packaging by placing solder balls directly at the bottom of the chip, thereby effectively reducing the occupied area of ​​the entire chip. The design of BGA packaging helps to quickly dissipate heat. With the use of a heat sink, the heat generated by the chip during operation can be effectively managed to ensure stable operation of the system.

[0123] The present application also provides a standard sample testing method, including:

[0124] Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters;

[0125] The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions;

[0126] Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance;

[0127] Run standard samples in an accelerated aging environment to evaluate long-term reliability;

[0128] Conduct leak tests on standard samples to ensure there is no leakage during use;

[0129] All test results are tested for repeatability and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

[0130] Reference Figure 8In this embodiment, the standard sample is subjected to room temperature initial test, screening test, and three-temperature measurement. The screening test includes stability baking, temperature cycling, aging test, leak detection, etc. All screening tests are carried out in accordance with national or defense standards, and then repeatability and stability assessments are performed on them, and finally the standard samples of the integrated circuit test system that meet the requirements are screened out.

[0131] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0132] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An integrated circuit standard sample, characterized in that: include: A substrate, and a system-on-chip (SoC), an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate; The system-on-chip SoC is used to control the output, collection and feedback control of standard signals; The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal; The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback; The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter; The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample.

2. The integrated circuit standard sample according to claim 1, characterized in that: An adapter plate is mounted on the top surface of the substrate, and the adapter plate is connected to the substrate via solder balls; The analog-to-digital converter, digital-to-analog converter and reference source are formed into a first component by 3D stacking and mounted on the adapter board. The pins of the analog-to-digital converter, digital-to-analog converter and reference source are interconnected with the system-on-chip SoC through the adapter board.

3. The integrated circuit standard sample according to claim 2, characterized in that: A plurality of data selectors are formed into a second component by 3D stacking and mounted on the adapter board. The pins of the data selectors are interconnected with the system-on-chip SoC through the adapter board, and the other pins of the data selectors are connected with the substrate through solder balls.

4. The integrated circuit standard sample according to claim 2, characterized in that: It also includes a heat sink arranged in partitions, and thermal conductive glue is provided between the heat sink and the first component and the system-on-chip SoC; The data selector is arranged on the side of the heat sink and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

5. The integrated circuit standard sample according to claim 1, characterized in that: The analog-to-digital converter cooperates with the system-on-chip SoC and is specifically used for: Collect high-precision standard signals; Based on the standard signal, the pressure measurement, current measurement, current measurement, current measurement, and pressure measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

6. The integrated circuit standard sample according to claim 1, characterized in that: The digital-to-analog converter cooperates with the system-on-chip SoC and is specifically used for: A high-precision standard signal is output to implement calibration of the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

7. The integrated circuit standard sample according to claim 1, characterized in that: The top surface of the substrate is used for mounting bare chips, and the bottom surface of the substrate is provided with solder balls for introducing signals; The bare chips are connected via through silicon vias, and the through silicon vias are used for signal transmission between the bare chips.

8. The integrated circuit standard sample according to claim 1, characterized in that: The top surface of the substrate is also used for mounting active devices and passive devices, and a filter circuit is built based on the active devices or passive devices to improve signal interference during signal transmission.

9. The integrated circuit standard sample according to claim 1, characterized in that: The chip is packaged in BGA format to reduce the chip area.

10. A standard sample testing method based on the integrated circuit standard sample according to any one of claims 1 to 9, characterized in that: include: Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters; The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions; Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance; Run standard samples in an accelerated aging environment to evaluate long-term reliability; Conduct leak tests on standard samples to ensure there is no leakage during use; All test results are tested for repeatability and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

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