Clock tree synthesis method
By building virtual and actual clock trees in the clock tree synthesis stage, considering the topological structure and OCV information of the clock tree, calculating the non-uniform timing margin and inserting the specified clock elements, the problem of poor timing convergence in the existing technology is solved, and better timing stability and design effects are achieved.
Patent Information
- Application Number
- CN202411603309.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art fails to effectively consider on-chip deviation (OCV) during the clock tree synthesis stage, resulting in poor timing convergence effect and prone to timing violations and functional errors.
In the beginning stage of clock tree synthesis, by building a virtual clock tree and an actual clock tree, considering the topology and OCV information of the clock tree, compute the non-uniform timing margin, and insert a specified type of clock buffer or clock inverter during clock tree synthesis to optimize timing.
By considering the actual topology structure and OCV information of the clock tree, the timing convergence effect is improved, the occurrence of timing violations is reduced, and the timing stability of the design is improved.
Smart Images
Figure CN119514477A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of physical design of synchronous digital integrated circuits and relates to a clock tree synthesis method. By considering on-chip variation (OCV) at the beginning stage of clock tree synthesis, a better clock tree clock skew is obtained, which is ultimately beneficial to the timing convergence of the design. Background Art
[0002] As the process of integrated circuits shrinks to deep submicron, due to process deviations in the manufacturing stage, the parameters of the same type of devices on the same die or on different dies on the same wafer show increasingly larger numerical differences. This difference is the on-chip deviation - OCV. OCV affects the difficulty of timing convergence: a larger OCV leads to a larger loss of timing margin, which is prone to timing violations in the timing analysis stage, resulting in functional errors in the final produced chip. This effect is more obvious when the clock frequency is higher.
[0003] In order to reduce the impact of OCV on timing, current electronic design automation (EDA) tools usually add a uniform timing margin in the clock tree synthesis (CTS) stage. Although this method takes into account the impact of OCV, it does not consider the actual topological structure of the clock tree, and the effect on timing convergence is still not significant. Summary of the invention
[0004] (I) Purpose of the invention
[0005] The purpose of the present invention is to provide a clock tree synthesis method, which improves the timing convergence effect while considering the actual topological structure of the clock tree.
[0006] (II) Technical solution
[0007] In order to solve the above technical problems, the present invention provides a clock tree synthesis method, which comprises the following steps:
[0008] Step 1: At the beginning of clock tree synthesis, select the clock tree topology based on the design input;
[0009] Step 2: Create a virtual clock tree according to the topological structure of the clock tree;
[0010] Step 3: Build the actual clock tree based on the OCV information of the clock tree.
[0011] In step 1, the selected clock tree topology structure is an H-type clock tree structure.
[0012] In step 2, the process of creating a virtual clock tree is as follows:
[0013] Step 21: Classify the clock tree sink points according to functional relevance, and group the clock tree sink points with timing relevance into a set;
[0014] Step 22: Place a buffer, namely the clock guide buffer, in front of each type of sink set;
[0015] Step 23: Make a virtual connection from the output of the guide buffer to the clock end of the clock tree sink.
[0016] In step 3, the process of building the actual clock tree is:
[0017] Step 31: Obtain the OCV deviation t of the clock path and data path based on the topological physical information of the virtual clock tree ocv_clock and t ocv_data ;
[0018] Step 32: Obtain the non-uniform timing margin t based on the OCV information ocv ;
[0019] Step 33: Calculate the current timing path setup time slack and hold time slack, and calculate the c of each sink point set based on the timing slack information. adi Adjustment factor is adjusted;
[0020] Step 34: Based on the non-uniform timing margin t ocv Perform final clock tree synthesis.
[0021] In step 32, the OCV information is used to obtain the non-uniform timing margin t ocv Determined by the physical distance between the clock root point and the clock sink point.
[0022] In step 32, t ocv Calculated as:
[0023] t ocv =L×C ocv ×C adj
[0024] Where L is the physical distance between the root point and the clock sink point, c ocv is the OCV delay coefficient, the value of which is determined by the process node information; c adj is the adjustment coefficient corresponding to the sink point set, c adj The default value is 1, and the increase or decrease is determined by the values of the setup time slack and hold time slack calculated subsequently.
[0025] In step 33, the adjustment coefficient is adjusted by: if the setup time slack is negative, that is, there is a timing violation in the setup time, then the OCV deviation t ocv_data The corresponding c adj Increase the adjustment range to ensure that the calculated timing path setup time does not violate the OCV. If the hold time slack is negative, that is, there is a timing violation in the hold time, the OCV deviation t of the timing path data path is ocv_data The corresponding c adj Adjust it down to a smaller value so that the calculated timing path hold time considering OCV does not violate any rule.
[0026] In step 34, during clock tree synthesis, the non-uniform timing margin t determined in the previous step is ocv Superimposed on the target clock tree delay, on the basis of meeting the maximum fan-out and maximum load capacitance design rules, insert the specified type of clock buffer or clock inverter on the path from the clock root to the clock sink to build a complete clock tree network.
[0027] (III) Beneficial effects
[0028] The clock tree synthesis method provided by the above technical solution adds a non-uniform timing margin to the clock tree network while considering OCV in the CTS stage. The margin is related to the topological structure of the clock tree. A virtual clock tree is constructed at the beginning of the clock tree synthesis stage, and the value of the non-uniform timing margin is added according to the OCV and timing information of the virtual clock tree, so as to finally obtain a timing-optimized clock tree network. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 The figure is a flow chart of the clock tree synthesis method of the present invention.
[0030] Figure 2 A schematic diagram of a clock tree topology.
[0031] Figure 3 A schematic diagram of a virtual clock tree.
[0032] Figure 4 The figure is a schematic diagram of a clock tree constructed based on OCV information. DETAILED DESCRIPTION
[0033] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.
[0034] like Figure 1 As shown, the clock tree synthesis method of this embodiment includes the following steps:
[0035] Step 1: At the beginning of clock tree synthesis, the clock tree topology is selected based on the design input.
[0036] The clock tree topology selected in this embodiment is: Figure 2 The H-type clock tree structure is shown.
[0037] Step 2: Create a virtual clock tree based on the topological structure of the clock tree.
[0038] like Figure 3 As shown in the figure, the process of creating a virtual clock tree is:
[0039] Step 21: Classify the clock tree sink points according to functional relevance, and group the clock tree sink points with timing relevance into a set;
[0040] Step 22: Place a buffer, namely the clock guide buffer, in front of each type of sink set;
[0041] Step 23: Make a virtual connection from the output of the guide buffer to the clock end of the clock tree sink.
[0042] Step 3: Build the actual clock tree based on the OCV information of the clock tree.
[0043] like Figure 4 As shown in the figure, the process of building the actual clock tree is:
[0044] Step 31: Obtain the OCV deviation t of the clock path and data path based on the topological physical information of the virtual clock tree ocv_clock and t oc_vdata
[0045] Step 32: Obtain the non-uniform timing margin t based on the OCV information ocv .
[0046] OCV information to obtain non-uniform timing margin t ocv Determined by the physical distance between the clock root point and the clock sink point.
[0047] t ocv Calculated as:
[0048] t ocv =L×C ocv ×C adj
[0049] Where L is the physical distance between the root point and the clock sink point, c ocv is the OCV delay coefficient, the value of which is determined by the process node information; c adj is the adjustment coefficient corresponding to the sink point set, Cadj The default value is 1, and the increase or decrease is determined by the values of the setup time slack and hold time slack calculated subsequently.
[0050] Step 33: Calculate the current timing path setup time slack and hold time slack, and calculate the C of each sink point set based on the timing slack information. adj Adjustment factor.
[0051] The adjustment coefficient is adjusted as follows: If the setup time slack is negative, that is, there is a timing violation in the setup time, then the OCV deviation t of the timing path data path is adjusted. ocv_data The corresponding C adj Increase the adjustment range to ensure that the calculated timing path setup time does not violate the OCV. If the hold time slack is negative, that is, there is a timing violation in the hold time, the OCV deviation t of the timing path data path is ocv_data The corresponding C adj Adjust it down to a smaller value so that the calculated timing path hold time considering OCV does not violate any rule.
[0052] Step 34: Based on the non-uniform timing margin t ocv Perform final clock tree synthesis.
[0053] During clock tree synthesis, the non-uniform timing margin t determined in the previous step is ocv Superimposed on the target clock tree delay (clock latency), insert a specified type of clock buff on the path from the clock root to the clock sink based on the design rules such as maximum fanout and maximum load capacitance. r or clock invert r , thereby building a complete clock tree network.
[0054] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A clock tree synthesis method, characterized in that: The following steps are involved: Step 1: At the beginning of clock tree synthesis, select the clock tree topology based on the design input; Step 2: Create a virtual clock tree according to the topological structure of the clock tree; Step 3: Build the actual clock tree based on the OCV information of the clock tree.
2. The clock tree synthesis method according to claim 1, characterized in that: In step 1, the selected clock tree topology structure is an H-type clock tree structure.
3. The clock tree synthesis method according to claim 2, characterized in that: In step 2, the process of creating a virtual clock tree is as follows: Step 21: Classify the clock tree sink points according to functional relevance, and group the clock tree sink points with timing relevance into a set; Step 22: Place a buffer, namely the clock guide buffer, in front of each type of sink set; Step 23: Make a virtual connection from the output of the guide buffer to the clock end of the clock tree sink.
4. The clock tree synthesis method according to claim 3, characterized in that: In step 3, the process of building the actual clock tree is: Step 31: Obtain the OCV deviation t of the clock path and data path based on the topological physical information of the virtual clock tree ocv_clock and t ocv_data ; Step 32: Obtain the non-uniform timing margin t based on the OCV information ocv ; Step 33: Calculate the current timing path setup time slack and hold time slack, and calculate the C of each sink point set based on the timing slack information. adj Adjustment factor is adjusted; Step 34: Based on the non-uniform timing margin t ocv Perform final clock tree synthesis.
5. The clock tree synthesis method according to claim 4, characterized in that: In step 32, the OCV information is used to obtain the non-uniform timing margin t ocv Determined by the physical distance between the clock root point and the clock sink point.
6. The clock tree synthesis method according to claim 5, characterized in that: In step 32, t ocv Calculated as: t ocv =L×C ocv ×C adj Where L is the physical distance between the root point and the clock sink point, C ocv is the OCV delay coefficient, the value of which is determined by the process node information; C adj is the adjustment coefficient corresponding to the sink point set, C adj The default value is 1, and the increase or decrease is determined by the values of the setup time slack and hold time slack calculated subsequently.
7. The clock tree synthesis method according to claim 6, characterized in that: In step 33, the adjustment coefficient is adjusted by: if the setup time slack is negative, that is, there is a timing violation in the setup time, then the OCV deviation t ocv_data The corresponding C adj Increase the adjustment range to ensure that the calculated timing path setup time does not violate the OCV. If the hold time slack is negative, that is, there is a timing violation in the hold time, the OCV deviation t of the timing path data path is ocv_data The corresponding C adj Adjust it down to a smaller value so that the calculated timing path hold time considering OCV does not violate any rule.
8. The clock tree synthesis method according to claim 7, characterized in that: In step 34, during clock tree synthesis, the non-uniform timing margin t determined in the previous step is ocv Superimposed on the target clock tree delay, on the basis of meeting the maximum fan-out and maximum load capacitance design rules, insert the specified type of clock buffer or clock inverter on the path from the clock root to the clock sink to build a complete clock tree network.
9. A clock tree, characterized in that: The method is comprehensively implemented by any one of claims 1 to 8.
10. An application of the method according to any one of claims 1 to 8 in the field of physical design of synchronous digital integrated circuits.