Transmission circuit, reception circuit, integrated circuit chip, and test method

Abstract

The embodiment of the invention provides a transmitting circuit, a receiving circuit, an integrated circuit chip and a test method. The transmitting circuit comprises a test data generation module, a to-be-tested transmitting module, a test receiving module and a test data detection module, wherein the test data generation module is configured to generate first test data; the to-be-tested sending module is configured to generate second test data based on the first test data; the test receiving module is configured to generate third test data based on the second test data; the test data detection module is configured to receive third test data and detect whether the third test data is consistent with the first test data, and the to-be-tested sending module is further configured to receive a first clock signal with an adjustable phase. The test receiving module and / or the test data detection module are / is further configured to receive a phase-adjustable second clock signal. According to the sending circuit, the circuit performance can be prevented from being affected, and performance testing, screening and grading of a physical layer circuit are achieved in the wafer testing stage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a transmitting circuit, a receiving circuit, an integrated circuit chip, and a testing method. Background Art

[0002] In a system-in-a-package (SIP), advanced packaging technologies such as 2D, 2.5D or 3D are usually used to integrate multiple chiplets together to realize a complete and complex system.

[0003] Core particles, also known as chiplets, refer to pre-manufactured, functional, and combinable dies. A die is a small piece cut from a silicon wafer, and is a crystal before the chip is packaged. In advanced packaging, data transmission between dies needs to be achieved through die-to-die (D2D) technology. The physical layer (PHY) circuit used for die-to-die interconnection is the physical layer interface responsible for achieving high-speed data transmission between different dies. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a sending circuit, comprising: a test data generating module, a sending module to be tested, a test receiving module, and a test data detecting module, wherein the test data generating module is configured to generate first test data; the sending module to be tested is configured to generate second test data based on the first test data, and output it to the test receiving module; the test receiving module is configured to generate third test data based on the second test data, and output it to the test data detecting module; the test data detecting module is configured to receive the third test data, and detect whether the third test data is consistent with the first test data, wherein the sending module to be tested is also configured to receive a first clock signal, and the test receiving module and / or the test data detecting module are also configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

[0005] The sending circuit provided in at least one embodiment of the present disclosure further includes: an input selection module, configured to receive the first test data for testing and the first sending data for data transmission, and output them to the sending module to be tested after selection.

[0006] In the transmitting circuit provided by at least one embodiment of the present disclosure, the transmitting module to be tested is further configured to generate second transmitting data based on the first transmitting data, and output the second transmitting data to a transmitting port of the transmitting circuit.

[0007] In the transmitting circuit provided by at least one embodiment of the present disclosure, the input reference voltage of the test receiving module is adjustable.

[0008] In the transmitting circuit provided in at least one embodiment of the present disclosure, the transmitting module to be tested includes a buffer, a parallel-to-serial circuit and a driving circuit, and the buffer, the parallel-to-serial circuit and the driving circuit are connected in sequence, the buffer is configured to receive a third clock signal as a write clock, and the test data generating module is also configured to receive the third clock signal.

[0009] In the transmitting circuit provided in at least one embodiment of the present disclosure, the parallel-to-serial circuit is configured to receive the first clock signal, and the buffer is configured to receive a fourth clock signal obtained by dividing the first clock signal as a read clock.

[0010] In the transmitting circuit provided in at least one embodiment of the present disclosure, the first test data is multi-bit data of the first rate, the second test data is one-bit data of the second rate, the third test data is one-bit data of the second rate or multi-bit parallel data of the first rate, and the second rate is higher than the first rate.

[0011] At least one embodiment of the present disclosure provides a receiving circuit, comprising: a test data generating module, a receiving module to be tested and a test data detecting module, wherein the test data generating module is configured to generate first test data; the receiving module to be tested is configured to generate second test data based on the first test data, and output it to the test data detecting module; the test data detecting module is configured to receive the second test data, and detect whether the second test data is consistent with the first test data, wherein the test data generating module is also configured to receive a first clock signal, the receiving module to be tested is also configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

[0012] In the receiving circuit provided in at least one embodiment of the present disclosure, the input reference voltage of the receiving module to be tested is adjustable.

[0013] The receiving circuit provided in at least one embodiment of the present disclosure further includes: a test driving circuit configured to provide an adjustable driving capability for the first test data.

[0014] The receiving circuit provided in at least one embodiment of the present disclosure further includes: a test data processing module configured to convert the rate of the first test data from a first rate to a higher-speed second rate.

[0015] In the receiving circuit provided by at least one embodiment of the present disclosure, the test data processing module is further configured to receive the first clock signal.

[0016] In the receiving circuit provided by at least one embodiment of the present disclosure, the test data detection module is configured to receive a third clock signal obtained by dividing the second clock signal.

[0017] In the receiving circuit provided in at least one embodiment of the present disclosure, the receiving module to be tested includes an analog front end, a sampling circuit and a serial-to-parallel circuit, and the analog front end, sampling circuit and serial-to-parallel circuit are connected in sequence, and the sampling circuit and / or serial-to-parallel circuit are configured to receive the second clock signal; the input reference voltage of the analog front end is adjustable.

[0018] In the receiving circuit provided by at least one embodiment of the present disclosure, the first test data is one bit of second rate data or multiple bits of first rate data, the second test data is multiple bits of first rate data, and the second rate is higher than the first rate.

[0019] At least one embodiment of the present disclosure provides an integrated circuit chip, comprising: the transmitting circuit as described in at least one embodiment above, and / or the receiving circuit as described in at least one embodiment above.

[0020] In the integrated circuit chip provided in at least one embodiment of the present disclosure, the integrated circuit chip includes a plurality of dies interconnected and communicating with each other, and at least one of the plurality of dies includes the transmitting circuit and / or the receiving circuit.

[0021] At least one embodiment of the present disclosure provides a method for testing a transmitting circuit according to at least one of the above-mentioned embodiments, comprising: adjusting a phase difference between the first clock signal and the second clock signal; for each phase difference, recording a test result output by the test data detection module to obtain a one-dimensional eye diagram; and performing a performance test on the transmitting circuit according to the eye width of the one-dimensional eye diagram.

[0022] In the test method provided by at least one embodiment of the present disclosure, after adjusting the phase difference between the first clock signal and the second clock signal, it also includes: for each phase difference value, adjusting the input reference voltage of the test receiving module, for each input reference voltage, recording the test result output by the test data detection module to obtain a two-dimensional eye diagram; and performing a performance test on the transmitting circuit according to the eye width and eye height of the two-dimensional eye diagram.

[0023] The test method provided in at least one embodiment of the present disclosure also includes: adjusting the driving capability of the driving circuit in the tested sending module to simulate the channel performance after packaging; or adjusting the receiving capability of the tested receiving module to simulate the performance of the receiving circuit connected to the sending circuit after packaging; determining the packaging position of the sending circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram.

[0024] At least one embodiment of the present disclosure provides a method for testing a receiving circuit according to at least one of the above-mentioned embodiments, comprising: adjusting a phase difference between the first clock signal and the second clock signal; for each phase difference, recording a test result output by the test data detection module to obtain a one-dimensional eye diagram; and performing a performance test on the receiving circuit according to the eye width of the one-dimensional eye diagram.

[0025] In the test method provided by at least one embodiment of the present disclosure, after adjusting the phase difference between the first clock signal and the second clock signal, it also includes: for each phase difference value, adjusting the input reference voltage of the receiving module to be tested, for each input reference voltage, recording the test result output by the test data detection module to obtain a two-dimensional eye diagram; and performing a performance test on the receiving circuit according to the eye width and eye height of the two-dimensional eye diagram.

[0026] The test method provided in at least one embodiment of the present disclosure also includes: adjusting the driving capability of the test driving circuit in the receiving circuit to simulate the signal quality received by the receiving port of the receiving circuit after packaging; or adjusting the receiving capability of the analog front end in the receiving module to be tested to simulate the performance fluctuation of the receiving circuit after packaging; determining the packaging position of the receiving circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0028] Figure 1A A schematic diagram of the interconnection between dies in a system-level package;

[0029] Figure 1B It is a schematic diagram of a physical layer circuit for interconnection between tube chips;

[0030] Figure 1C It is a schematic diagram of a physical layer circuit for interconnection between tube chips;

[0031] Figure 2A A schematic block diagram of a transmitting circuit provided in at least one embodiment of the present disclosure;

[0032] Figure 2B A schematic diagram of a sending circuit provided by at least one embodiment of the present disclosure;

[0033] Figure 3A A schematic block diagram of a receiving circuit provided for at least one embodiment of the present disclosure;

[0034] Figure 3BA schematic diagram of a receiving circuit provided by at least one embodiment of the present disclosure;

[0035] Figure 4 A schematic diagram of a physical layer circuit for interconnecting dies provided by at least one embodiment of the present disclosure;

[0036] Figure 5 A schematic block diagram of an integrated circuit chip provided for at least one embodiment of the present disclosure;

[0037] Fig. 6A A flowchart of a method for testing a transmitting circuit provided in at least one embodiment of the present disclosure;

[0038] Figure 6B A flowchart of a method for testing a transmitting circuit provided in at least one embodiment of the present disclosure;

[0039] Fig. 7A A flowchart of a method for testing a receiving circuit provided in at least one embodiment of the present disclosure;

[0040] Figure 7B A flowchart of a method for testing a receiving circuit provided in at least one embodiment of the present disclosure;

[0041] Fig. 8A A schematic diagram of a one-dimensional eye diagram recording table provided for at least one embodiment of the present disclosure;

[0042] Figure 8B A schematic diagram of a two-dimensional eye diagram recording table provided for at least one embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of a method for testing data transmission from a sending circuit to a receiving circuit provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components (elements) may be omitted. When any part (element) of the embodiments of the present disclosure appears in more than one figure, the part (element) is represented by the same or similar reference numeral in each figure.

[0047] In system-level packaging, advanced packaging technologies such as 2D, 2.5D or 3D are usually used to integrate multiple cores together to achieve a complete and complex system. In advanced packaging, data transmission between each die needs to be achieved through die-to-die (D2D) technology. Die-to-die interconnection technology is an advanced interconnection technology that has gradually emerged with the growth of the semiconductor industry's demand for high-performance computing and the slowdown of Moore's Law. It is the core of core development and has the characteristics of large channels and dense wiring. Related to this is the die-to-die interconnection physical layer (PHY) circuit, which is the physical layer interface responsible for achieving high-speed data transmission between different dies.

[0048] Figure 1A Schematic diagram of the interconnection between dies in a system-level package. Figure 1A As shown in the figure, DIE 0 to DIE 3 belong to the same type of core 1, and DIE 4 to DIE 5 belong to another type of core 2. The data transmission rate requirements between different cores are different: for example, the interconnection rate between DIE 0, DIE 1, DIE 2 and DIE 3 is the highest, the interconnection rate between DIE 0, DIE 1, DIE 2, DIE 3 and DIE 4, DIE 5 is the second lowest, and the interconnection rate between DIE 4 and DIE 5 is the lowest.

[0049] exist Figure 1AIn the case of a 1-channel interconnection, even at the same transmission rate, the lengths of different channels are different. For example, the interconnection lines between DIE 0-DIE 1, DIE 1-DIE 2, DIE 2-DIE 3, and DIE 0-DIE 3 are relatively short, while the interconnection lines between DIE0-DIE 2 and DIE 1-DIE 3 are relatively long. Channels of different lengths have different effects on the performance of the inter-die interconnection physical layer circuit (hereinafter also referred to as the inter-die interconnection interface).

[0050] like Figure 1A As shown, each die has multiple inter-die interconnection interfaces, such as PHY0-PHY5, which are interconnected with different dies. Even the same inter-die interconnection interface on the same die may have different performance requirements due to the different positions of the die in the package.

[0051] Due to defects in the production process, there is a possibility of performance and function anomalies between dies and between different inter-die interconnection interfaces within a die. If the performance and function of the inter-die interconnection interfaces in each die are not screened and graded before packaging, the packaged chip may have data transmission errors between the dies, resulting in performance degradation and functional errors of the entire chip, or even causing the chip to become a waste. Therefore, at each stage of chip production, the function and performance of the inter-die interconnection interfaces need to be screened and graded to detect and resolve problems as early as possible, thereby effectively controlling costs and improving yields.

[0052] Chip production includes wafer test, packaging, and final test (FT). Wafer test, also known as chip probing (CP), is to test the wafer before the chip is packaged, so that the problematic chips can be screened out before packaging, saving packaging costs. Final test refers to the test of chip function, performance, and reliability after the chip is packaged.

[0053] During the wafer testing phase, it is necessary to perform transmission performance tests on the inter-die interconnect interfaces on the die, screen out inter-die interconnect interfaces with abnormal functions, and grade the performance of the inter-die interconnect interfaces based on the test results.

[0054] During the packaging phase, it is necessary to select dies of different performance levels based on application performance requirements and the usage of the interconnection interfaces between dies. Figure 1AIn the process, if PHY 0 in core 1 has abnormal function, such core can be placed in DIE 0 or DIE 2 during packaging; if PHY 4 performance degradation occurs in core 1, such core can be placed in DIE 1 or DIE 3. The above method can realize the maximum utilization of each die, and at the same time make the overall performance of the chip meet the system requirements, thereby reducing the production cost to the greatest extent on the basis of meeting the system requirements.

[0055] In the final test phase, the data transmission function and performance test of each interconnected die interconnection interface is required to verify whether its function is normal and whether the performance meets the application requirements, and to screen out chips that do not meet the requirements.

[0056] Figure 1B The present invention is a schematic diagram of a physical layer circuit for interconnection between tube chips.

[0057] For example, Figure 1B As shown, the inter-die interconnection physical layer circuit includes a transmitting circuit and a receiving circuit. In the transmitting circuit, data starts from the transmitting data source and flows to the transmitting port (PAD1) through the transmitting module; in the receiving circuit, data flows in from the receiving port (PAD2) and flows to the receiving data output direction through the transmitting module. The inter-die interconnection physical layer circuit has a single-ended, unidirectional transmission characteristic, that is, the transmitting channel (TX lane) implemented by the transmitting circuit is only responsible for sending single-ended signals and does not have a receiving function; the receiving channel (RX lane) implemented by the receiving circuit is only responsible for receiving single-ended signals and does not have a transmitting function. Therefore, in the wafer testing stage, the inter-die interconnection physical layer circuit cannot directly form a test loop for loopback testing, and an additional test loop needs to be designed to verify the function and performance of the inter-die interconnection physical layer circuit. Loopback testing refers to the act of sending an electronic signal or data stream back to the sender as is, and is mainly used to verify the function of the communication link.

[0058] Figure 1C The present invention is a schematic diagram of a physical layer circuit for interconnection between tube chips.

[0059] For example, Figure 1C As shown, in order to implement loopback testing, some solutions are Figure 1B On the basis of the present invention, a transmission path is added between the transmitting circuit and the receiving circuit, and the connection state of the path is controlled by a switch SW0 or a similar mechanism.

[0060] When performing a loopback test, switch SW0 is closed to connect the sending circuit to the receiving circuit. By comparing the data sent by the sending circuit and the data received by the receiving circuit, the circuit function is judged to be correct and the performance is good. If the sent data is consistent with the received data, it indicates that the function of the physical layer circuit of the inter-die interconnection is normal and the performance meets the requirements.

[0061] When data is transmitted normally, the switch SW0 is turned off, thereby disconnecting the connection between the transmitting circuit and the receiving circuit. The transmitting circuit sends data to the opposite end (ie, the receiving circuit of another die), and the receiving circuit receives the data sent by the opposite end (ie, the transmitting circuit of another die).

[0062] The inventors of the present disclosure have noticed that there are some problems with the above solution:

[0063] 1. The physical layer circuits for interconnecting dies generally have the characteristics of multiple channels, such as 16, 32, 64 or even more channels. In the above scheme, the transmitting circuit and the receiving circuit need to form a test loop one by one, which will increase the complexity of design and testing.

[0064] 2. Considering the internal layout of the physical layer circuits of the packaging and inter-die interconnection, the transmitting circuit and the receiving circuit are usually laid out together, resulting in long routing when the transmitting circuit and the receiving circuit are interconnected. Long routing consumes a lot of routing resources, making the design more difficult to implement; there may be crosstalk between long routings, affecting the test results and causing misjudgment; long routing also brings large parasitic capacitance, affecting performance.

[0065] 3. If the driver unit of the transmitting circuit is used directly in the loopback test, the parasitic capacitance caused by the long wiring will increase the load of the driver unit and affect the final performance of the transmitting circuit; in the normal working mode, due to the coupling capacitors on both sides of SW0, even if SW0 is disconnected, the high-speed data sent by the transmitting circuit may affect the input data received by the receiving port of the receiving circuit. The above problems can be solved by adding a new driver unit, but since a stronger driving capability is required, the driver unit will occupy a larger area and increase the cost.

[0066] 4. The length of each pair of connecting lines and environmental factors vary, affecting the accuracy of the test results.

[0067] At least one embodiment of the present disclosure provides a sending circuit, which includes: a test data generating module, a sending module to be tested, a test receiving module, and a test data detection module, wherein the test data generating module is configured to generate first test data; the sending module to be tested is configured to generate second test data based on the first test data, and output it to the test receiving module; the test receiving module is configured to generate third test data based on the second test data, and output it to the test data detection module; the test data detection module is configured to receive the third test data, and detect whether the third test data is consistent with the first test data, wherein the sending module to be tested is also configured to receive a first clock signal, and the test receiving module and / or the test data detection module are also configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

[0068] At least one embodiment of the present disclosure also provides a receiving circuit, which includes: a test data generating module, a receiving module to be tested and a test data detection module, wherein the test data generating module is configured to generate first test data; the receiving module to be tested is configured to generate second test data based on the first test data, and output it to the test data detection module; the test data detection module is configured to receive the second test data, and detect whether the second test data is consistent with the first test data, wherein the test data generating module is also configured to receive a first clock signal, and the receiving module to be tested is also configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

[0069] The transmitting circuit and receiving circuit provided by at least one embodiment of the present disclosure can respectively constitute independent test loops, and there is no long-distance routing inside the inter-die interconnection physical layer circuit to avoid mutual interference affecting circuit performance. In addition, according to at least one embodiment of the present disclosure, performance testing, screening and grading of the inter-die interconnection physical layer circuit can be achieved during the wafer testing stage. This design significantly improves the accuracy and efficiency of the test, and enhances the reliability and performance of the final product.

[0070] Furthermore, through the constructed test loop, the impact of packaging on performance can also be simulated, so that the packaging position of the die where the receiving circuit is located can be predicted, effectively saving production costs and improving chip yield.

[0071] Figure 2A A schematic block diagram of a sending circuit provided in at least one embodiment of the present disclosure.

[0072] For example, Figure 2A As shown, the sending circuit 200 provided by at least one embodiment of the present disclosure includes a test data generating module 201 , a sending module to be tested 202 , a test receiving module 203 and a test data detecting module 204 .

[0073] For example, the test data generation module 201 is configured to generate first test data. For example, the test data generation module 201 can be set in the digital domain, that is, it processes discrete, non-continuous digital signals. For example, the test data generation module 201 can generate a low-rate test code stream, such as PRBS7, PRBS15, PRBS31, etc. or a fixed cyclic code pattern, and the bit width of the code stream is the same as the transmission data source, and the transmission data source provides the first transmission data for data transmission during the normal use phase. The output data timing of the test data generation module 201 meets the input requirements of the transmission module 202 to be tested. For example, the test data generation module 201 can be implemented by a combinational circuit.

[0074] For example, the test sending module 202 is configured to generate second test data based on the first test data and output the second test data to the test receiving module 203. Figure 1B The sending module in can convert the input low-speed parallel signal into a high-speed serial signal.

[0075] For example, the test receiving module 203 is configured to generate third test data based on the second test data, and output the third test data to the test data detection module 204. For example, the test receiving module 203 can be set in the analog domain, that is, it processes a continuous analog signal. For example, the test receiving module 203 can be implemented by an inverter.

[0076] For example, the test data detection module 204 is configured to receive the third test data and detect whether the third test data is consistent with the first test data. For example, the test data detection module 204 can output the detection result in real time, or can output the detection result after the detection is completed. For example, the test data detection module 204 can be set in the digital domain or the analog domain. For example, the test data detection module 204 can be implemented by a combinational circuit.

[0077] For example, the transmission module to be tested is further configured to receive a first clock signal, the test receiving module and / or the test data detection module is further configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable. For example, the performance test of the transmission circuit can be achieved by adjusting the phase difference between the first clock signal and the second clock signal.

[0078] In the transmitting circuit provided in at least one embodiment of the present disclosure, the first test data is multi-bit data of the first rate, the second test data is one-bit data of the second rate, and the third test data is one-bit data of the second rate or multi-bit parallel data of the first rate, and the second rate is higher than the first rate.

[0079] For example, the first rate data may be low rate data, and the second rate data may be high rate data.

[0080] For example, the test data generation module may be configured to output multiple bits of low-speed data.

[0081] For example, the test receiving module can be configured to receive one bit of high-speed data and output one bit of high-speed data; it can also be configured to receive one bit of high-speed data and output one bit of high-speed data or multiple bits of parallel low-speed data. For example, the test receiving module can receive high-speed CML (Current Mode Logic) or CMOS (Complementary Metal-Oxide-Semiconductor) data and output high-speed CMOS data. The test receiving module can also receive high-speed CMOS or CML data and output one bit of high-speed or multiple bits of parallel low-speed data. The embodiments of the present disclosure are not limited to this.

[0082] The transmitting circuit provided in at least one embodiment of the present disclosure is additionally provided with a test data generating module, a test receiving module and a test data detecting module. The three additional modules have a single function and are easy to implement technically. Moreover, the area occupied by the three additional modules in the physical layout can be very small, for example, only less than 3% of the area required for the transmitting module to be tested, so that there is almost no impact on the production cost. Since these modules are easy to implement and occupy a small space, the impact on the cost and layout design of the entire project can be ignored, and the reliability and functionality of the product can be improved without significantly increasing the cost.

[0083] It should be noted that in the transmitting circuit provided in the embodiment of the present disclosure, a serial-to-parallel module or other functional modules may be added between the test receiving module and the test data detection module, and the embodiment of the present disclosure does not limit this.

[0084] For example, the transmitting circuit provided in at least one embodiment of the present disclosure further includes an input selection module configured to receive first test data for testing and first transmission data for data transmission, and output the selected data to the transmitting module to be tested.

[0085] For example, in the test phase, the input selection module selects the first test data for testing and outputs it to the transmission module to be tested; in the normal use phase, the input selection module selects the first transmission data for data transmission and outputs it to the transmission module to be tested. For example, the first transmission data is data from the transmission data source, and is used for data transmission when the transmission circuit is in normal use. For example, the input selection module can be implemented by a combinational circuit.

[0086] For example, in the transmitting circuit provided in at least one embodiment of the present disclosure, the transmitting module to be tested is further configured to generate second transmitting data based on the first transmitting data, and output the second transmitting data to the transmitting port of the transmitting circuit.

[0087] For example, in the normal use phase, the sending module to be tested can generate second sending data based on the first sending data from the sending data source, and output it to the sending port of the sending circuit, thereby sending it to the receiving port of the receiving circuit at the opposite end.

[0088] For example, in the transmitting circuit provided in at least one embodiment of the present disclosure, the input reference voltage of the test receiving module is adjustable.

[0089] For example, the input reference voltage of the test receiving module refers to the reference voltage (threshold voltage) used by the test receiving module to receive data. The test receiving module can be implemented by a customized inverter with adjustable threshold voltage. For example, performance testing can be implemented by adjusting the input reference voltage of the test receiving module based on adjusting the phase difference between the first clock signal and the second clock signal.

[0090] It should be noted that the test receiving module provided in the embodiment of the present disclosure may not support input reference voltage adjustment, and the embodiment of the present disclosure does not limit this.

[0091] For example, in the transmitting circuit provided in at least one embodiment of the present disclosure, the transmitting module to be tested includes a buffer, a parallel-to-serial circuit and a driving circuit, and the buffer, the parallel-to-serial circuit and the driving circuit are connected in sequence.

[0092] For example, the buffer may be a FIFO (First Input First Output) memory, such as a FIFO dual-port buffer, where the first data that enters will also be the first data that is removed, and dual-port means that the memory has an input port and an output port.

[0093] For example, the main function of the parallel-to-serial circuit is to convert parallel data into serial data. The parallel-to-serial circuit outputs data bit by bit in a certain order through a clock synchronization mechanism, which can reduce the number of physical connections, thereby reducing complexity and cost.

[0094] For example, the main function of the driver circuit is to enhance the signal strength so that the signal can be transmitted over a longer distance without distortion. In the transmitting module, the driver circuit is usually located at the end of the signal transmission path and is responsible for converting the serial data output by the parallel-to-serial circuit into a signal format suitable for transmission. The driver circuit also needs to be able to provide sufficient current and voltage to overcome the loss on the transmission line. In addition, the driver circuit may also include the function of matching impedance to reduce signal reflection and improve signal integrity.

[0095] It should be noted that the sending module to be tested may also include more modules with other functions, or the above modules may be combined into one to have fewer modules, which is not limited in the embodiments of the present disclosure.

[0096] For example, the buffer is configured to receive the third clock signal as the write clock, and the test data generation module is configured to receive the third clock signal. In order to ensure that the output data timing of the test data generation module meets the input requirements of the test sending module, the clock of the test data generation module can be set to be consistent with the write clock of the buffer.

[0097] It should be noted that the clock of the test data generation module may also be inconsistent with the write clock of the buffer, as long as the output data timing of the test data generation module can meet the input requirements of the test sending module. The embodiments of the present disclosure do not limit this.

[0098] For example, in the transmitting circuit provided by at least one embodiment of the present disclosure, the parallel-to-serial circuit is configured to receive a first clock signal, and the buffer is configured to receive a fourth clock signal obtained by dividing the first clock signal as a read clock. For example, the frequency of the first clock signal can be reduced to a suitable level using a frequency divider to meet the operational requirements of the buffer. In this way, the buffer can read data according to the clock cycle of the fourth clock signal to achieve accurate reading and synchronization of the data.

[0099] The transmitting circuit provided by at least one embodiment of the present disclosure forms an independent test loop by adding modules such as a test data generation module, a test receiving module, and a test data detection module. There is no long-distance routing inside the inter-die interconnection physical layer circuit to avoid mutual interference affecting circuit performance. In addition, the performance testing, screening, and grading of the inter-die interconnection physical layer circuit can be realized during the wafer testing stage. This design significantly improves the accuracy and efficiency of the test, and enhances the reliability and performance of the final product.

[0100] Figure 2B A schematic diagram of a sending circuit provided by at least one embodiment of the present disclosure.

[0101] Figure 2B is an example of the transmitting circuit provided in the above embodiment. Figure 2B As shown, the transmitting circuit provided by at least one embodiment of the present disclosure includes a test data generating module, an input selecting module, a transmitting module to be tested, a test receiving module and a test data detecting module. The test path is: test data generating module→input selecting module→transmitting module to be tested→test receiving module→test data detecting module.

[0102] For example, Figure 2B As shown, the test data generation module generates the first test data and outputs it to the input selection module; the input selection module receives the first test data for testing and the first sending data for data transmission (provided by the data sending source), and outputs them to the sending module to be tested after selection.

[0103] During the testing phase, the input selection module outputs the first test data to the sending module to be tested, the sending module to be tested generates the second test data based on the first test data, and outputs it to the test receiving module; the test receiving module generates the third test data based on the second test data, and outputs it to the test data detection module; the test data detection module receives the third test data, and detects whether the third test data is consistent with the first test data generated by the test data generation module.

[0104] In the normal use phase, the input selection module outputs the first transmission data to the transmission module to be tested, and the transmission module to be tested generates the second transmission data based on the first transmission data and outputs it to the transmission port (PAD1) of the transmission circuit.

[0105] It should be noted that Figure 2B This is just an example of a sending circuit. Figure 2B The test loop connection point N1 shown may be on the connection line between the sending module to be tested and the sending port, or on the sending port, or connected to the main path in other ways, which is not limited in the embodiment of the present disclosure.

[0106] For example, Figure 2B As shown, the sending module to be tested receives a first clock signal (CLK1), and the test data detection module receives a second clock signal (CLK2). The phases of the first clock signal and the second clock signal are adjustable, so that performance testing can be performed during the test phase by adjusting the clock phase difference between the sending module to be tested and the test data detection module.

[0107] It should be noted that the test receiving module can also receive the second clock signal, so that during the test phase, performance testing can also be performed by adjusting the clock phase difference between the test sending module and the test receiving module, and the embodiments of the present disclosure do not limit this.

[0108] For example, Figure 2B As shown, the transmission module to be tested includes a buffer, a parallel-to-serial circuit and a driving circuit. For example, the parallel-to-serial circuit receives a first clock signal, and the above "adjusting the clock phase difference between the transmission module to be tested and the test data detection module" can be specifically expressed as adjusting the clock phase difference between the parallel-to-serial circuit and the test data detection module. For example, the buffer receives a fourth clock signal (CLK4) obtained by dividing the first clock signal as a read clock, and receives a third clock signal (CLK3) as a write clock. The test data generation module also receives the third clock signal, so that the clock of the test data generation module is set to be consistent with the write clock of the buffer.

[0109] It should be noted that Figure 2BThis is just an example of a sending circuit. The test data generating module may not receive the third clock signal, as long as the output data timing of the test data generating module meets the input requirement of the sending module to be tested.

[0110] Figure 3A A schematic block diagram of a receiving circuit provided for at least one embodiment of the present disclosure.

[0111] For example, Figure 3A As shown, the receiving circuit 300 provided by at least one embodiment of the present disclosure includes a test data generating module 301 , a receiving module to be tested 302 , and a test data detecting module 303 .

[0112] For example, the test data generation module 301 is configured to generate first test data. For example, the test data generation module 301 can be set in the digital domain, that is, it processes discrete, non-continuous digital signals; it can also be set in the analog domain, that is, it processes continuous analog signals. For example, the test data generation module 301 can generate a high-rate test code stream, such as PRBS7, PRBS15, PRBS31, etc. or a fixed cyclic code pattern, and the bit width of the code stream is one bit. For example, the test data generation module 301 can be implemented by a combinational circuit.

[0113] For example, the receiving module to be tested 302 is configured to generate second test data based on the first test data and output the second test data to the test data detection module 303. For example, the receiving module to be tested 302 may be Figure 1B The receiving module in can convert the received high-speed serial signal into a low-speed parallel signal.

[0114] For example, the test data detection module 303 is configured to receive the second test data and detect whether the second test data is consistent with the first test data. For example, the test data detection module 303 can output the detection result in real time, or can output the detection result after the detection is completed. For example, the test data detection module 303 can be set in the digital domain. For example, the test data detection module 303 can be implemented by a combinational circuit.

[0115] For example, the test data generation module is further configured to receive a first clock signal, and the receiving module to be tested is further configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable. For example, the performance test can be implemented by adjusting the phase difference between the first clock signal and the second clock signal.

[0116] In the receiving circuit provided in at least one embodiment of the present disclosure, the first test data is one bit of second rate data or multiple bits of first rate data, the second test data is multiple bits of first rate data, and the second rate is higher than the first rate.

[0117] For example, the first rate data may be low-speed data, and the second rate data may be high-speed data. For example, the test data generation module may be configured to output one bit of high-speed data or multiple bits of low-speed data, and the test data detection module may be configured to receive multiple bits of low-speed data.

[0118] The receiving circuit provided in at least one embodiment of the present disclosure is additionally provided with a test data generation module and a test data detection module. The two additional modules have a single function and are easy to implement technically. Moreover, the area occupied by the two additional modules in the physical layout can be very small, so there is almost no impact on the production cost. Since these modules are easy to implement and occupy a small space, the impact on the cost and layout design of the entire project can be ignored, and the reliability and functionality of the product can be improved without significantly increasing the cost.

[0119] In the receiving circuit provided in at least one embodiment of the present disclosure, the input reference voltage of the receiving module to be tested is adjustable.

[0120] For example, the input reference voltage of the receiving module to be tested refers to the reference voltage (threshold voltage) used by the receiving module to be tested to receive data. For example, the performance test can be implemented by adjusting the input reference voltage of the receiving module to be tested based on adjusting the phase difference between the first clock signal and the second clock signal.

[0121] The receiving circuit provided in at least one embodiment of the present disclosure further includes a test driving circuit, wherein the test driving circuit is configured to provide an adjustable driving capability for the first test data.

[0122] For example, the test drive circuit can adjust the amplitude and strength of its output signal as needed to provide different test conditions. By adjusting the driving capability of the test drive circuit, the signal quality received by the receiving port of the packaged receiving circuit can be simulated. For example, the test drive circuit can be implemented by a resistor array, which has a simple circuit implementation and a small occupied area, and its driving capability can be adjusted by adjusting the size of the resistor. For example, the test drive circuit can be set between the test data generation module and the receiving module to be tested.

[0123] The receiving circuit provided in at least one embodiment of the present disclosure further includes a test data processing module, which is configured to convert the rate of the first test data from a first rate to a higher-speed second rate.

[0124] For example, the test data processing module can convert low-speed data into high-speed data. When the first test data generated by the test data generation module is low-speed data, a test data processing module can be set between the test data generation module and the receiving module to be tested to convert the first test data output by the test data generation module from low-speed data to high-speed data and output it to the receiving module to be tested. In some examples, the test data processing module can also be configured to receive a first clock signal.

[0125] For example, the test drive circuit and the test data processing module can also form a test sending module, which is arranged between the test data generating module and the receiving module to be tested. In the test sending module, the test data processing module and the test drive circuit are connected in sequence.

[0126] In the receiving circuit provided in at least one embodiment of the present disclosure, the receiving module to be tested includes an analog front end, a sampling circuit and a serial-to-parallel circuit, and the analog front end, the sampling circuit and the serial-to-parallel circuit are connected in sequence.

[0127] For example, the analog front end is composed of multiple functional modules and has adjustable capabilities, which can achieve adjustment of power consumption, equalization capability, bandwidth, etc. For example, by adjusting the receiving capability of the analog front end, the performance fluctuation of the receiving circuit after packaging can be simulated. The sampling circuit can be configured to convert a continuous analog signal into a discrete digital signal; the serial-to-parallel circuit can be configured to convert serial data into parallel data.

[0128] For example, the sampling circuit and / or the serial-to-parallel circuit are configured to receive the second clock signal. In the receiving circuit, the second clock signal can be used to synchronize the sampling circuit and the serial-to-parallel circuit to achieve accurate sampling and conversion of data.

[0129] For example, the input reference voltage of the analog front end is adjustable. The performance test can be implemented by adjusting the phase difference between the first clock signal and the second clock signal through the input reference voltage of the analog front end.

[0130] It should be noted that the sending module to be tested may also include more modules with other functions, or the above modules may be combined into one to have fewer modules, for example, a buffer or a decision feedback equalizer (Decision Feedback Equalizer, DFE) may be added, etc., and the embodiments of the present disclosure are not limited to this.

[0131] In the receiving circuit provided in at least one embodiment of the present disclosure, the test data detection module is configured to receive a third clock signal obtained by dividing the second clock signal. For example, the frequency of the second clock signal can be reduced to a suitable level by using a frequency divider to meet the working requirements of the test data detection module, thereby improving the accuracy and synchronization of data detection. It should be noted that the test data detection module can also receive other clock signals, which is not limited by the embodiment of the present disclosure.

[0132] The receiving circuit provided by at least one embodiment of the present disclosure forms an independent test loop by adding modules such as a test data generation module and a test data detection module, and there is no long-distance routing inside the inter-die interconnection physical layer circuit to avoid mutual interference affecting circuit performance. In addition, the performance test, screening and grading of the inter-die interconnection physical layer circuit can be realized during the wafer testing stage. This design significantly improves the accuracy and efficiency of the test, and enhances the reliability and performance of the final product.

[0133] Figure 3B A schematic diagram of a receiving circuit provided according to at least one embodiment of the present disclosure.

[0134] Figure 3B is an example of the receiving circuit provided in the above embodiment. Figure 3B As shown, at least one embodiment of the present disclosure provides a receiving circuit including a test data generation module, a test sending module, a receiving module to be tested and a test data detection module. The test path is: test data generation module→test sending module→receiving module to be tested→test data detection module.

[0135] For example, Figure 3B As shown, in the test phase, the test data generation module generates the first test data and outputs it to the test sending module; the test sending module includes a test data processing module and a test driving circuit, the test data processing module converts the rate of the first test data from the first rate to a higher speed second rate, and the test driving circuit provides an adjustable driving capability for the first test data. The receiving module to be tested generates the second test data based on the first test data and outputs it to the test data detection module; the test data detection module receives the second test data and detects whether the second test data is consistent with the first test data generated by the test data generation module.

[0136] In the normal use phase, the receiving module to be tested generates second receiving data based on the first receiving data from the receiving port (PAD2), and outputs the second receiving data to the subsequent module.

[0137] For example, Figure 3BAs shown, the test data generating module receives a first clock signal (CLK1), and the receiving module to be tested receives a second clock signal (CLK2). The phases of the first clock signal and the second clock signal are adjustable, so that during the test phase, the performance test of the receiving circuit can be performed by adjusting the clock phase difference between the test data generating module and the receiving module to be tested.

[0138] It should be noted that the test data processing module in the test sending module can also receive the first clock signal, so that during the test phase, the performance test of the receiving circuit can be performed by adjusting the clock phase difference between the test data processing module and the receiving module to be tested. The embodiments of the present disclosure do not limit this.

[0139] For example, Figure 3B As shown, the receiving module to be tested includes an analog front end, a sampling circuit and a serial-to-parallel circuit. For example, the sampling circuit and / or the serial-to-parallel circuit receive the second clock signal, and the above "adjusting the clock phase difference between the test data generation module and the receiving module to be tested" can be specifically expressed as adjusting the clock phase difference between the test data generation module and the sampling circuit and / or the serial-to-parallel circuit. For example, the test data detection module receives a third clock signal (CLK3) obtained by dividing the second clock signal.

[0140] It should be noted that Figure 3B This is only an example of a receiving circuit. The test data detection module may not receive the third clock signal, and the embodiment of the present disclosure does not limit this.

[0141] Furthermore, it should be noted that Figure 3B The test loop connection point N2 shown can be on the connection line between the receiving module to be tested and the receiving port, or on the receiving port, or connected to the main path by other means, and the embodiment of the present disclosure does not limit this. For example, the analog front end supports multi-channel input selection, and the first test data can be input from one of the channels instead of being input through the receiving port or the receiving port connection.

[0142] Figure 4 A schematic diagram of a physical layer circuit for interconnecting dies provided for at least one embodiment of the present disclosure.

[0143] For example, Figure 4 As shown, the inter-die interconnection physical layer circuit provided by at least one embodiment of the present disclosure includes the transmitting circuit provided by at least one embodiment and the receiving circuit provided by at least one embodiment. The specific description of the transmitting circuit and the receiving circuit can refer to the contents of the above embodiments, which will not be repeated here.

[0144] The inter-die interconnection physical layer circuit provided by at least one embodiment of the present disclosure adds test loops in the unidirectional transmission transmission circuit and the receiving circuit respectively, and there is no long-distance routing inside the inter-die interconnection physical layer circuit to avoid mutual interference affecting circuit performance. In addition, the performance testing, screening and grading of the inter-die interconnection physical layer circuit can be realized during the wafer testing stage. This design significantly improves the accuracy and efficiency of the test, and enhances the reliability and performance of the final product.

[0145] Figure 5 A schematic block diagram of an integrated circuit chip provided for at least one embodiment of the present disclosure.

[0146] For example, Figure 5 As shown, the integrated circuit chip provided by at least one embodiment of the present disclosure includes a transmitting circuit 501 and / or a receiving circuit 502. The transmitting circuit 501 may be, for example, the transmitting circuit provided by at least one embodiment above, for example Figure 2A The receiving circuit 502 may be, for example, the receiving circuit provided by at least one of the above embodiments, for example Figure 3A The receiving circuit 300 in FIG.

[0147] In the integrated circuit chip provided in at least one embodiment of the present disclosure, the integrated circuit chip includes a plurality of dies interconnected and communicating with each other, and at least one of the plurality of dies includes a transmitting circuit and / or a receiving circuit.

[0148] For example, an integrated circuit chip is composed of multiple tube cores, and these tube cores communicate through an interconnection structure. A tube core refers to a functional circuit area on a single silicon wafer, which is usually integrated together through packaging technology to form a complete chip. At least one tube core includes a transmitting circuit and / or a receiving circuit provided by at least one of the above embodiments. In this way, the performance testing, screening and grading of the transmitting circuit and / or the receiving circuit can be realized during the wafer testing stage, thereby improving the overall performance and reliability of the system. In addition, the packaging position of the tube core can also be evaluated, effectively saving production costs.

[0149] Fig. 6A A flowchart of a method for testing a sending circuit provided in at least one embodiment of the present disclosure.

[0150] like Fig. 6A As shown, the testing method of the transmitting circuit provided by at least one embodiment of the present disclosure is applicable to testing the transmitting circuit provided by at least one embodiment above, and includes the following steps S610 to S630.

[0151] Step S610: Adjust the phase difference between the first clock signal and the second clock signal.

[0152] Step S620: For each phase difference value, record the test result output by the test data detection module to obtain a one-dimensional eye diagram.

[0153] Step S630: Perform a performance test on the transmitting circuit according to the eye width of the one-dimensional eye diagram.

[0154] For example, in step S610, the phase difference between the first clock signal and the second clock signal is adjusted so that the phase difference gradually expands from 0 to 1 unit time interval (UI) or more. The unit time interval is a standard unit for measuring clock cycles. At a given data transmission rate, the unit time interval can be defined as the time required to transmit one bit.

[0155] For example, in step S620, at each phase difference value, the test data detection module detects whether the received data is consistent with the data sent by the test data generation module, and records the test results output by the test data detection module, thereby obtaining a one-dimensional eye diagram. A one-dimensional eye diagram is a graphical representation used to display the signal transmission quality at different phase difference values. A one-dimensional eye diagram can be formed by plotting the test results at all phase difference values ​​together. The eye diagram can intuitively display the transmission quality of the signal, including the jitter, noise and other interference factors of the signal, and can be applied to occasions where serial digital signals or high-speed digital signals in devices and chips need to be tested and verified.

[0156] For example, in step S630, the eye width refers to the maximum opening and closing width of the signal in the horizontal direction in the eye diagram. An eye width threshold can be preset, and when the eye width of the one-dimensional eye diagram is greater than the eye width threshold, it indicates that the performance of the transmitting circuit meets the standard.

[0157] Figure 6B A flowchart of a method for testing a sending circuit provided in at least one embodiment of the present disclosure.

[0158] like Figure 6B As shown, the testing method of the transmitting circuit provided by at least one embodiment of the present disclosure is applicable to testing the transmitting circuit provided by at least one embodiment above, and includes the following steps S640 to S660.

[0159] Step S640: Adjust the phase difference between the first clock signal and the second clock signal.

[0160] Step S650: for each phase difference value, adjust the input reference voltage of the test receiving module, and for each input reference voltage, record the test result output by the test data detection module to obtain a two-dimensional eye diagram.

[0161] Step S660: Perform a performance test on the transmitting circuit according to the eye width and eye height of the two-dimensional eye diagram.

[0162] For example, in step S640, the phase difference between the first clock signal and the second clock signal is adjusted so that the phase difference gradually expands from 0 to 1 unit time interval or more.

[0163] For example, in step S650, the input reference voltage of the test receiving module is adjusted for each phase difference value, and under each different combination of the phase difference value and the input reference voltage, the test data detection module detects whether the received data is consistent with the data sent by the test data generation module, and records the test result output by the test data detection module, thereby obtaining a two-dimensional eye diagram. For example, the horizontal axis of the two-dimensional eye diagram is the phase, and the vertical axis is the voltage.

[0164] For example, in step S660, the eye width refers to the maximum opening and closing width of the signal in the horizontal direction in the two-dimensional eye diagram, and the eye width can be calculated by measuring the time difference between the crossing points of the upper and lower edges of the eye diagram; the eye height refers to the maximum opening and closing height of the signal in the vertical direction in the two-dimensional eye diagram. The eye height can be calculated by measuring the amplitude difference between the crossing points of the left and right boundaries of the eye diagram. An eye width threshold and an eye height threshold can be preset. When the eye width of the two-dimensional eye diagram is greater than the eye width threshold and the eye height is greater than the eye height threshold, it means that the performance of the transmitting circuit meets the standard.

[0165] The test method of the transmitting circuit provided by the above embodiment of the present disclosure can be performed in the wafer test stage to verify that the internal functions of the transmitting circuit are correct and the performance meets the requirements. In some examples, it can also be performed during the debugging process to assist in locating the problem.

[0166] In some examples, the method for testing a transmitting circuit provided by at least one embodiment of the present disclosure further includes the following steps S61 to S62.

[0167] Step S61: adjusting the driving capability of the driving circuit in the transmitting module to be tested to simulate the channel performance after packaging.

[0168] Step S62: Determine the packaging position of the transmitting circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram.

[0169] For example, in step S61, the driving capability can be adjusted by adjusting the resistance of the driving circuit. The smaller the resistance, the stronger the driving capability; the larger the resistance, the weaker the driving capability. By adjusting the driving capability, the quality of the signal sent to the other end through the channel after packaging can be simulated. For example, weakening the driving capability can simulate the quality of the signal sent to the other end through the channel becoming worse.

[0170] For example, in step S62, if the eye diagram test result still does not meet the standard when the driving capability is adjusted to the strongest, it means that in the package, a position with good channel performance or a position with good peer performance should be selected for the die where the transmitting circuit is located, so as to improve the chip yield.

[0171] In some examples, the method for testing a transmitting circuit provided by at least one embodiment of the present disclosure further includes the following steps S63 to S64.

[0172] Step S63: adjusting the receiving capability of the test receiving module to simulate the performance of the receiving circuit connected to the transmitting circuit after packaging.

[0173] Step S64: Determine the packaging position of the transmitting circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram.

[0174] For example, in step S63, the receiving capability of the test receiving module can be adjusted by adjusting the resistance connected in series in the signal path in the test receiving module. The smaller the resistance, the larger the bandwidth and the stronger the receiving capability; the larger the resistance, the smaller the bandwidth and the weaker the receiving capability. By adjusting the receiving capability of the test receiving module, the performance of the receiving circuit of the opposite end can be simulated. For example, by weakening the receiving capability of the test receiving module, the performance of the receiving circuit of the opposite end can be simulated to be relatively weak.

[0175] For example, in step S64, if the receiving capability of the test receiving module is adjusted to be relatively weak, the eye diagram test result can meet the standard, indicating that the sending capability of the sending circuit on this end is relatively strong. Therefore, in the package, the die where the sending circuit is located can be placed in a position where the channel performance is relatively weak, or a position where the opposite end performance is relatively weak, thereby saving production costs.

[0176] By using the testing method of the transmitting circuit provided in the above embodiment of the present disclosure, the influence of packaging on performance can be simulated, so that the packaging position of the tube core where the transmitting circuit is located can be predicted, effectively saving production costs and improving chip yield.

[0177] Fig. 7A A flowchart of a method for testing a receiving circuit provided in at least one embodiment of the present disclosure.

[0178] like Fig. 7A As shown, the method for testing a receiving circuit provided by at least one embodiment of the present disclosure is suitable for testing the receiving circuit provided by at least one embodiment above, and includes the following steps S710 to S730.

[0179] Step S710: Adjust the phase difference between the first clock signal and the second clock signal.

[0180] Step S720: For each phase difference value, record the test result output by the test data detection module to obtain a one-dimensional eye diagram.

[0181] Step S730: Performing a performance test on the receiving circuit according to the eye width of the one-dimensional eye diagram.

[0182] For example, in step S710, the phase difference between the first clock signal and the second clock signal is adjusted so that the phase difference gradually extends from 0 to 1 unit time interval (Unit Interval, UI) or more.

[0183] For example, in step S720, at each phase difference value, the test data detection module detects whether the received data is consistent with the data sent by the test data generation module, and records the test result output by the test data detection module, thereby obtaining a one-dimensional eye diagram.

[0184] For example, in step S730, an eye width threshold may be preset, and when the eye width of the one-dimensional eye diagram is greater than the eye width threshold, it indicates that the performance of the receiving circuit meets the standard.

[0185] Figure 7B A flowchart of a method for testing a receiving circuit provided in at least one embodiment of the present disclosure.

[0186] like Figure 7B As shown, the testing method of the receiving circuit provided by at least one embodiment of the present disclosure is suitable for testing the receiving circuit provided by at least one embodiment above, and includes the following steps S740 to S760.

[0187] Step S740: Adjust the phase difference between the first clock signal and the second clock signal.

[0188] Step S750: for each phase difference value, adjusting the input reference voltage of the receiving module to be tested, and for each input reference voltage, recording the test result output by the test data detection module to obtain a two-dimensional eye diagram.

[0189] Step S760: Perform a performance test on the receiving circuit according to the eye width and eye height of the two-dimensional eye diagram.

[0190] For example, in step S740, the phase difference between the first clock signal and the second clock signal is adjusted so that the phase difference gradually extends from 0 to 1 unit time interval or more.

[0191] For example, in step S750, the input reference voltage of the receiving module to be tested is adjusted for each phase difference value. Under each different combination of phase difference value and input reference voltage, the test data detection module will detect whether the received data is consistent with the data sent by the test data generation module, and record the test results output by the test data detection module to obtain a two-dimensional eye diagram.

[0192] For example, in step S760, an eye width threshold and an eye height threshold may be preset. When the eye width of the two-dimensional eye diagram is greater than the eye width threshold and the eye height is greater than the eye height threshold, it indicates that the performance of the receiving circuit meets the standard.

[0193] The test method for the receiving circuit provided in the above embodiments of the present disclosure can be performed in the wafer test stage to verify that the internal functions of the receiving circuit are correct and the performance meets the requirements. In some examples, it can also be performed during the debugging process to assist in locating the problem.

[0194] In some examples, the receiving circuit testing method provided by at least one embodiment of the present disclosure further includes the following steps S71 to S72.

[0195] Step S71: adjusting the driving capability of the test driving circuit in the receiving circuit to simulate the signal quality received by the receiving port of the packaged receiving circuit.

[0196] Step S72: Determine the packaging position of the receiving circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram.

[0197] For example, in step S71, the driving capability can be adjusted by adjusting the resistance of the test driving circuit. The smaller the resistance, the stronger the driving capability; the larger the resistance, the weaker the driving capability. By adjusting the driving capability, the quality of the signal received by the receiving port of the receiving circuit after packaging can be simulated. For example, weakening the driving capability can simulate the deterioration of the quality of the signal received by the receiving port.

[0198] For example, in step S72, if the eye diagram test result still does not meet the standard when the driving capability is adjusted to the strongest, it means that in the package, a position with good channel performance or a position with good peer performance should be selected for the tube core where the receiving circuit is located, so as to improve the chip yield.

[0199] In some examples, the method for testing a receiving circuit provided by at least one embodiment of the present disclosure further includes the following steps S73 to S74.

[0200] Step S73: adjusting the receiving capability of the analog front end in the receiving module to be tested to simulate the performance fluctuation of the receiving circuit after packaging.

[0201] Step S74: Determine the packaging position of the receiving circuit according to the one-dimensional eye diagram or the two-dimensional eye diagram.

[0202] For example, in step S73, the analog front end is composed of multiple functional modules and has adjustable capabilities, which can adjust power consumption, balancing capabilities, bandwidth, etc. By adjusting the receiving capability of the analog front end, the performance fluctuation of the receiving circuit after packaging can be simulated.

[0203] For example, in step S74, if the eye diagram test result meets the standard when the performance fluctuation is relatively large, it means that the receiving capability of the receiving circuit at this end is relatively strong. Therefore, in the package, the tube core where the receiving circuit is located can be placed in a position where the channel performance is relatively weak, or a position where the opposite end performance is relatively weak, saving production costs.

[0204] By using the test method for the receiving circuit provided in the above embodiment of the present disclosure, the influence of packaging on performance can be simulated, so that the packaging position of the tube core where the receiving circuit is located can be predicted, effectively saving production costs and improving chip yield.

[0205] Fig. 8A A schematic diagram of a one-dimensional eye diagram recording table provided for at least one embodiment of the present disclosure; Figure 8B A schematic diagram of a two-dimensional eye diagram recording table provided for at least one embodiment of the present disclosure.

[0206] For example, the test results output by the test data detection module are recorded in the record table, and 1 is filled in if the data is received correctly, and 0 is filled in if the data is received incorrectly. There should be only two consecutive eye diagrams in both the one-dimensional eye diagram and the two-dimensional eye diagram. For example, the eye width of the one-dimensional eye diagram and the two-dimensional eye diagram can be calculated according to the following formula (1) or formula (2):

[0207]

[0208]

[0209] Among them, EyeWidth represents the eye width, X represents the maximum number of consecutive 1s along the horizontal axis in the eye diagram, N represents the number of samples corresponding to one unit time interval, and T UI Represents the time width of a unit time interval. The unit of the result calculated by formula (1) above is unit time interval (UI), and the unit of the result calculated by formula (2) is second (s).

[0210] In the performance test of the transmitting circuit, the eye width threshold can be set to 0.5UI, and in the performance test of the receiving circuit, the eye width threshold can be set to 0.4UI. It should be noted that the above eye width threshold is only an example and can be set according to actual needs.

[0211] For example, the eye height of a two-dimensional eye diagram can be calculated according to the following formula (3):

[0212]

[0213] Among them, EyeHigh represents the eye height, Y represents the maximum number of consecutive 1s along the vertical axis in the eye diagram, W represents the number of input reference voltage samples, V FS Indicates full amplitude, which refers to the difference between the maximum and minimum values ​​of the signal amplitude. The unit of the result calculated by formula (3) is volt (V).

[0214] In the performance test of the transmitting circuit, the eye height threshold can be set to 0.7V FS , in the performance test of the receiving circuit, the eye height threshold can be set to 0.4V FS It should be noted that the above eye height threshold is only an example and can be set according to actual needs.

[0215] Fig. 9 A schematic diagram of a method for testing data transmission from a sending circuit to a receiving circuit provided by at least one embodiment of the present disclosure.

[0216] For example, Fig. 9 As shown, the first core particle includes a first controller and a sending circuit. The first controller includes a first test data generating module, and the sending circuit can refer to the sending circuit in the above embodiment, which is not described here. The second core particle includes a second controller and a receiving circuit, and the second controller includes a first test data detection module. The receiving circuit can refer to the receiving circuit in the above embodiment, which is not described here. Fig. 9 A test method for data transmission from a sending circuit of a first chip to a receiving circuit of a second chip is shown, and the test path is: first test data generation module→input selection module→test sending module→channel→test receiving module→first test data detection module.

[0217] In one example, a method for testing data transmission from a sending circuit to a receiving circuit provided by at least one embodiment of the present disclosure includes the following steps S910 to S930.

[0218] S910: Adjust the delay of the clock channel (Lane) and the data channel (Lane) so that the relative sampling phase difference value of the receiving module to be tested gradually extends from 0 to 1 unit time interval or more.

[0219] S920: For each phase difference value, record the test result output by the first test data detection module to obtain a one-dimensional eye diagram.

[0220] S930: Perform performance test based on the eye width of the one-dimensional eye diagram.

[0221] For example, the calculation method of the eye width of the one-dimensional eye diagram can refer to the above embodiment, which will not be described in detail here. An eye width threshold can be preset. When the eye width of the one-dimensional eye diagram is greater than the eye width threshold, it means that the performance of data transmission from the sending circuit to the receiving circuit meets the standard. The eye width threshold can be, for example, 0.3UI. It should be noted that the above eye width threshold is only an example and can be set according to actual needs.

[0222] In another example, a method for testing data transmission from a sending circuit to a receiving circuit provided by at least one embodiment of the present disclosure includes the following steps S940 to S960.

[0223] S940: Adjust the delay of the clock channel and the data channel so that the relative sampling phase difference value of the receiving module to be tested gradually extends from 0 to 1 unit time interval or more.

[0224] S950: For each phase difference value, adjust the input reference voltage of the receiving module to be tested, and for each input reference voltage, record the test result output by the test data detection module to obtain a two-dimensional eye diagram.

[0225] S960: Perform performance test based on the eye width and eye height of the 2D eye diagram.

[0226] For example, the calculation method of the eye width and eye height of the two-dimensional eye diagram can refer to the above embodiment, which will not be described in detail here. An eye width threshold and an eye height threshold can be preset. When the eye width of the two-dimensional eye diagram is greater than the eye width threshold and the eye height is greater than the eye height threshold, it means that the performance of the receiving circuit meets the standard. The eye width threshold can be, for example, 0.3UI, and the eye height threshold can be, for example, 0.3V FS It should be noted that the above eye width threshold and eye height threshold are only examples and can be set according to actual needs.

[0227] The test method for transmitting data from a transmitting circuit to a receiving circuit provided in at least one embodiment of the present disclosure can be performed in the wafer test stage and the final test stage to verify that the interconnection function is correct and the performance meets the requirements. In some examples, it can also be performed during the debugging process to assist in locating the problem.

[0228] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0229] There are a few points to note about this disclosure:

[0230] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0231] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0232] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0233] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A transmitting circuit, comprising: Test data generation module, test sending module, test receiving module, test data detection module, wherein: The test data generation module is configured to generate first test data; The to-be-tested sending module is configured to generate second test data based on the first test data, and output the second test data to the test receiving module; The test receiving module is configured to generate third test data based on the second test data, and output the third test data to the test data detection module; The test data detection module is configured to receive the third test data and detect whether the third test data is consistent with the first test data. The test sending module is further configured to receive a first clock signal, the test receiving module and / or the test data detection module is further configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

2. The transmitting circuit according to claim 1, further comprising: The input selection module is configured to receive the first test data for testing and the first sending data for data transmission, and output them to the sending module to be tested after selection.

3. The transmitting circuit according to claim 2, wherein: The transmission module to be tested is further configured to generate second transmission data based on the first transmission data, and output the second transmission data to a transmission port of the transmission circuit.

4. The transmitting circuit according to claim 1, wherein: The input reference voltage of the test receiving module is adjustable.

5. The transmitting circuit according to claim 1, wherein: The transmission module to be tested includes a buffer, a parallel-to-serial circuit and a driving circuit, wherein the buffer, the parallel-to-serial circuit and the driving circuit are connected in sequence. The buffer is configured to receive a third clock signal as a write clock, and the test data generation module is further configured to receive the third clock signal.

6. The transmitting circuit according to claim 5, wherein: The parallel-to-serial circuit is configured to receive the first clock signal, and the buffer is configured to receive a fourth clock signal obtained by dividing the first clock signal as a read clock.

7. The transmitting circuit according to claim 1, wherein: The first test data is multi-bit data of the first rate, the second test data is one-bit data of the second rate, the third test data is one-bit data of the second rate or multi-bit parallel data of the first rate, and the second rate is higher than the first rate.

8. A receiving circuit, comprising: A test data generation module, a test receiving module and a test data detection module, wherein: The test data generation module is configured to generate first test data; The receiving module to be tested is configured to generate second test data based on the first test data, and output the second test data to the test data detection module; The test data detection module is configured to receive the second test data and detect whether the second test data is consistent with the first test data. The test data generating module is further configured to receive a first clock signal, and the receiving module to be tested is further configured to receive a second clock signal, and the phases of the first clock signal and the second clock signal are adjustable.

9. The receiving circuit according to claim 8, wherein: The input reference voltage of the receiving module to be tested is adjustable.

10. The receiving circuit according to claim 8, further comprising: The test driving circuit is configured to provide an adjustable driving capability for the first test data.

11. The receiving circuit according to claim 10, further comprising: The test data processing module is configured to convert the rate of the first test data from a first rate to a higher-speed second rate.

12. The receiving circuit according to claim 11, wherein: The test data processing module is further configured to receive the first clock signal.

13. The receiving circuit according to claim 8, wherein: The test data detection module is configured to receive a third clock signal obtained by dividing the second clock signal.

14. The receiving circuit according to claim 8, wherein: The receiving module to be tested includes an analog front end, a sampling circuit and a serial-to-parallel circuit, which are connected in sequence. The sampling circuit and / or the serial-to-parallel circuit is configured to receive the second clock signal; The input reference voltage of the analog front end is adjustable.

15. The receiving circuit according to claim 8, wherein: The first test data is one bit of data at the second rate or multiple bits of data at the first rate, the second test data is multiple bits of data at the first rate, and the second rate is higher than the first rate.

16. An integrated circuit chip, comprising: The transmitting circuit according to any one of claims 1 to 7, and / or A receiving circuit as claimed in any one of claims 8 to 15.

17. The integrated circuit chip according to claim 16, wherein: The integrated circuit chip includes a plurality of dies interconnected and communicating with each other, and at least one of the plurality of dies includes the transmitting circuit and / or the receiving circuit.

18. A method for testing a transmitting circuit according to any one of claims 1 to 7, comprising: adjusting a phase difference between the first clock signal and the second clock signal; For each phase difference value, recording the test result output by the test data detection module to obtain a one-dimensional eye diagram; A performance test is performed on the transmitting circuit according to the eye width of the one-dimensional eye diagram.

19. The testing method according to claim 18, wherein: After adjusting the phase difference between the first clock signal and the second clock signal, the method further includes: For each phase difference value, the input reference voltage of the test receiving module is adjusted, For each input reference voltage, recording the test result output by the test data detection module to obtain a two-dimensional eye diagram; A performance test is performed on the transmitting circuit according to the eye width and eye height of the two-dimensional eye diagram.

20. The testing method according to claim 18, further comprising: Adjusting the driving capability of the driving circuit in the transmitting module to be tested to simulate the channel performance after packaging; or Adjusting the receiving capability of the test receiving module to simulate the performance of the receiving circuit connected to the transmitting circuit after packaging; The packaging position of the transmitting circuit is determined according to the one-dimensional eye diagram or the two-dimensional eye diagram.

21. A method for testing a receiving circuit according to any one of claims 8 to 15, comprising: adjusting a phase difference between the first clock signal and the second clock signal; For each phase difference value, recording the test result output by the test data detection module to obtain a one-dimensional eye diagram; A performance test is performed on the receiving circuit according to the eye width of the one-dimensional eye diagram.

22. The testing method according to claim 21, wherein: After adjusting the phase difference between the first clock signal and the second clock signal, the method further includes: For each phase difference value, adjusting the input reference voltage of the receiving module to be tested, For each input reference voltage, recording the test result output by the test data detection module to obtain a two-dimensional eye diagram; A performance test is performed on the receiving circuit according to the eye width and eye height of the two-dimensional eye diagram.

23. The testing method according to claim 21, further comprising: Adjusting the driving capability of the test driving circuit in the receiving circuit to simulate the signal quality received by the receiving port of the packaged receiving circuit; or Adjusting the receiving capability of the analog front end in the receiving module to be tested to simulate the performance fluctuation of the receiving circuit after packaging; The packaging position of the receiving circuit is determined according to the one-dimensional eye diagram or the two-dimensional eye diagram.

Images