Converter modulation method, system, equipment and medium

Abstract

The invention relates to the technical field of power conversion, and particularly discloses a modulation method and system of a converter, equipment and a medium. The converter comprises at least two H bridges and a multi-winding high-frequency isolation transformer. The modulation method of the converter comprises the following steps: setting modulation parameters; on the basis of the modulation parameter, modulating the converter by using a preset modulation strategy; wherein the set modulation parameters are as follows: different duty ratios and different out-shift ratios are respectively set for the first half cycle and the second half cycle of each switching cycle during modulation of the converter, and phase-shift zero-voltage sequences with different duration proportions are respectively added when the first half cycle and the second half cycle of each switching cycle are ended; therefore, the equivalent switching frequencies of the first half period and the second half period of each switching period are reduced by different proportions. By adopting the method and the device, when modulation input parameters change, the delay of power transmission is small, the precision is high, and in addition, the method and the device are simple and easy to implement, strong in robustness, strong in practicability and high in light load efficiency.

Description

Technical Field

[0001] The present application relates to the field of power conversion technology, and in particular to a modulation method, system, device and medium of a converter. Background Art

[0002] The modulation strategy of the multiple active bridge (MAB) converter generally adopts single phase shift (SPS) modulation or extended soft switching phase shift (ESSPS) modulation.

[0003] During SPS modulation and ESSPS modulation, even if the input parameters are constant, the excitation current still has a transient bias, and the time constant is large, the transient time is long, causing the transformer bias and AC and DC currents to increase, the transient performance of the MAB converter to decrease, and the loss to increase. During SPS modulation and ESSPS modulation, the temporal overlap of the AC voltage and current of adjacent switching cycles is inevitable. Therefore, when the modulation input parameters change, especially when the external shift phase changes, an abnormal pulse voltage will be generated, resulting in uncontrollable power transfer; at the same time, due to the change in input parameters, the time integral of the square wave voltage is asymmetric, and the winding current produces a significant transient bias; the transient steady-state performance of the MAB converter is reduced, and the loss increases. Summary of the invention

[0004] Based on this, it is necessary to provide a modulation method, system, equipment and medium for a converter to address the above technical problems. When the modulation input parameters change, there is no transient winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, and the power transfer delay is small and the accuracy is high. In addition, the modulation strategy is simple and easy, does not require additional sensor signal feedback and complex control process, the modulation strategy is independent of the transformer inductance parameters, has strong robustness, strong practicality, and high light load efficiency.

[0005] In a first aspect, a modulation method of a converter is provided, wherein the converter includes at least two H-bridges, and the modulation method includes:

[0006] Set modulation parameters;

[0007] Based on the modulation parameters, modulating the converter with a preset modulation strategy;

[0008] Among them, the modulation parameters are set as follows: different duty cycles and different external shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated. At the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half cycle and the second half cycle of each switching cycle is reduced by different ratios.

[0009] In some examples, setting the modulation parameters includes:

[0010] The modulation parameters are constrained, and when the modulation parameters are constrained, the modulation parameters are calculated according to key input parameters, wherein the constraints on the modulation parameters include:

[0011] The AC voltage and current of adjacent switching cycles do not overlap in time, and the start or end time point of a half switching cycle is zero voltage;

[0012] The time integral of the half-switching cycle voltage is the same for all ports;

[0013] The independent excitation inductor current rise value in the first half cycle is equal to the difference between the expected positive peak value of the independent excitation inductor current and the expected reverse peak value of the independent excitation inductor current in the previous switching cycle;

[0014] The time during which the independent magnetizing inductor current in a switching cycle maintains the forward peak value is equal to the time during which the reverse peak value is maintained.

[0015] In some examples, the key input parameters include a frequency reduction factor, a global duty cycle factor, and an out-shift ratio;

[0016] The calculating the modulation parameter according to the key input parameter comprises:

[0017] According to the frequency reduction coefficient, the global duty cycle coefficient and the external shift comparison, the first half cycle duty cycle, the second half cycle duty cycle, the first half cycle external shift comparison, the second half cycle external shift comparison, the first half cycle frequency reduction coefficient and the second half cycle frequency reduction coefficient are obtained.

[0018] In some examples, where

[0019] The duty cycle d of the first half of the kth switching cycle j,FH,k is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the k-th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, and the DC voltage of the port with the lowest voltage in the k-th switching cycle;

[0020] The duty cycle d of the second half of the kth switching cycle j,SH,kIt is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the DC voltage of the port j in the kth switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle.

[0021] In some examples, where

[0022] The frequency reduction coefficient of the first half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle;

[0023] The frequency reduction coefficient of the second half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle;

[0024] Before calculating the frequency reduction coefficient of the first half cycle of the kth switching cycle and calculating the frequency reduction coefficient of the second half cycle of the kth switching cycle, an approximate method or a prediction method is used to obtain the DC voltage of the k+1th cycle.

[0025] In some examples, where

[0026] The first half of the kth switching cycle is shifted outward compared to D j,FH,k is obtained according to the outward shift ratio of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port j of the k-1th switching cycle, and the duty cycle of port j of the k-1th switching cycle;

[0027] The second half of the kth switching cycle is shifted outward compared to D j,SH,k It is obtained according to the outward shift ratio of the kth switching cycle and the outward shift ratio of the first half cycle of the kth switching cycle.

[0028] In some examples, the preset modulation strategy is an extended soft switching phase shift modulation strategy.

[0029] In a second aspect, a modulation system of a converter is provided, wherein the converter comprises at least two H-bridges and a multi-winding high-frequency isolation transformer, and the modulation system comprises:

[0030] A modulation parameter setting module, used to set modulation parameters;

[0031] A modulation module is used to modulate the converter according to the modulation parameters and a preset modulation strategy, wherein the modulation parameters are set as follows: different duty cycles and different shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated, and at the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequencies of the first half cycle and the second half cycle of each switching cycle are reduced by different ratios.

[0032] In a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the modulation method of the converter of the implementation method of the first aspect are implemented.

[0033] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the steps of the modulation method of the converter of the implementation mode of the first aspect are implemented.

[0034] By adopting the embodiments of the present application, when the modulation input parameters change, there is no transient winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, the power transfer delay is small and the accuracy is high. In addition, the modulation strategy is simple and easy to implement, does not require additional sensor signal feedback and complex control process, the modulation strategy is independent of the transformer inductance parameters, has strong robustness, strong practicality, and high light load efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0036] Figure 1 Schematic diagram of the topological structure of the dual active bridge converter;

[0037] Figure 2 It is a schematic diagram of the topological structure of a multi-active bridge converter;

[0038] Figure 3 This is the schematic diagram of the H-bridge high frequency voltage during GPS modulation of the MAB converter;

[0039] Figure 4 A flow chart of a modulation method for a converter provided in an embodiment of the present application;

[0040] Figure 5 Schematic diagram of the 10 time stages of the ALF-ESSPS modulation cycle;

[0041] Figure 6 Schematic diagram of the time integration of the half-switching cycle voltage at each port of the MAB converter;

[0042] Figure 7 Schematic diagram of the relationship between the independent magnetizing inductor current change and the duty cycle at port j of the MAB converter;

[0043] Figure 8 Schematic diagram of the forward time integral and reverse time integral of the independent magnetizing inductor current at port j of the MAB converter;

[0044] Fig. 9 A schematic diagram of the specific implementation of ALF-ESSPS modulation;

[0045] Fig.10 This is a schematic diagram of the functions and timing of the carrier generation and synchronization modules;

[0046] Fig.11 A schematic diagram of switching between modulation modes of a MAB converter;

[0047] Fig.12 is a flow chart of a direct modulation parameter calculation module;

[0048] Fig.13 This is a schematic diagram of the gate signal generation module function and timing;

[0049] Fig.14 Schematic diagram of the switch function output for different zero voltage mode selection signals MZ;

[0050] Fig.15 It is a schematic diagram of DAB converter-ALF-ESSPS modulation-mutation a-time domain waveform;

[0051] Fig.16 Schematic diagram of DAB converter-ALF-ESSPS modulation-mutation a-core BH loop;

[0052] Fig.17 It is a schematic diagram of DAB converter-ALF-ESSPS modulation-mutated R-time domain waveform;

[0053] Fig.18 Schematic diagram of DAB converter-ALF-ESSPS modulation-mutated R-core BH loop;

[0054] Fig.19 It is a schematic diagram of QAB converter-ALF-ESSPS modulation-mutation D4-time domain waveform;

[0055] Fig. 20 Schematic diagram of QAB converter-ALF-ESSPS modulation-mutation D4-core BH loop;

[0056] Fig.21 It is a schematic diagram of the comparison of the time domain waveforms of the QAB converter-mutation D4;

[0057] Fig. 22 It is a comparison diagram of QAB converter-mutation D4-core BH loop;

[0058] Fig.23 A structural block diagram of a modulation system of a converter provided in an embodiment of the present application;

[0059] Fig.24 A structural block diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The present application is further described in detail below in conjunction with the embodiments and drawings. It is to be understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It is also necessary to explain that, for ease of description, only the parts related to the application are shown in the drawings.

[0061] It should be noted that, in the absence of conflict, the embodiments of the present application, that is, the features of the embodiments, can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0062] The modulation method, system, device and medium of the converter according to the embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0063] In an embodiment of the present application, the converter refers to a dual active bridge (DAB) converter or a multiple active bridge (MAB) converter including at least two H-bridges. The basic working principles of the dual active bridge converter and the multiple active bridge converter are first described below.

[0064] like Figure 1 As shown, it is the topological structure diagram of the dual active bridge converter. Figure 1 As shown in Figure 1, the dual active bridge DAB converter consists of two fully controlled H bridges (H bridge 1 and H bridge 2) and a dual-winding high-frequency transformer (the number of turns of the two windings are n1 and n2 respectively). The DC voltage of H bridge 1 is V dc,1 , the DC voltage of H bridge 2 is V dc,2 .

[0065] Q1, Q2, Q3, and Q4 are semiconductor power switches (usually silicon-based IGBTs, silicon-based power MOSFETs, or silicon carbide power MOSFETs) for the front bridge upper tube, front bridge lower tube, rear bridge upper tube, and rear bridge lower tube of H bridge 1, respectively. The corresponding gate switch signals are S1, S2, S3, and S4 (S x =1 represents the gate-level conduction signal, S x =0 represents a gate-level shutdown signal).

[0066] Q5, Q6, Q7, and Q8 are semiconductor power switches of the front bridge upper tube, front bridge lower tube, rear bridge upper tube, and rear bridge lower tube of H bridge 2. The corresponding gate switch signals are S5, S6, S7, and S8 respectively.

[0067] H bridge 1 can modulate the DC voltage V by different timing combinations (modulation) of S1, S2, S3, and S4. dc,1 Convert to frequency f sw , the duty cycle d1 is adjustable, and the fundamental phase angle is (i.e. reference phase) of the high-frequency square wave v1. H-bridge 2 can modulate S5, S6, S7, and S8 to convert the DC voltage V dc,2 Convert to frequency f sw , the duty cycle d2 is adjustable, and the fundamental phase angle is (relative to the reference phase) of the high frequency square wave v2.

[0068] The high-frequency square wave voltages v1 and v2 output by the two H-bridges are simultaneously applied to the two windings on the primary and secondary sides of the dual-winding high-frequency transformer. The power flow between the two H-bridges is controlled by the phase difference between the two high-frequency square wave voltages, thereby realizing the basic control of the dual active bridge converter.

[0069] like Figure 2 As shown, the topology of the multi-active bridge converter is combined with Figure 2 As shown in the figure, the MAB converter consists of N fully controlled H bridges (H bridge 1, ..., H bridge N) and a multi-winding high-frequency transformer (the number of winding turns are n1, ..., n N ). The DC voltages of the N H bridges are V dc,1 ,…,V dc,N .

[0070] Q 1,Uj , Q 2,Uj , Q 3,Uj , Q 4,Uj They are the semiconductor power switches of the front bridge upper tube, front bridge lower tube, rear bridge upper tube, and rear bridge lower tube of H bridge j (j∈[1,N]). The corresponding gate switch signals are S 1,Uj , S 2,Uj , S 3,Uj , S 4,Uj .

[0071] H bridge j can modulate S1,Uj, S2,Uj, S3,Uj, S4,Uj to convert the DC voltage V dc,j Convert to frequency f sw , duty cycle d j Adjustable, and the fundamental phase angle is (relative to the reference phase ) of high frequency square wave v j The high-frequency square wave voltage (v1,…,v N ) are simultaneously applied to the N windings of the multi-winding high-frequency transformer, and the phase difference between the N high-frequency square wave voltages controls the power flow between the N H-bridges respectively, thereby realizing the basic control of the multi-active bridge converter.

[0072] Transfer power of MAB converter under GPS modulation: Let the DC voltage of H bridge j be V d ' c,j , the DC voltage of H bridge i is V d ' c,i When GPS is modulated, the high-frequency square wave output by H bridge j is v j j(frequency f act , half switching cycle duty cycle d j ∈[0,1], outward shift compared to ), the high frequency square wave output by H bridge i is v i ′(frequency f act , half switching cycle duty cycle d i ∈[0,1], outward shift compared to ). At this time, the difference between the outward displacement of H bridge j and H bridge i is D j,i =D j -D i ,and like Figure 3 As shown, it is a schematic diagram of the H-bridge high-frequency voltage of the MAB converter during GPS modulation. Therefore, the (2N-1) degrees of freedom during GPS modulation are d1, d2, …, d N ; Assume that the H-bridge with the most advanced phase is shifted outwards by D1 = 0, then D2∈[0,0.5],…,D N ∈[0,0.5].

[0073] The power (average value of the switching cycle) transferred from H-bridge j to H-bridge i during GPS modulation of the MAB converter is shown in Table 1. The half-switching cycle power (H-bridge j → H-bridge i) during GPS modulation of the MAB converter. Both SPS modulation and ESSPS modulation are special cases of GPS modulation.

[0074] Table 1

[0075]

[0076] Since the MAB converter is usually defined without DC bias as: the winding AC current i′ j In steady state, there is no bias, that is, DC component. In the π-shaped equivalent circuit model of a multi-winding transformer considering the magnetizing inductance, the AC current at the port There should be no DC component in steady state, and the following two specific requirements need to be met at the same time: First, L′ j,is The current on the transformer should not have a DC component in steady state; secondly, considering the excitation state of the transformer core, L ′ ' j,ms The current on the MOSFET should not have a DC component in steady state.

[0077] For any inductor, according to the law of electromagnetic induction, When the series resistance is ignored and the terminal voltage is given externally, the inductor terminal voltage When the inductance is constant, That is to say, the time integral of the inductor terminal voltage determines the inductor current value. Therefore, for any inductance (L′ j,is , L′ ′j,ms ) terminal voltage (v′ j -v′ i , v′ j ) is a completely symmetrical square wave (GPS modulation), it can meet the requirement of steady-state without DC bias.

[0078] However, there are two major problems with MAB modulation methods (such as SPS modulation and ESSPS modulation), which affect their performance and practical applications:

[0079] (1) In SPS modulation and ESSPS modulation, even if the input parameters are constant, the excitation current i j ′, ms There is still a transient bias, and the time constant τ = L j ′, ms / R ms The larger the transient time, the longer the transient time, which causes the transformer bias magnetization and AC and DC currents to increase, the transient performance of the MAB converter to decrease, and the loss to increase.

[0080] (2) In SPS modulation and ESSPS modulation, the temporal overlap of the AC voltage and current of adjacent switching cycles is inevitable. Therefore, when the modulation input parameters change, especially when the external shift phase changes, abnormal pulse voltage will be generated, resulting in uncontrollable power transfer; at the same time, due to the change in input parameters, the time integral of the square wave voltage is asymmetric, resulting in significant transient winding current bias; the transient steady-state performance of the MAB converter is reduced and the loss is increased.

[0081] Figure 4 FIG. 1 is a flow chart of a modulation method of a converter according to an embodiment of the present application. Figure 4 As shown, a modulation method of a converter according to an embodiment of the present application specifically includes:

[0082] S101: Setting modulation parameters.

[0083] In one embodiment of the present application, setting modulation parameters includes: constraining the modulation parameters, and calculating the modulation parameters according to key input parameters when the modulation parameters are constrained, wherein the constraints on the modulation parameters include: the AC voltage and current of adjacent switching cycles do not overlap in time, and the start or end time point of a half-switching cycle is zero voltage; the time integral of the half-switching cycle voltage of all ports is the same; the independent excitation inductor current rise value of the first half cycle is equal to the difference between the expected forward peak value of the independent excitation inductor current and the expected reverse peak value of the independent excitation inductor current of the previous switching cycle; the time that the independent excitation inductor current maintains the forward peak value within the switching cycle is equal to the time that the reverse peak value is maintained.

[0084] In a specific example, the key input parameters include a frequency reduction coefficient, a global duty cycle coefficient and an external shift comparison; the modulation parameters are calculated according to the key input parameters, including: according to the frequency reduction coefficient, the global duty cycle coefficient and the external shift comparison, the duty cycle of the first half cycle, the duty cycle of the second half cycle, the external shift comparison of the first half cycle, the external shift comparison of the second half cycle, the frequency reduction coefficient of the first half cycle and the frequency reduction coefficient of the second half cycle are obtained.

[0085] S102: Based on the modulation parameters, the converter is modulated with a preset modulation strategy, wherein the modulation parameters are set as follows: different duty cycles and different shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated, and at the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequencies of the first half cycle and the second half cycle of each switching cycle are reduced by different ratios.

[0086] Generally speaking, the modulation strategy of the multi-active bridge converter includes a single phase shift (SPS) modulation strategy or an extended soft switching phase shift (ESSPS) modulation strategy. In the present application, the preset modulation strategy adopts an extended soft switching phase shift (ESSPS) modulation strategy. Among them, during SPS modulation and ESSPS modulation, even if the input parameters are constant, the excitation current still has a transient bias, and the time constant is large, and the transient time is long, which causes the transformer bias and AC and DC currents to increase, and the transient performance of the MAB converter is reduced and the loss is increased. During SPS modulation and ESSPS modulation, the temporal overlap of the AC voltage and current of adjacent switching cycles is inevitable. Therefore, when the modulation input parameters change, especially when the external shift phase changes, an abnormal pulse voltage will be generated, resulting in uncontrollable power transfer; at the same time, due to the change in input parameters, the time integral of the square wave voltage is asymmetric, and the winding current produces a significant transient bias; the transient steady-state performance of the MAB converter is reduced and the loss is increased.

[0087] In order to completely eliminate the transient steady-state winding current bias and DC bias magnetism, in the embodiments of the present application, on the basis of ESSPS modulation, the following direct modulation parameters are set: different duty cycles are set for the first half cycle and the second half cycle of the switching cycle; different external shift phases are set for the first half cycle and the second half cycle of the switching cycle; at the end of the first half cycle and the second half cycle of the switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequencies of the first half cycle and the second half cycle are reduced by different ratios. On this basis, the direct modulation parameters are constrained as follows, so that the direct modulation parameters can be calculated based on the key input parameters: (1) To ensure that the change of the modulation parameters of each half-switching cycle will not affect the voltage and current of the adjacent half-switching cycle, it is necessary to ensure that the AC voltage and current of the adjacent switching cycles do not overlap in time, and the start or end time point of the half-switching cycle is zero voltage; (2) The time integral of the half-switching cycle voltage of all ports is the same, that is, the current of the power transfer inductor is zero at the start or end time point of the half-switching cycle; (3) The rise value of the independent excitation inductor current in the first half cycle is equal to the difference between the expected positive peak value of the independent excitation inductor current and the expected reverse peak value of the independent excitation inductor current in the previous switching cycle, that is, the positive peak value and reverse peak value of the independent excitation inductor current are the same in one switching cycle; (4) The time that the independent excitation inductor current maintains the positive peak value in one switching cycle is equal to the time that it maintains the reverse peak value, that is, the forward time integral and reverse time integral of the independent excitation inductor current are the same in one switching cycle.

[0088] According to the modulation method of the converter of the embodiment of the present application, when the modulation input parameters change, there is no transient winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, the power transfer delay is small and the accuracy is high. In addition, the modulation strategy is simple and easy to implement, does not require additional sensor signal feedback and complex control process, the modulation strategy is independent of the transformer inductance parameters, has strong robustness, strong practicality, and high light load efficiency.

[0089] The modulation method of the converter of the embodiment of the present application is recorded as the ALF-ESSPS modulation method, which is based on the ESSPS modulation, and is designed as follows to completely eliminate the winding current bias and DC bias magnetism:

[0090] (1) Different duty ratios (d) are set for the first and second half of a switching cycle;

[0091] (2) Different external shift ratios (D) are set for the first and second half of a switching cycle. j );

[0092] (3) At the end of the first half and the second half of a switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half and the second half is reduced by different ratios (R).

[0093] The (N+1) key input parameters of ALF-ESSPS modulation are R (frequency reduction coefficient), a (global duty cycle coefficient) and D j (Compared with outward migration). j , a, and R have no coupling relationship and can be set arbitrarily. j Used to control power transfer. Both R and a can set a larger jump in a single cycle, and the value range is wide. Frequency reduction coefficient R: reduces the equivalent switching frequency, which can be used to improve system efficiency; global duty cycle coefficient a: changes the ratio of the duty cycle of all ports of MAB at the same time, which can be used for start-stop control, temporary steady-state performance optimization, etc.

[0094] In the modulation of the MAB converter, let f act The ESSPS modulates the switching frequency before adding the phase-shifted zero voltage sequence. In the MAB converter operation, f act Generally, it is a fixed or slowly changing given parameter (the actual working state is limited to the core material, voltage, frequency, current, iron loss and copper loss, etc.). ALF-ESSPS adds phase-shifted zero voltage sequences with different duration ratios at the end of the first half cycle and the second half cycle respectively; when the frequency reduction coefficient R increases, the actual equivalent switching frequency f eq =f act / R decreases accordingly, but as long as f actIf the switching period of ESSPS is fixed, the frequency restriction will not be violated during operation. ALF-ESSPS equivalent switching cycle

[0095] According to (N+1) key input parameters R, a and D j , can be calculated by the ALF-ESSPS strategy, and (2N+2N-2+2=4N) direct modulation parameters are obtained: dj,,FH (duty cycle of the first half cycle), dj,,SH (duty cycle of the second half cycle), Dj,,FH (shift ratio of the first half cycle) and D j,SH (Compared with the outward shift in the second half of the cycle), R FH (frequency reduction coefficient in the first half cycle) and R SH (Frequency reduction coefficient in the second half cycle).

[0096] The kth equivalent switching cycle T after the ALF-ESSPS modulation operation starts eq,k The DC voltage detection value of port j at the beginning of the current switching cycle is V d ' c,j,k , the key input parameter is R k 、a k and D j,k , then the 6 direct modulation parameters of port j in this cycle are: d j,FH,k (duty cycle of the first half cycle), d j,SH,k (duty cycle of the second half period), D j,FH,k (Compared with the first half cycle outward shift) and D j,SH,k (Compared with the outward shift in the second half of the cycle), R FH,k (frequency reduction coefficient in the first half cycle) and R SH,k (frequency reduction coefficient of the second half cycle); where R FH,k and R SH,k The operation of port j in the kth switching cycle can be divided into 10 time stages, as shown in Table 2, which is the kth switching cycle T eq,k Each segment time occupies half a period Proportion.

[0097] Table 2

[0098]

[0099] like Figure 5As shown, the 10 time stages of the ALF-ESSPS modulation cycle are shown, among which stage ① and ⑥ are the phase shift of port j relative to port 1 in the first half cycle and the second half cycle respectively, and the H-bridge output voltage is 0 during this period; stage ②, ④ and ⑦, ⑨ are the symmetrical zero voltage part of the square wave output duty cycle of port j in the first half cycle and the second half cycle respectively, and the H-bridge output voltage is 0 during this period; stage ③ and ⑧ are the effective voltage part of the square wave output duty cycle of port j in the first half cycle and the second half cycle respectively, and the H-bridge output voltage is V d ' c,j,k and -V ′ d c,j,k ; Stages ⑤ and ⑩ are the parts of the zero voltage time added after the first half cycle and the second half cycle respectively minus the phase shift time. During this time period, the H-bridge output voltage is 0.

[0100] In order to ensure that the change of modulation parameters of each half switching cycle does not affect the voltage and current of the adjacent half switching cycle, it is necessary to ensure that the start or end time point of the half switching cycle is zero voltage. Therefore, the time length of stages ⑤ and ⑩ in Table 2 must be greater than or equal to zero.

[0101] In addition, the power transfer inductor L ′ j, is The terminal voltage and current, as well as the independent excitation inductance L j ′, ms The terminal voltage and current need to be limited according to the following theory to ensure the elimination of the transient steady-state bias. The following analyzes how to eliminate the winding current bias and DC bias magnetism by calculating 4N direct modulation parameters.

[0102] Among them, the duty cycle of the first half of the kth switching cycle is d j,FH,k is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the k-th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, and the DC voltage of the port with the lowest voltage in the k-th switching cycle;

[0103] The duty cycle d of the second half of the kth switching cycle j,SH,k It is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the DC voltage of the port j in the kth switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle.

[0104] The frequency reduction coefficient of the first half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle;

[0105] The frequency reduction coefficient of the second half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle;

[0106] Before calculating the frequency reduction coefficient of the first half cycle of the kth switching cycle and calculating the frequency reduction coefficient of the second half cycle of the kth switching cycle, an approximate method or a prediction method is used to obtain the DC voltage of the k+1th cycle.

[0107] The first half of the kth switching cycle is shifted outward compared to D j,FH,k is obtained according to the outward shift ratio of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port j of the k-1th switching cycle, and the duty cycle of port j of the k-1th switching cycle;

[0108] The second half of the kth switching cycle is shifted outward compared to D j,SH,k is obtained based on the outward shift ratio of the kth switching cycle and the outward shift ratio of the first half of the kth switching cycle. Specifically:

[0109] (1) Duty cycle d in the second half of the cycle j,SH,k

[0110] Power transfer inductor L j ′, is The voltage across the terminals is When the time integral of the half switching cycle voltage of all ports is the same, L j ′, is The voltage integral of the half switching cycle of the voltage across the two terminals Therefore, it can be guaranteed that j ′, isAt the beginning or end of a half switching cycle, it is 0. Figure 6 As shown, the time integral of the half switching cycle voltage of each port is shown.

[0111] In the kth cycle, let the DC voltage of the port with the lowest voltage be V d ' c,min,k , assume that the duty cycle of the second half period is equal to the global duty cycle coefficient a k To ensure L j ′, is The current value starts at 0 and ends at 0 in half a cycle, and all ports meet the ZVS soft switching conditions. It is necessary to make the time integral of the half switching cycle voltage of all ports the same:

[0112] d j,SH,k V d ′ c,j,k =a k V d ′ v,min,k (5)

[0113] The duty cycle of the second half of each port should be set to:

[0114]

[0115] (2) Duty cycle d in the first half of the cycle j,FH,k

[0116] For the jth port, the independent magnetizing inductor L j ′, ms The voltage across the two ends is v j ′. By setting the time integral of the voltage in the first half of the kth switching cycle equal to the average of the time integral of the voltage in the second half of the k-1th switching cycle and the time integral of the voltage in the second half of the kth switching cycle, it can be ensured that the rising value of the independent magnetizing inductor current in the first half of the kth switching cycle is equal to the difference between the expected forward peak value of the independent magnetizing inductor current in the kth switching cycle and the expected reverse peak value of the independent magnetizing inductor current in the k-1th switching cycle, that is, the forward and reverse peak values ​​of the independent magnetizing inductor current are the same in a whole switching cycle (I j ′, ms,FH,k =I j ′, ms,SH,k ),like Figure 7 As shown, the relationship between the independent excitation inductance current change and the duty cycle of port j is shown.

[0117]

[0118] The duty cycle of the first half cycle of each port is:

[0119]

[0120] (3) Frequency reduction coefficient R FH,k and R SH,k

[0121] At the end of the first half cycle and the second half cycle, each port adds a phase-shifted zero voltage sequence, and the ratio of the zero voltage duration added in the first half cycle and the second half cycle is (R FH,k -1) and (R SH,k -1), and the frequency reduction factor of a whole cycle

[0122] For the jth port, the forward and reverse peak values ​​of the independent magnetizing inductor current are the same in a complete switching cycle (I j ′, ms,FH,k =I j ′, ms,SH,k ), the time (T k,Area+ =t④, k +t⑤, k +t⑥, k +t⑦, k ) is equal to the time to maintain the reverse peak value (T k,Area- =t⑨, k +t⑩, k +t ①,k+1 +t ②,k+1 ), the forward time integral and reverse time integral of the independent magnetizing inductor current can be guaranteed to be the same within one switching cycle, that is, the independent magnetizing inductor current has no DC component and there is no transient core flux density bias. Figure 8 As shown, the forward time integral and reverse time integral of the independent excitation inductor current at port j are shown.

[0123] Therefore, the zero voltage ratio needs to be added to meet the following conditions:

[0124] t④, k +t⑤, k +t⑥, k +t⑦, k =t⑨, k +t⑩, k +t①, k+1 +t②, k+1 (9)

[0125] Right now:

[0126]

[0127] And R FH,k -R SH,k =2Ck Must be the same for all ports in the kth switching cycle (2C k is a constant).

[0128] Since for port 1, Therefore, the following formula holds for all ports:

[0129]

[0130] and:

[0131]

[0132] Since the total equivalent switching cycle length ratio satisfies:

[0133] R FH,k +R SH,k =2R k (13)

[0134] According to (11) and (13), R FH,k and R SH,k :

[0135]

[0136]

[0137] (4) Outward migration compared to D j,FH,k and D j,SH,k

[0138] According to formula 12:

[0139]

[0140] Further, according to the given value D of the outward shift of the kth switching cycle j,k , we can set:

[0141]

[0142]

[0143] Where D in formulas 17 and 18 is j,FH,k and D j,SH,k The condition in formula 16 can be satisfied.

[0144] From the above, it can be seen that in the ALF-ESSPS modulation strategy, the basic theoretical formulas for eliminating transient winding current bias and DC bias magnetism are formulas 5, 7, 11, 12 and 13 respectively.

[0145] For direct modulation parameters, the (N-1) key input parameters R, a and D can be obtained according to formulas 5, 7, 11, 12 and 13. j , and obtain the direct modulation parameter d j,FH ,d j,SH , D j,FH , D j,SH , R FH and R SH The 4N calculation expressions of are used as the theoretical basis of the ALF-ESSPS modulation strategy, namely, Formulas 6, 8, 14, 15, 17 and 18.

[0146] The actual cycle calculation strategy can be obtained according to formulas 6 and 8: j,FH,k The calculation strategy is:

[0147]

[0148] According to formulas 8, 14 and 15, we can get R FH,k and R SH,k The calculation strategy is:

[0149]

[0150]

[0151] In formulas 20 and 21, in the kth cycle, the external input parameter a of the k+1th cycle is used. k+1 , which is impossible in practical applications, so it is necessary to use a in all the above formulas. k-1 Replace a k , as the given value of a for the kth cycle. Therefore, a delay of about one switching cycle is added to the dynamic characteristics of the ALF-ESSPS modulation of the MAB converter.

[0152] In summary, the actual cycle-by-cycle calculation strategy for ALF-ESSPS modulation is summarized as Equation 22 to Equation 27:

[0153]

[0154]

[0155]

[0156]

[0157]

[0158]

[0159] Approximation or prediction of DC voltage:

[0160] In formulas 24 and 25, R FH,k and R SH,k The calculation of V in the k+1th cycle needs to be known in advance. ′ d c,1,k+1 and V d ' c,min,k+1 . It can be obtained by using approximate method or prediction method.

[0161] Approximate method: Since it is assumed that the DC voltage will not change rapidly within a single cycle, it can be approximately assumed that V′ dc,1,k+1 ≈V′ dc,1,k , V′ dc,min,k+1 ≈V′ dc,min,k . Then, Formula 28 and Formula 29 can be used to replace Formula 24 and Formula 25 respectively:

[0162]

[0163]

[0164] Prediction method 1: The trend of DC voltage can be used to predict the DC voltage of the next cycle:

[0165]

[0166] Prediction method 2: When more parameters, source-load characteristics, and operating status of the system are known, more complex prediction methods such as model predictive control (MPC) can be used to predict the DC voltage of the next cycle.

[0167] Port 1 switching based on outbound comparison:

[0168] In formulas 24 to 27, the duty cycle d of the first port is used as the phase reference in the calculation of the frequency reduction coefficient and the shift ratio between the first half cycle and the second half cycle. 1,FH At the beginning of each equivalent switching cycle, the port with the smallest input external shift ratio needs to be marked as port 1, and the external shift ratios of each port need to be updated based on port 1 (D1=0).

[0169] Since V′ is dc,1,k+1 Approximation and prediction are made. If port 1 changes in the k+1th cycle, an additional transition and switching process of 1 cycle is required: if port 1 in the k+1th cycle is different from port 1 in the kth cycle, the k+1th cycle should be used as a transition period. During the transition period, the external shift comparisons of port 1 in the previous cycle and port 1 in the current cycle are set to 0 at the same time, and port 1 in the k+1th cycle is marked to achieve marked transition and switching; then, starting from the k+2th cycle, port 1 in the kth cycle resumes outputting the externally given external shift comparison.

[0170] The key input parameter value ranges of ALF-ESSPS need to meet the following requirements:

[0171] (a) Global duty cycle coefficient a

[0172] The global duty cycle coefficient a∈[0,1]. When a=0, the AC voltage output by the H-bridge is always 0; when a=1, the voltage utilization rate of the MAB is the highest.

[0173] In addition, according to (23), d j,FH,k The size of is related to the DC voltage change rate and the global duty cycle coefficient. d ' c,j,k When descending rapidly, may be greater than 1; at this time, if the global duty cycle coefficient a is close to 1, d may appear j,FH,k If it is greater than 1, a judgment needs to be made and if it exceeds the limit, d is limited by reducing a. j,FH,k ≤1.

[0174] (b) Outward shift compared to D j

[0175] Outward migration compared to D j ∈[0,0.5]. It is set that in each equivalent switching cycle, the H bridge with the most advanced phase is numbered 1, and its external shift ratio is D1=0, then the other H bridges lag behind H bridge 1, and the lag angle must be within 90°, that is, D2∈[0,0.5],…,D N ∈[0,0.5]. Calculate the outward shift ratio D according to (26) and (27) j,FH,k and D j,SH,k It is necessary to make a judgment and limit D by changing a when it exceeds the limit. j,FH,k ∈[0,0.5], D j,SH,k ∈[0,0.5].

[0176] (c) Frequency reduction factor R

[0177] The lengths of stages ⑤ and ⑩ in Table 2 must be greater than or equal to zero to ensure that there is no overlap between adjacent half-cycles. This is the key to the ALF-ESSPS modulation method to avoid abnormal pulse voltages caused by transients or parameter changes.

[0178]

[0179]

[0180] The value range of the frequency reduction coefficient R is:

[0181] Rk ≥(1+D max,FH,k )+ΔR (33)

[0182] Where ΔR is R FH,k and R SH,k 2 times the absolute value of the difference:

[0183]

[0184] It can be seen that the minimum value of R is related to the rate of change of the DC voltage and the rate of change of the global duty cycle coefficient. When the DC voltage remains unchanged and the global duty cycle coefficient remains unchanged, R FH,k and R SH,k The difference is 0, just need:

[0185] R k ≥1+D max,FH,k (35)

[0186] The power transmitted between port j and port i in the first half cycle and the second half cycle of ALF-ESSPS modulation (P FH,j,i and P SH,j,i ) can be derived according to the following formula, combined with the GPS power characteristics in Table 1:

[0187]

[0188]

[0189] The total power at port j is:

[0190]

[0191] In the upper control, according to the power reference value P 1,ref ,P 2,ref ,…,P N,ref (where P 1,ref +P 2,ref +…+P N,ref = 0), can be controlled according to the system parameters and status (such as P ref , L Ts0 and V′ dc etc.), by decoupling the instantaneous power, we can obtain the outward shift ratio D2,…,D N , thereby controlling the power of all ports of the MAB converter simultaneously.

[0192] According to formulas 26 and 27, the actual outward displacement is (D j,FH and D j,SH ) requires about 0.5 equivalent switching cycles to reach the set value, that is, a given external shift (D j), plus the delay of one equivalent switching cycle of the global duty cycle coefficient setting value, it can be considered that the dynamic response process of ALF-ESSPS modulation has a delay of about 1.5 switching cycles. If the power reference input and decoupling are further added in the upper-level control according to (38), and the key input parameters are calculated according to the current modulation state and the ALF-ESSPS power characteristics, a high dynamic response speed of the power control process can be achieved.

[0193] In specific applications, the specific implementation of ALF-ESSPS modulation can be achieved by using a microcontroller such as a single chip microcomputer or an FPGA.

[0194] like Fig. 9 As shown, it is a schematic diagram of the specific implementation of ALF-ESSPS modulation. The implementation scheme of ALF-ESSPS modulation includes three modules: (1) carrier generation and synchronization module, (2) direct modulation parameter calculation module, and (3) gate signal generation module.

[0195] Except for (N+1) key input parameters (a, D j and R), N detection feedback signals (V d ' c,j ), 1 given frequency signal (f act ), 4N direct modulation parameters (d j,FH d j,SH , D j,FH , D j,SH , R FH and R SH )、4N gate output signals (g 1,j , g 2,j , g 3,j and g 4,j ), the block diagram also involves five control signals: an enable signal EN, a zero voltage mode selection signal MZ, a modulation mode switching signal MS, a global carrier signal CR, and a trigger signal TR.

[0196] The enable signal EN is an external input signal used to control the start and stop of ALF-ESSPS modulation.

[0197] The zero voltage mode selection signal MZ is an external input signal used to switch the zero voltage mode of the gate signal (for example, when MZ=0, the upper and lower tubes of the H-bridge are alternately turned on in adjacent half cycles; when MZ=1, the two upper tubes of the H-bridge are always turned on; when MZ=2, the two lower tubes of the H-bridge are always turned on).

[0198] The modulation mode switching signal MS is an external input signal used to switch the output of ALF-ESSPS modulation and other modulation modes.

[0199] The global carrier signal CR is an internal sawtooth wave signal generated by the carrier generation and synchronization module, and includes the carrier and synchronization information required by the gate signal generation module.

[0200] The trigger signal TR is an internal rising edge signal generated by the carrier generation and synchronization module, which realizes the global carrier signal CR clearing or CR initial value assignment when the modulation mode is switched, the ZOH sampling of some signals in the carrier generation and synchronization module, and the synchronous triggering and ZOH sampling of the direct modulation parameter calculation module.

[0201] The functions and timing of the carrier generation and synchronization modules are as follows: Fig.10 As shown, it is a schematic diagram of the functions and timing of the carrier generation and synchronization modules.

[0202] The global carrier signal CR always has the same time slope 2f act It rises and is cleared when the trigger signal TR rises or is assigned a value when the modulation mode is switched.

[0203] The trigger signal TR is set to 1 when the global carrier signal CR reaches 2R, or when MS changes (rising edge or falling edge), and is set to 0 after a short period of time (using a monostable trigger or a comparator to CR).

[0204] The function of the modulation mode switching signal MS is to control the switching between the ALF-ESSPS modulation mode and the ESSPS modulation mode.

[0205] When working in ALF-ESSPS modulation mode, after detecting the falling edge of MS, the system switches to ALF-ESSPS modulation mode at the appropriate time and conditions (the effective phase of ALF-ESSPS modulation needs to be set to be the same as the effective phase of ESSPS modulation at the switching moment, and the two modulations expect all ports to be in the first half cycle ②③④ or the second half cycle ⑦⑧⑨ at the same time without overlap), and R is set to an external set value greater than 1.

[0206] When working in ESSPS modulation mode, after detecting the rising edge of MS, the system switches to ESSPS modulation mode at the appropriate time and conditions (the effective phase of ESSPS modulation needs to be set to be the same as the effective phase of ALF-ESSPS modulation at the switching moment, and the two modulations expect all ports to be in the first half cycle ②③④ or the second half cycle ⑦⑧⑨ at the same time without overlap), and set R=1.

[0207] like Fig.11As shown, it is a schematic diagram of switching between modulation modes of the MAB converter. Switching between modulation modes of the MAB converter can give full play to the advantages of various modulation modes (ALF-ESSPS mode: when parameters change, there is no transient steady-state DC bias and high light-load efficiency; ESSPS and SPS modes: when the working state is fixed, the voltage utilization rate is high and the maximum transferred power is high).

[0208] In the direct modulation parameter calculation module, each rising edge of the trigger signal TR triggers a ZOH sampling and calculation process. The flow chart is as follows: Fig.12 As shown, it is a flow chart of the direct modulation parameter calculation module.

[0209] Fig.13 The gate signal generation module is a function and timing diagram. The input of the gate signal generation module is the global carrier signal CR, the zero voltage mode selection signal MZ, the gate enable signal EN, and 4N direct modulation parameters d j,FH,k and d j,SH,k , D j,FH,k and D j,SH,k , R FH,k and R SH,k . R FH,k +R SH,k =2R is used to divide CR into two parts, namely the first half cycle and the second half cycle; D j,FH,k and D j,SH,k It is used to lag CR in the first half cycle and the second half cycle respectively. and After that, the positive and negative triangle wave carrier CR' is generated. j,FH,k and d j,SH,k Used to compare with the carrier CR' and output the switching signal S according to the zero voltage mode F,j and S B,j .

[0210] The zero voltage mode selection signal MZ is an external input signal used to switch the zero voltage mode of the gate signal (for example, when MZ=0, the upper and lower tubes of the H-bridge are alternately turned on in adjacent half cycles; when MZ=1, the two upper tubes of the H-bridge are always turned on; when MZ=2, the two lower tubes of the H-bridge are always turned on). Fig.14 As shown, a schematic diagram of the switching function output of different zero voltage mode selection signals MZ is shown.

[0211] When the enable signal EN = 1, the switch tube Q 1,j The gate signal g 1,j =S F,j Otherwise, after an equivalent switching cycle, let g 1,j =0;

[0212] When the enable signal EN = 1, the switch tube Q2,j The gate signal Otherwise, after an equivalent switching cycle, let g 1,j =0;

[0213] When the enable signal EN=1, the switch tube Q 3,j The gate signal g 3,j =S B,j Otherwise, after an equivalent switching cycle, let g 1,j =0;

[0214] When the enable signal EN=1, the switch tube Q 4,j The gate signal Otherwise, after an equivalent switching cycle, let g 1,j =0.

[0215] Effectiveness of ALF-ESSPS modulation (DAB converter)

[0216] DAB converter: global duty cycle factor a changes

[0217] (1) Step change of global duty cycle coefficient a

[0218] Fig.15 and Fig.16 The time domain waveform and core BH loop of the DAB converter when the global duty cycle coefficient changes stepwise during ALF-ESSPS modulation, where: Fig.15 This is a schematic diagram of DAB converter-ALF-ESSPS modulation-mutation a-time domain waveform. Fig.16 The schematic diagram of DAB converter-ALF-ESSPS modulation-mutation a-core BH loop. The transformer winding AC current has no transient steady-state bias, and the excitation current has no transient steady-state bias; the transformer working state is to switch to another fixed working loop around the zero point within a switching cycle, and the core has no transient steady-state DC bias.

[0219] DAB converter: frequency reduction factor R changes

[0220] (1) Step change of frequency reduction coefficient R

[0221] Fig.17 and Fig.18 The time domain waveform and core BH loop of the DAB converter when the frequency reduction coefficient changes stepwise during ALF-ESSPS modulation, where: Fig.17 This is a schematic diagram of DAB converter-ALF-ESSPS modulation-mutated R-time domain waveform. Fig.18The schematic diagram of DAB converter-ALF-ESSPS modulation-mutated R-core BH loop. The transformer winding AC current has no transient steady-state bias, and the excitation current has no transient steady-state bias; the transformer working state is a fixed working loop around the zero point, and the core has no transient steady-state DC bias.

[0222] QAB Converter: Switching from ALF-ESSPS Modulation to ESSPS Modulation

[0223] QAB Converter: Outward Shift Compared to D j change

[0224] (1) Outward migration compared to D j Step Changes

[0225] Fig.19 and Fig. 20 The time domain waveform and core BH loop of the QAB converter when the external shift changes stepwise during ALF-ESSPS modulation, where: Fig.19 This is a schematic diagram of the QAB converter-ALF-ESSPS modulation-mutation D4-time domain waveform. Fig. 20 The diagram is a QAB converter-ALF-ESSPS modulation-mutation D4-core BH loop diagram. The transformer winding AC current has no transient steady-state bias, and the excitation current has no transient steady-state bias; the transformer working state is a fixed working loop around the zero point, and the core has no transient steady-state DC bias.

[0226] Comparison with other modulations

[0227] Qualitative comparison

[0228] Compared with SPS modulation and ESSPS modulation, when the modulation input parameters change, ALF-ESSPS modulation has no transient steady-state winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, as shown in Table 3, which shows the qualitative comparison between ALF-ESSPS modulation and other modulations. The power transmission delay of ALF-ESSPS modulation is small and the accuracy is high; the modulation method is simple and easy, and does not require additional sensor signal feedback and complex control process; the modulation strategy is independent of the transformer inductance parameters, and has strong robustness and practicality; and the light load efficiency is high.

[0229] Table 3

[0230]

[0231] Startup transient (ALF-ESSPS vs. ESSPS vs. SPS)

[0232] Fig.21 and Fig. 22The time domain waveform and core BH loop of the QAB converter during the step change of the outward shift during ALF-ESSPS modulation are compared with ESSPS modulation and SPS modulation.

[0233] During ALF-ESSPS modulation, the transformer winding AC current has no transient steady-state bias, and the excitation current has no transient steady-state bias; the transformer working state is a fixed working loop around the zero point, and the magnetic core has no transient steady-state DC bias.

[0234] During ESSPS modulation or SPS modulation, there are large transient biases in the winding AC current and the excitation current, and there is also a large transient DC bias in the magnetic core.

[0235] According to the modulation method of the converter of the embodiment of the present application, when the modulation input parameters change, there is no transient winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, the power transfer delay is small and the accuracy is high. In addition, the modulation strategy is simple and easy to implement, does not require additional sensor signal feedback and complex control process, the modulation strategy is independent of the transformer inductance parameters, has strong robustness, strong practicality, and high light load efficiency.

[0236] In the above description:

[0237] Multiple Active Bridge (MAB)

[0238] Single Phase Shift (SPS)

[0239] Extended Soft Switching Phase Shift (ESSPS)

[0240] Asymmetric Lower Frequency-Extended Soft Switching Phase Shift (ALF-ESSPS)

[0241] Generic Phase Shift (GPS)

[0242] Zero Voltage Switching (ZVS)

[0243] Model Predictive Control (MPC)

[0244] Field Programmable Gate Array (FPGA)

[0245] Zero Order Hold (ZOH)

[0246] Dual Active Bridge (DAB)

[0247] Quadruple Active Bridge (QAB)

[0248] Fig.23 is a structural block diagram of a modulation system of a converter according to an embodiment of the present application. The converter includes at least two H-bridges and a multi-winding high-frequency isolation transformer. The structure of the converter has been described in one or more of the above examples, and will not be repeated here. Fig.23 As shown, the modulation system of the converter according to the embodiment of the present application includes: a modulation parameter setting module 7110 and a modulation module 7120, wherein:

[0249] A modulation parameter setting module 7110, used to set modulation parameters;

[0250] The modulation module 7120 is used to modulate the converter according to the modulation parameters and a preset modulation strategy, wherein the modulation parameters are set as follows: different duty cycles and different shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated, and at the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequencies of the first half cycle and the second half cycle of each switching cycle are reduced by different ratios.

[0251] According to the modulation system of the converter of the embodiment of the present application, when the modulation input parameters change, there is no transient winding current bias and DC bias magnetism, no transient abnormal pulse voltage and the uncontrollable power caused by it, the power transfer delay is small and the accuracy is high. In addition, the modulation strategy is simple and easy to implement, does not require additional sensor signal feedback and complex control process, the modulation strategy is independent of the transformer inductance parameters, has strong robustness, strong practicality, and high light load efficiency.

[0252] The specific definition of the modulation system of the converter can be found in the above definition of the modulation method of the converter, which will not be repeated here.

[0253] In one embodiment, a computer device is provided. Fig.24 This is a block diagram of the computer device provided in the embodiment of the present application, refer to Fig.24 The computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the modulation method embodiment of the converter is implemented. For example, the following is executed:

[0254] Set modulation parameters;

[0255] Based on the modulation parameters, modulating the converter with a preset modulation strategy;

[0256] Among them, the modulation parameters are set as follows: different duty cycles and different external shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated. At the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half cycle and the second half cycle of each switching cycle is reduced by different ratios.

[0257] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the processor executes the computer program, the modulation method embodiment of the above converter is implemented. For example, executing:

[0258] Set modulation parameters;

[0259] Based on the modulation parameters, modulating the converter with a preset modulation strategy;

[0260] Among them, the modulation parameters are set as follows: different duty cycles and different external shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated. At the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half cycle and the second half cycle of each switching cycle is reduced by different ratios.

[0261] The present application embodiment provides a computer program product, which includes instructions. When the instructions are executed, the method described in the embodiment of the present application is executed. For example, it can be executed Figure 3 The various steps of the modulation method of the converter shown are performed, for example:

[0262] Set modulation parameters;

[0263] Based on the modulation parameters, modulating the converter with a preset modulation strategy;

[0264] Among them, the modulation parameters are set as follows: different duty cycles and different external shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated. At the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half cycle and the second half cycle of each switching cycle is reduced by different ratios.

[0265] Those of ordinary skill in the art can understand that all or part of the processes in the methods for implementing the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0266] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0267] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A modulation method for a converter, characterized in that: The converter includes at least two H-bridges and a multi-winding high-frequency isolation transformer, and the modulation method includes: Set modulation parameters; Based on the modulation parameters, modulating the converter with a preset modulation strategy; Among them, the modulation parameters are set as follows: different duty cycles and different external shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated. At the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequency of the first half cycle and the second half cycle of each switching cycle is reduced by different ratios.

2. The modulation method of the converter according to claim 1, characterized in that: The step of setting the modulation parameters comprises: The modulation parameters are constrained, and when the modulation parameters are constrained, the modulation parameters are calculated according to key input parameters, wherein the constraints on the modulation parameters include: The AC voltage and current of adjacent switching cycles do not overlap in time, and the start or end time point of a half switching cycle is zero voltage; The time integral of the half-switching cycle voltage is the same for all ports; The independent excitation inductor current rise value in the first half cycle is equal to the difference between the expected positive peak value of the independent excitation inductor current and the expected reverse peak value of the independent excitation inductor current in the previous switching cycle; The time during which the independent magnetizing inductor current in a switching cycle maintains the forward peak value is equal to the time during which the reverse peak value is maintained.

3. The modulation method of the converter according to claim 2, characterized in that: The key input parameters include frequency reduction coefficient, global duty cycle coefficient and external shift ratio; The calculating the modulation parameter according to the key input parameter comprises: According to the frequency reduction coefficient, the global duty cycle coefficient and the external shift comparison, the first half cycle duty cycle, the second half cycle duty cycle, the first half cycle external shift comparison, the second half cycle external shift comparison, the first half cycle frequency reduction coefficient and the second half cycle frequency reduction coefficient are obtained.

4. The modulation method of the converter according to claim 3, characterized in that: in, The duty cycle d of the first half of the kth switching cycle j,FH,k is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the k-th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, and the DC voltage of the port with the lowest voltage in the k-th switching cycle; The duty cycle d of the second half of the kth switching cycle j,SH,k It is obtained according to the global duty cycle coefficient of the k-1th switching cycle, the DC voltage of the port j in the kth switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle.

5. The modulation method of the converter according to claim 3, characterized in that: in, The frequency reduction coefficient of the first half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle; The frequency reduction coefficient of the second half of the kth switching cycle is: obtained according to the frequency reduction coefficient of the kth switching cycle, the global duty cycle coefficient of the kth switching cycle, the global duty cycle coefficient of the k-1th switching cycle, the global duty cycle coefficient of the k-2th switching cycle, the DC voltage of port j in the kth switching cycle, the DC voltage of port j in the k+1th switching cycle, the DC voltage of the port with the lowest voltage in the k-1th switching cycle, the DC voltage of the port with the lowest voltage in the k+1th switching cycle, and the DC voltage of the port with the lowest voltage in the kth switching cycle; Before calculating the frequency reduction coefficient of the first half cycle of the kth switching cycle and calculating the frequency reduction coefficient of the second half cycle of the kth switching cycle, an approximate method or a prediction method is used to obtain the DC voltage of the k+1th cycle.

6. The modulation method of the converter according to claim 3, characterized in that: in, The first half of the kth switching cycle is shifted outward compared to D j,FH,k is obtained according to the outward shift ratio of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port 1 of the k-1th switching cycle, the duty cycle of port j of the k-1th switching cycle, and the duty cycle of port j of the k-1th switching cycle; The second half of the kth switching cycle is shifted outward compared to D j,SH,k It is obtained according to the outward shift ratio of the kth switching cycle and the outward shift ratio of the first half cycle of the kth switching cycle.

7. The modulation method of the converter according to any one of claims 1 to 6, characterized in that: The preset modulation strategy is an extended soft switching phase shift modulation strategy.

8. A modulation system for a converter, characterized in that: The converter includes at least two H-bridges and a multi-winding high-frequency isolation transformer, and the modulation system includes: A modulation parameter setting module, used to set modulation parameters; A modulation module is used to modulate the converter according to the modulation parameters and a preset modulation strategy, wherein the modulation parameters are set as follows: different duty cycles and different shift ratios are set for the first half cycle and the second half cycle of each switching cycle when the converter is modulated, and at the end of the first half cycle and the second half cycle of each switching cycle, phase-shifted zero voltage sequences with different duration ratios are added respectively, so that the equivalent switching frequencies of the first half cycle and the second half cycle of each switching cycle are reduced by different ratios.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the modulation method of the converter according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the modulation method of the converter according to any one of claims 1 to 7 is implemented.

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