Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing an initial substrate which comprises a plurality of active regions; the active regions are etched to form a substrate, the substrate comprises channel regions located in the active regions, and each channel region is provided with at least one convex part or at least one concave part or a combination of a plurality of convex parts and a plurality of concave parts; and forming a storage gate structure on the surface of the channel region, wherein the projection of the convex part or the concave part on the surface of the substrate is located in the projection range of the storage gate structure on the surface of the substrate. According to the semiconductor structure and the forming method thereof, the channel length of a flash memory device is increased, and the erasing efficiency of the device is optimized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] NOR Flash is a non-volatile memory commonly used in embedded systems and storage devices. In recent years, with the rapid increase in chip storage and processing performance and cost requirements, the requirements for device integration have become increasingly higher. Therefore, the size of NOR Flash devices has been continuously reduced to meet the growing device performance requirements.

[0003] Among them, due to device miniaturization, the NOR Flash channel length becomes shorter, thus facing the short channel effect and affecting the device performance. In addition, the reduction in the size of the active area also leads to the degradation of the device programming and erasing rate performance, and the device programming-erasing window cannot be maintained. Therefore, the planar structure commonly used in Nor Flash devices is limited by size and process, and cannot meet the high performance requirements of the device while reducing the device size. It has the defects of too short channel length and low erase efficiency. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which increases the channel length of a flash memory device and optimizes the erasing efficiency of the device.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a plurality of active areas, the active areas having a channel area, the channel area having at least one protrusion or at least one recessed portion or a combination of a plurality of protrusions and a plurality of recessed portions; a storage gate structure located on the surface of the channel area, the projection of the protrusion or the recessed portion on the substrate surface is located within the projection range of the storage gate structure on the substrate surface.

[0006] Optionally, it further includes: a source region and a drain region located in the substrate, and the channel region is located between the source region and the drain region.

[0007] Optionally, the corner formed by the top surface and the side wall surface of the protrusion is a rounded corner; the corner formed by the bottom surface and the side wall surface of the recessed portion is a rounded corner.

[0008] Optionally, the active regions are arranged along a first direction, and an extension direction of the active regions is parallel to a second direction, and adjacent active regions are separated from each other.

[0009] Optionally, the number of the protrusions is greater than or equal to 1.

[0010] Optionally, the number of the recessed portions is greater than or equal to one.

[0011] Optionally, the channel region extends along the second direction; when the sum of the number of the protrusions and the recesses is greater than 1, the protrusions and the recesses are distributed along the second direction.

[0012] Optionally, the storage gate structure includes: a floating gate dielectric layer located on the surface of the channel region, a floating gate located on the surface of the floating gate dielectric layer, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer, wherein the width of the control gate is greater than the width of the raised portion or recessed portion of the channel region.

[0013] Optionally, the floating gate includes a first region and a second region located on both sides of the first region, the first region and the second region are arranged along a first direction, and a surface of the first region is lower than a surface of the second region.

[0014] Optionally, a shallow trench isolation structure is located between each active area, and a top surface of the shallow trench isolation structure is lower than, flush with, or higher than a bottom surface of the floating gate.

[0015] Optionally, there are sidewall structures located on the surface of the active region and on the sidewall surfaces of both sides of the storage gate structure, and the channel region is located between the two sidewall structures.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing an initial substrate, the initial substrate comprising a plurality of active areas; etching each active area to form a substrate, the substrate comprising a channel area located in each active area, each of the channel areas having at least one protruding portion or at least one recessed portion or a combination of a plurality of protruding portions and a plurality of recessed portions; forming a storage gate structure on the surface of the channel area, the projection of the protruding portion or the recessed portion on the substrate surface being located within the projection range of the storage gate structure on the substrate surface.

[0017] Optionally, the method for forming each channel region includes: forming a first mask layer on the surface of the initial substrate, the first mask layer exposing a portion of the active region; using the first mask layer as a mask, etching the active region to form a recessed portion or a raised portion, thereby forming a channel region in each active region.

[0018] Optionally, after forming the recessed portion or the raised portion, the method further includes: performing surface treatment on the channel region to round the corner formed by the top surface and the side wall surface of the raised portion, or to round the corner formed by the bottom surface and the side wall surface of the recessed portion.

[0019] Optionally, the surface treatment is isotropic dry etching or wet etching; the process parameters of the surface treatment include: the etching solution used includes a hydrofluoric acid solution; the concentration range of the hydrofluoric acid solution is 1:1000 to 1:100.

[0020] Optionally, the active regions are arranged along a first direction, and an extension direction of the active regions is parallel to a second direction, and adjacent active regions are separated from each other.

[0021] Optionally, the storage gate structure includes: a floating gate dielectric layer located on the surface of the channel region, a floating gate located on the surface of the floating gate dielectric layer, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer, wherein the width of the control gate is greater than the width of the raised portion or recessed portion of the channel region.

[0022] Optionally, the floating gate includes a first region and a second region located on both sides of the first region, the first region and the second region are arranged along a first direction, and a surface of the first region is lower than a surface of the second region.

[0023] Optionally, the method for forming the storage gate structure includes: forming a floating gate dielectric material layer on the surface of the active area; forming a floating gate material layer on the surface of the floating gate dielectric material layer; forming a control gate dielectric material layer on the surface of the floating gate material layer; forming a control gate material layer on the surface of the control gate dielectric material layer; and patterning the control gate material layer, the control gate dielectric material layer, the floating gate material layer and the floating gate dielectric material layer to form a storage gate structure.

[0024] Optionally, after forming the channel region and before forming the floating gate material layer, it also includes: forming an isolation structure between the active regions, the top surface of the isolation structure being higher than the top surface of the channel region; the floating gate material layer is formed on the surface of the floating gate dielectric material layer on the active region and the side wall surface of the isolation structure.

[0025] Optionally, after forming the floating gate material layer, the isolation structure is highly thinned to form a shallow trench isolation structure, wherein the top surface of the shallow trench isolation structure is lower than, flush with, or higher than the bottom surface of the floating gate material layer.

[0026] Optionally, the floating gate material layer is formed by a process including a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or a jet vapor deposition process.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the semiconductor structure provided by the technical solution of the present invention, the active region has a channel region, the channel region has at least one protrusion or at least one depression or a combination of several protrusions and several depressions, and the projection of the protrusion or depression on the substrate surface is located within the projection range of the storage gate structure on the substrate surface, therefore, compared with the device structure of the planar channel, the effective area of ​​the channel region is increased, the effective length of the channel is increased, and the short channel effect is suppressed. In addition, due to the presence of the protrusion or depression, the capacitance area formed by the storage gate structure and the channel region is larger, the coupling coefficient is increased, and the erasing efficiency of the device is optimized.

[0029] Furthermore, the corner formed by the top surface and the side wall surface of the protrusion is a rounded corner; the corner formed by the bottom surface and the side wall surface of the recessed portion is a rounded corner. The rounded corner avoids the appearance of a sharp-angle structure, thereby making the morphology of the subsequent floating gate dielectric layer and floating gate more uniform, reducing structural defects and enhancing the stability of device performance.

[0030] Furthermore, the floating gate includes a first region and a second region located on both sides of the first region, the first region and the second region are arranged along a first direction, and the surface of the first region is lower than the surface of the second region, so that the surface of the first region in the floating gate and the sidewall of the second region form a groove, and then the control gate dielectric layer and the control gate are also located in the groove. The existence of the height difference between the first region and the second region surface can increase the effective size of the floating gate and the control gate, and increase the relative area of ​​the floating gate, the control gate dielectric layer and the control gate, thereby increasing the capacitance formed by the floating gate, the control gate dielectric layer and the control gate, and optimizing the erasing performance of the device.

[0031] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since a channel region is formed in the device region, the channel region has at least one protrusion or at least one depression or a combination of several protrusions and several depressions, and the projection of the protrusion or depression on the substrate surface is located within the projection range of the storage gate structure on the substrate surface, therefore, compared with the device structure of the planar channel, the effective area of ​​the channel region is increased, the effective length of the channel is increased, and the short channel effect is suppressed. In addition, due to the presence of the protrusion or depression, the capacitance area formed by the storage gate structure and the channel region is larger, the coupling coefficient is increased, and the erasing efficiency of the device is optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 18 It is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background technology, as the size of flash memory devices continues to shrink, the channel length of the device continues to shorten, causing the device to face the short channel effect and affect performance. In addition, the reduction in the size of the active area of ​​the device also leads to the degradation of the device programming and erasing rate performance, and the device programming-erasing window cannot be maintained. Therefore, the planar structure commonly used in Nor Flash devices is limited by size and process, and cannot meet the high performance requirements of the device while reducing the size of the device, and has the defects of too short channel length and low erasing efficiency.

[0034] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein a channel region is formed in the device region, the channel region has at least one protrusion or at least one depression or a combination of several protrusions and several depressions, and the projection of the protrusion or depression on the substrate surface is located within the projection range of the storage gate structure on the substrate surface. Therefore, compared with the device structure of the planar channel, the effective area of ​​the channel region is increased, the effective length of the channel is increased, and the short channel effect is suppressed. In addition, due to the presence of the protrusion or depression, the capacitance area formed by the storage gate structure and the channel region is larger, the coupling coefficient is increased, and the erasing efficiency of the device is optimized.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 18 It is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 Top view along the P direction, Figure 2 yes Figure 1 A schematic cross-sectional view along the AA′ direction shows an initial substrate 100 . The initial substrate 100 includes a plurality of active regions I and an isolation region II between adjacent active regions I.

[0038] The material of the initial substrate 100 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc. Specifically, in this embodiment, the material of the initial substrate 100 is silicon.

[0039] In this embodiment, the active regions I are arranged along the first direction X, and the extension direction of the active regions I is parallel to the second direction Y, and adjacent active regions I are separated from each other.

[0040] Next, a first sacrificial oxide layer (not shown) is formed on the surface of the initial substrate 100 ; and a source region (not shown) and a drain region (not shown) are formed in the active region I.

[0041] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Top view along the P direction, Figure 4 yes Figure 3 In the cross-sectional view along the AA′ direction, the first sacrificial oxide layer is removed; each active region I is etched to form a substrate 101 , wherein the substrate 101 includes a channel region M located in each active region I, and each channel region M has a protrusion 120 .

[0042] In this embodiment, the channel region M is located between the source region and the drain region. The source region, the drain region and the channel region M are arranged along the second direction Y.

[0043] Among them, when the device is working, the device voltage can be controlled to turn on the channel region M to conduct the source region and the drain region. Since the channel region M has a protrusion 120, compared with the device structure of the planar channel, the effective area of ​​the surface of the channel region M is increased, and the effective length of the channel is increased; especially for small-sized devices, the short channel effect is suppressed.

[0044] In addition, due to the presence of the protruding portion 120, the capacitance area formed by the subsequently formed floating gate dielectric layer, the floating gate and the channel region M is larger, and the floating gate coupling coefficient is increased, thereby optimizing the erasing efficiency of the device.

[0045] In this embodiment, the method for forming each channel region M includes: forming a first mask layer (not shown) on the surface of the initial substrate 100, wherein the first mask layer exposes a portion of the active region I; using the first mask layer as a mask, etching the active region I to form a protrusion 120, thereby forming a channel region M in each active region I.

[0046] In this embodiment, after the protrusion 120 is formed, the channel region M is further subjected to surface treatment, so that the corner formed by the top surface and the side wall surface of the protrusion 120 is rounded, and the corner formed by the surface of the active region I outside the channel region M and the side wall surface of the protrusion 120 is also rounded (e.g. Figure 4 C and D in the figure).

[0047] Since the corner is rounded, the appearance of a sharp-angle structure is avoided, so that the morphology of the subsequent floating gate dielectric layer and the floating gate is more uniform, structural defects are reduced, and the stability of device performance is enhanced.

[0048] Specifically, the surface treatment is isotropic dry etching or wet etching; the process parameters of the surface treatment include: the etching solution used includes a hydrofluoric acid solution; the concentration range of the hydrofluoric acid solution is 1:1000 to 1:100. Hydrofluoric acid pickling can remove oxides on the surface of the substrate, which is conducive to exposing the substrate, intensifying the reaction, and thus forming rounded corners.

[0049] In this embodiment, the channel region M includes one protrusion 120 .

[0050] In another embodiment, each active region of the initial substrate is etched to form a substrate, wherein the substrate includes a channel region located in each active region, each channel region has a recessed portion therein, and the recessed portion is recessed downward relative to the top surface of the substrate.

[0051] After the recess is formed, the channel region is surface treated to round the corner formed by the bottom surface and the sidewall surface of the recess, thereby making the morphology of the subsequent floating gate dielectric layer and floating gate more uniform.

[0052] In other embodiments, the substrate is formed by etching each active region of the initial substrate, the substrate includes a channel region located in each active region, each of the channel regions has at least one protrusion or at least one depression or a combination of several protrusions and several depressions. Compared with the device structure of the planar channel, the presence of the protrusion or depression increases the effective area of ​​the channel region surface, increases the effective length of the channel, and suppresses the short channel effect; in addition, it is also beneficial to increase the floating gate coupling coefficient of the device, thereby optimizing the erasing efficiency of the device.

[0053] After forming the protrusion or the depression, the channel region is surface treated to round the corner formed by the top surface and the side wall surface of the protrusion or to round the corner formed by the bottom surface and the side wall surface of the depression.

[0054] Please refer to Figures 5 to 7 ,in, Figure 5 for Figure 6 Top view along the P direction, Figure 5 Too Figure 7 Top view along the Q direction, Figure 6 for Figure 5 Schematic diagram of the cross section along the AA' direction, Figure 7 for Figure 5 Schematic diagram of the cross section along the BB' direction.

[0055] A second sacrificial oxide layer 111 is formed on the surface of the substrate 101 ; the second sacrificial oxide layer 111 on the surface of the isolation region II and the isolation region II are etched to form an isolation trench 121 in the isolation region II.

[0056] Specifically, the method for forming the isolation trench 121 includes: forming a second mask layer 110 on the surface of the second sacrificial oxide layer 111, the second mask layer 110 exposing the second sacrificial oxide layer 111 on the surface of the isolation region II; using the second mask layer 110 as a mask, etching the second sacrificial oxide layer 111 and the isolation region II to form the isolation trench 121.

[0057] Please refer to Figure 8 and Fig. 9 ,in, Figure 8 and Figure 6 The viewing direction is consistent with Fig. 9 and Figure 7 The viewing direction is consistent.

[0058] An isolation material layer (not shown) is filled in the isolation trench 121 ; the isolation material layer is planarized to form an isolation structure 123 , and the isolation structure 123 is located between the active regions I.

[0059] Wherein, while the isolation material layer is planarized, the height of the second mask layer 110 is also thinned.

[0060] Please refer to Fig.10 and Fig.11 ,in, Fig.10 and Figure 8 The viewing direction is consistent with Fig.11 and Fig. 9 The second mask layer 110 is removed; and the second sacrificial oxide layer 111 is removed.

[0061] After the second sacrificial oxide layer 111 is removed, the surface of the active region I, the top of the isolation structure 123 and a portion of the sidewall surface are exposed.

[0062] The top of the isolation structure 123 is higher than the surface of the substrate 101 .

[0063] Next, a storage gate structure is formed on the surface of the channel region M, and the projection of the protrusion 120 or the recess on the surface of the substrate 101 is located within the projection range of the storage gate structure on the surface of the substrate 101. Specifically, the storage gate structure includes: a floating gate dielectric layer located on the surface of the channel region M, a floating gate located on the surface of the floating gate dielectric layer, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer, and the width of the control gate is greater than the width of the protrusion 120 or the recess in the channel region M.

[0064] Please refer to Fig.12 , a floating gate dielectric material layer 125 is formed on the surface of the active area I.

[0065] In this embodiment, the floating gate dielectric material layer 125 is located on the surface of the raised portion 120 of the channel region M and the surface of other active regions I. Since the corner formed by the top surface and the sidewall surface of the raised portion 120 is a rounded corner, the floating gate dielectric material layer 125 is deposited uniformly on the surface of the raised portion 120 as a whole, with fewer defects.

[0066] The top surface of the isolation structure 123 is higher than the surface of the floating gate dielectric material layer 125 .

[0067] In this embodiment, the floating gate dielectric material layer 125 includes silicon oxide, nitrogen-doped silicon oxide, silicon nitride, silicon oxynitride and other high dielectric constant dielectric materials, including aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide.

[0068] In this embodiment, the formation process of the floating gate dielectric material layer 125 includes a thermal oxidation process, a rapid thermal annealing process, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or a jet vapor deposition process.

[0069] Please refer to Fig.14 and Fig.15 ,in, Fig.14 and Fig.12 The viewing direction is consistent with Fig.15 and Fig.13 The viewing direction is consistent.

[0070] In this embodiment, a floating gate material layer 130 is formed on the surface of the floating gate dielectric material layer 125 and the sidewall surface of the isolation structure 123 .

[0071] The floating gate material layer 130 is partially filled between adjacent isolation structures 123, and the top of the isolation structure 123 is higher than the floating gate dielectric material layer 125, so that the floating gate material layer 130 between the isolation structures 123 is "U"-shaped, and there is a groove 124 in the floating gate material layer 130. Since the floating gate material layer 130 is partially filled between adjacent isolation structures 123, the presence of the groove 124 in the floating gate material layer 130 increases the surface area of ​​the subsequent floating gate and the effective size of the floating gate, thereby optimizing the erasing performance of the device.

[0072] In this embodiment, the material of the floating gate material layer 130 includes silicon-based materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, and other high-dielectric-constant metal gate materials, such as hafnium oxide, iridium oxide, and ruthenium oxide.

[0073] In this embodiment, the formation process of the floating gate material layer 130 includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and a jet vapor deposition process.

[0074] In this embodiment, the portion of the top of the isolation structure 123 that is higher than the surface of the substrate 101 controls the height of the floating gate material layer 130 .

[0075] In this embodiment, after the floating gate material layer 130 is deposited, the floating gate material layer 130 is planarized until the surface of the isolation structure 123 is exposed.

[0076] In another embodiment, the floating gate material layer completely fills between adjacent isolation structures, the floating gate material layer is a solid structure without grooves therein, and the top surface of the floating gate material layer is flush with the top surface of the isolation structure.

[0077] In other embodiments, the floating gate material layer is a solid structure without a groove inside. The isolation structure is flush with the surface of the floating gate dielectric material layer, and the floating gate material layer is formed on the floating gate dielectric material layer and the top surface of the isolation structure.

[0078] Please refer to Fig.16 and Fig.17 , the isolation structure 123 is highly thinned to form a shallow trench isolation structure 135; a control gate dielectric material layer 131 is formed on the surface of the floating gate material layer 130 and the shallow trench isolation structure 135; and a control gate material layer 140 is formed on the surface of the control gate dielectric material layer 131.

[0079] In this embodiment, the top surface of the shallow trench isolation structure 135 is flush with the bottom surface of the floating gate material layer 130 .

[0080] In other embodiments, the top surface of the shallow trench isolation structure may be higher or lower than the bottom surface of the floating gate material layer, and the height of the shallow trench isolation structure may be designed according to actual device requirements.

[0081] In this embodiment, the control gate dielectric material layer 131 and the control gate material layer 140 are deposited along the surface of the floating gate material layer 130, so the bottom surface of the control gate dielectric material layer 131 and the control gate material layer 140 retains the shape of the surface of the floating gate material layer 130. The control gate dielectric material layer 131 and the control gate material layer 140 fill the groove 124 in the floating gate material layer 130. The control gate dielectric material layer 131 and the control gate material layer 140 are also located on the top surface of the shallow trench isolation structure 135.

[0082] In this embodiment, the material of the shallow trench isolation structure 135 includes silicon oxide, other oxides, or a mixture of oxides and other compounds.

[0083] Please continue to refer to Fig.17 , and combined with Fig.17 refer to Fig.18 ,in, Fig.18 and Fig.16 The control gate material layer 140 , the control gate dielectric material layer 131 , the floating gate material layer 130 and the floating gate dielectric material layer 125 are patterned to form a storage gate structure 150 .

[0084] The memory gate structure 150 includes: a floating gate dielectric layer 144 located on the surface of the channel region M, a floating gate 143 located on the surface of the floating gate dielectric layer 144, a control gate dielectric layer 142 located on the surface of the floating gate 143, and a control gate 141 located on the surface of the control gate dielectric layer 142. The width D2 of the control gate 141 is greater than the width D1 of the protruding portion 120 of the channel region M, that is, the width D2 of the memory gate structure 150 is greater than the width D1 of the protruding portion 120 of the channel region M. The floating gate dielectric layer 144 is formed by patterning the floating gate dielectric material layer 125, the floating gate 143 is formed by patterning the control gate dielectric material layer 131, and the control gate 141 is formed by patterning the control gate material layer 140.

[0085] In this embodiment, since the width D2 of the control gate 141 is greater than the width D1 of the protrusion 120 of the channel region M, the projection of the protrusion 120 on the surface of the substrate 101 is located within the projection range of the storage gate structure 150 on the surface of the substrate 101. Therefore, compared with the device structure of the planar channel, the effective area of ​​the channel region M in this embodiment is larger, the effective length of the channel is increased, and the short channel effect is suppressed. In addition, due to the existence of the protrusion 120, the capacitor area formed by the floating gate 143, the floating gate dielectric layer 144 and the channel region M is larger, the coupling coefficient is increased, and the erasing efficiency of the device is optimized.

[0086] In another embodiment, each of the channel regions includes a recessed portion, and the width of the control gate is greater than the width of the recessed portion of the channel region. The presence of the recessed portion also increases the effective length of the channel, suppresses the short channel effect, and optimizes the erasing efficiency of the device.

[0087] In other embodiments, each of the channel regions has at least one protrusion or at least one depression or a combination of several protrusions and several depressions. The more the protrusions or depressions, the larger the effective area of ​​the channel region, the longer the effective length of the channel, and thus the short channel effect can be better suppressed. In addition, the capacitance area formed by the floating gate, the floating gate dielectric layer, and the channel region is made larger, and the coupling coefficient is better increased, thereby optimizing the erasing efficiency of the device.

[0088] Specifically, in some embodiments, the number of the protrusions is greater than or equal to 1. In some embodiments, the number of the recesses is greater than or equal to 1.

[0089] Wherein, the channel region extends along the second direction; when the sum of the number of the protrusions and the recesses is greater than 1, the protrusions and the recesses are distributed along the second direction.

[0090] In this embodiment, the floating gate 143 includes a first region 130a and a second region 130b located on both sides of the first region 130a. The first region 130a and the second region 130b are arranged along the first direction X. The surface of the first region 130a is lower than the surface of the second region 130b, so that the surface of the first region 130a in the floating gate 143 and the sidewall of the second region 130b form a groove (not shown), and then, the control gate dielectric layer 142 and the control gate 141 are still located in the groove. The existence of the height difference between the first region 130a and the second region 130b can increase the effective size of the floating gate 143 and the control gate 141, and increase the relative area of ​​the floating gate 143, the control gate dielectric layer 142 and the control gate 141, thereby increasing the capacitance formed by the floating gate 143, the control gate dielectric layer 142 and the control gate 141, and optimizing the erase performance of the device.

[0091] Next, a spacer structure 151 is formed on the surface of the active region I and the sidewall surfaces of both sides of the storage gate structure 150 , and the channel region M is located between the two spacer structures 151 .

[0092] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by adopting the above method.

[0093] Please continue to refer to Fig.17 and Fig.18 The semiconductor structure includes: a substrate 101, wherein the substrate 101 includes a plurality of active regions I, wherein the active regions I have channel regions M, wherein the channel regions M have a protrusion 120; a storage gate structure 150 located on the surface of the channel region M, wherein the projection of the protrusion 120 on the surface of the substrate 101 is located within the projection range of the storage gate structure 150 on the surface of the substrate 101.

[0094] In this embodiment, the active regions I are arranged along the first direction X, and the extension direction of the active regions I is parallel to the second direction Y, and adjacent active regions I are separated from each other.

[0095] In this embodiment, the semiconductor structure further includes: a source region and a drain region located in the substrate 101, and the channel region M is located between the source region and the drain region.

[0096] In this embodiment, the storage gate structure 150 includes: a floating gate dielectric layer 144 located on the surface of the channel region M, a floating gate 143 located on the surface of the floating gate dielectric layer 144, a control gate dielectric layer 142 located on the surface of the floating gate 143, and a control gate 141 located on the surface of the control gate dielectric layer 142, and the width D2 of the control gate 141 is greater than the width D1 of the protrusion 120 of the channel region M.

[0097] In this embodiment, since the width D2 of the control gate 141 is greater than the width D1 of the protrusion 120 of the channel region M, the projection of the protrusion 120 on the surface of the substrate 101 is located within the projection range of the storage gate structure 150 on the surface of the substrate 101. Therefore, compared with the device structure of the planar channel, the effective area of ​​the channel region M in this embodiment is larger, the effective length of the channel is increased, and the short channel effect is suppressed. In addition, due to the existence of the protrusion 120, the capacitor area formed by the floating gate 143, the floating gate dielectric layer 144 and the channel region M is larger, the coupling coefficient is increased, and the erasing efficiency of the device is optimized.

[0098] In another embodiment, each of the channel regions includes a recessed portion, and the width of the control gate is greater than the width of the recessed portion of the channel region, so that the projection of the recessed portion on the substrate surface is located within the projection range of the storage gate structure on the substrate surface. The presence of the recessed portion also increases the effective length of the channel, suppresses the short channel effect, and optimizes the erasing efficiency of the device.

[0099] In other embodiments, each of the channel regions has at least one protrusion or at least one depression or a combination of several protrusions and several depressions. The more the protrusions or depressions, the larger the effective area of ​​the channel region, the longer the effective length of the channel, and thus the short channel effect can be better suppressed. In addition, the capacitance area formed by the floating gate, the floating gate dielectric layer, and the channel region is made larger, and the coupling coefficient is better increased, thereby optimizing the erasing efficiency of the device.

[0100] Specifically, in some embodiments, the number of the protrusions is greater than or equal to 1. In some embodiments, the number of the recesses is greater than or equal to 1.

[0101] Wherein, the channel region extends along the second direction; when the sum of the number of the protrusions and the recesses is greater than 1, the protrusions and the recesses are distributed along the second direction.

[0102] In this embodiment, the corners formed by the top surface and the side wall surface of the protrusion 120 are rounded, which avoids the appearance of sharp-angle structures, thereby making the morphology of the subsequent floating gate dielectric layer 144 and the floating gate 143 more uniform, reducing structural defects and enhancing the stability of device performance.

[0103] In another embodiment, each of the channel regions includes a recessed portion, and a corner formed by a bottom surface and a sidewall surface of the recessed portion is a rounded corner.

[0104] In this embodiment, the floating gate 143 includes a first region 130a and a second region 130b located on both sides of the first region 130a. The first region 130a and the second region 130b are arranged along the first direction X. The surface of the first region 130a is lower than the surface of the second region 130b, so that the surface of the first region 130a in the floating gate 143 and the sidewall of the second region 130b form a groove (not shown), and then, the control gate dielectric layer 142 and the control gate 141 are still located in the groove. The existence of the height difference between the first region 130a and the second region 130b can increase the effective size of the floating gate 143 and the control gate 141, and increase the relative area of ​​the floating gate 143, the control gate dielectric layer 142 and the control gate 141, thereby increasing the capacitance formed by the floating gate 143, the control gate dielectric layer 142 and the control gate 141, and optimizing the erase performance of the device.

[0105] In this embodiment, the semiconductor structure further includes: a shallow trench isolation structure 135 located between the active regions I, and a top surface of the shallow trench isolation structure 135 is lower than, flush with, or higher than a bottom surface of the floating gate 143 .

[0106] In this embodiment, the semiconductor structure further includes: a spacer structure 151 located on the surface of the active region I and the sidewall surfaces of both sides of the storage gate structure 150 , and the channel region M is located between the two spacer structures 151 .

[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate comprises a plurality of active regions, wherein the active regions have a channel region, and wherein the channel region has at least one protrusion or at least one depression or a combination of a plurality of protrusions and a plurality of depressions; The storage gate structure is located on the surface of the channel region, and the projection of the protrusion or the depression on the substrate surface is located within the projection range of the storage gate structure on the substrate surface.

2. The semiconductor structure according to claim 1, wherein: Also includes: A source region and a drain region are located in the substrate, and the channel region is located between the source region and the drain region.

3. The semiconductor structure according to claim 1, wherein: The corner formed by the top surface and the side wall surface of the protrusion is a rounded corner; the corner formed by the bottom surface and the side wall surface of the recessed portion is a rounded corner.

4. The semiconductor structure according to claim 1, wherein: The active regions are arranged along a first direction, and an extending direction of the active regions is parallel to a second direction, and adjacent active regions are separated from each other.

5. The semiconductor structure according to claim 1, wherein: The number of the protrusions is greater than or equal to one.

6. The semiconductor structure according to claim 1, wherein: The number of the recessed portions is greater than or equal to one.

7. The semiconductor structure according to claim 4, wherein: The channel region extends along the second direction; when the sum of the number of the protrusions and the recesses is greater than 1, the protrusions and the recesses are distributed along the second direction.

8. The semiconductor structure according to claim 4, wherein: The storage gate structure includes: a floating gate dielectric layer located on the surface of the channel region, a floating gate located on the surface of the floating gate dielectric layer, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer, wherein the width of the control gate is greater than the width of the raised portion or recessed portion of the channel region.

9. The semiconductor structure according to claim 8, characterized in that The floating gate includes a first region and second regions located on both sides of the first region. The first region and the second region are arranged along a first direction, and a surface of the first region is lower than a surface of the second region.

10. The semiconductor structure according to claim 8, wherein: A shallow trench isolation structure is located between each active area, wherein the top surface of the shallow trench isolation structure is lower than, flush with or higher than the bottom surface of the floating gate.

11. The semiconductor structure according to claim 1, wherein: A sidewall structure is located on the surface of the active area and the sidewall surfaces of both sides of the storage gate structure, and the channel area is located between the two sidewall structures.

12. A method for forming a semiconductor structure, characterized in that: include: Providing an initial substrate, wherein the initial substrate includes a plurality of active regions; Etching each active area to form a substrate, wherein the substrate includes a channel area located in each active area, and each channel area has at least one protrusion or at least one depression or a combination of several protrusions and several depressions; A storage gate structure is formed on the surface of the channel region, and the projection of the protrusion or the depression on the substrate surface is located within the projection range of the storage gate structure on the substrate surface.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming each channel region includes: forming a first mask layer on the surface of the initial substrate, wherein the first mask layer exposes a portion of the active region; using the first mask layer as a mask, etching the active region to form a recessed portion or a raised portion, thereby forming a channel region in each active region.

14. The method for forming a semiconductor structure according to claim 12, wherein: After forming the recessed portion or the raised portion, the method further includes: performing surface treatment on the channel region to round the corner formed by the top surface and the side wall surface of the raised portion, or to round the corner formed by the bottom surface and the side wall surface of the recessed portion.

15. The method for forming a semiconductor structure according to claim 14, wherein: The surface treatment is isotropic dry etching or wet etching; the process parameters of the surface treatment include: the etching solution used includes a hydrofluoric acid solution; the concentration range of the hydrofluoric acid solution is 1:1000 to 1:

100.

16. The method for forming a semiconductor structure according to claim 12, wherein: The active regions are arranged along a first direction, and an extending direction of the active regions is parallel to a second direction, and adjacent active regions are separated from each other.

17. The method for forming a semiconductor structure according to claim 16, wherein: The storage gate structure includes: a floating gate dielectric layer located on the surface of the channel region, a floating gate located on the surface of the floating gate dielectric layer, a control gate dielectric layer located on the surface of the floating gate, and a control gate located on the surface of the control gate dielectric layer, wherein the width of the control gate is greater than the width of the raised portion or recessed portion of the channel region.

18. The method for forming a semiconductor structure according to claim 17, wherein: The floating gate includes a first region and second regions located on both sides of the first region. The first region and the second region are arranged along a first direction, and a surface of the first region is lower than a surface of the second region.

19. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the storage gate structure includes: forming a floating gate dielectric material layer on the surface of the active area; forming a floating gate material layer on the surface of the floating gate dielectric material layer; forming a control gate dielectric material layer on the surface of the floating gate material layer; forming a control gate material layer on the surface of the control gate dielectric material layer; and patterning the control gate material layer, the control gate dielectric material layer, the floating gate material layer and the floating gate dielectric material layer to form a storage gate structure.

20. The method for forming a semiconductor structure according to claim 19, wherein: After forming the channel region and before forming the floating gate material layer, it also includes: forming an isolation structure between the active regions, the top surface of the isolation structure is higher than the top surface of the channel region; the floating gate material layer is formed on the surface of the floating gate dielectric material layer on the active region and the side wall surface of the isolation structure.

21. The method for forming a semiconductor structure according to claim 20, wherein: After forming the floating gate material layer, the isolation structure is thinned to form a shallow trench isolation structure, wherein the top surface of the shallow trench isolation structure is lower than, flush with, or higher than the bottom surface of the floating gate material layer.

22. The method for forming a semiconductor structure according to claim 20, wherein: The formation process of the floating gate material layer includes: chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or jet vapor deposition process.

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