System and method for testing comprehensive aging stress of GaN power device

Abstract

The invention discloses a comprehensive aging stress test system and method for a GaN power device, and aims to meet various test requirements of the GaN power device on one platform. The system comprises an upper computer module, a central control system, a main circuit module, a power supply module, an oscilloscope, a temperature control module and a tested device slot. The central control system stores a plurality of test programs, such as high-temperature reverse bias, high-temperature gate bias and a power cycle mode. The upper computer module communicates with the central control system through an I / O interface and sends a control command. And after receiving the command, the central control system controls the temperature control module, the power supply module and the main circuit module. The power supply module is connected with the main circuit module, the main circuit module is connected with the oscilloscope, the temperature control module is connected with the tested device slot, and the tested device slot is connected with the main circuit module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and more specifically, to a GaN power device comprehensive aging stress testing system and testing method. Background Art

[0002] In the field of practical applications, the performance of traditional silicon-based power semiconductor devices has reached its limit and cannot further adapt to the new requirements of industrial development. Therefore, it is crucial to promote gallium nitride (GaN) power devices because they have high frequency, high efficiency, high power density, and good high temperature resistance and radiation resistance. However, as an emerging power device, the production process of GaN is not mature enough, its failure mode and mechanism have not been fully clarified, and there is a lack of reliability models. Therefore, it is particularly important to conduct a series of reliability tests on it, such as the currently representative high-temperature reverse bias test, high-temperature gate bias test, and power cycle test. However, these reliability test items are often implemented on different independent devices, which may introduce some additional variables to cause errors in the experiment and increase the amount of experiments. In addition, in such high-temperature tests, online monitoring of thermal parameters such as the junction temperature of the device under test is also particularly critical. In addition, GaN power devices also face the challenge of dynamic on-resistance characteristics, and most devices cannot perform online testing of such dynamic parameters. These problems have seriously restricted the widespread application of GaN power devices.

[0003] The Chinese invention application with application number 201510715870.1 discloses the "High-temperature reverse bias and high-temperature gate bias test system for power devices". The system consists of four parts: a microcomputer control system, a voltage bias system, a device heating system, and a data acquisition system. Depending on the terminals of the device under test, the device under test can be subjected to high-temperature reverse bias test or high-temperature gate bias test, and the leakage current data of the power device under test can be collected in real time during the test. The failure time of high-temperature reverse bias and high-temperature gate bias can be recorded according to the pre-set failure standard. Its technical solution does not realize the comprehensive aging stress test of GaN power devices. Summary of the invention

[0004] The purpose of the present invention is to provide a comprehensive aging stress test system and test method for GaN power devices, which can meet the diversified test requirements of different GaN power devices by flexibly adjusting the operating environment temperature, load current / voltage, device conduction time and gate drive conditions on a platform.

[0005] To achieve the above object, the technical solution adopted by the present invention includes:

[0006] A first aspect of the present invention provides a GaN power device comprehensive aging stress test system, the system comprising a host computer module, a central control system, a main circuit module, a power module, an oscilloscope, a temperature control module and a device under test slot, wherein the central control system stores a high temperature reverse bias mode program, a high temperature gate bias mode program, and a power cycle mode program;

[0007] The host computer module is connected to the central control system through an I / O interface; the host computer module is used to send control commands to the central control system;

[0008] The central control system is respectively connected to the main circuit module, the power module and the temperature control module in communication; the central control system is used to receive commands from the host computer to control the temperature control module, the power module and the main circuit module;

[0009] The power supply module is connected to the main circuit module;

[0010] The main circuit module is connected to the oscilloscope;

[0011] The temperature control module is connected to the device under test slot;

[0012] The device under test slot is connected to the main circuit module.

[0013] As a preferred solution, the host computer module is composed of a program based on a computer.

[0014] As a preferred solution, the central control system includes a digital signal processor chip and an auxiliary circuit, wherein the digital signal processor chip stores a high-temperature reverse bias mode program, a high-temperature gate bias mode program, and a power cycle mode program; the digital signal processor chip is connected to the auxiliary circuit via a detachable pin header.

[0015] As a preferred solution, the main circuit module includes a PCB board and a power transformer circuit, a signal conditioning circuit, a power circuit, a clamping circuit, a MOS switch circuit, an ADC circuit, a gate drive circuit, an off-state stress time control circuit, a high-voltage power supply circuit, an auxiliary power supply circuit, and a DC / DC step-down voltage stabilization circuit arranged on the PCB board.

[0016] As a preferred solution, the temperature control module includes an industrial liquid cooler, a water pump solenoid valve and a water pipeline; the device under test slot includes a heat conductive sheet; the temperature control module is connected to the heat conductive sheet through a water pump solenoid valve and a water pipeline.

[0017] As a preferred solution, the heat conducting sheet is provided with a groove, a thermocouple is provided in the groove, and the thermocouple is connected to the ADC circuit and the signal conditioning circuit.

[0018] As a preferred solution, the oscilloscope includes a differential probe and a ground probe; the differential probe and the ground probe are used to be externally connected to the clamp circuit, the power circuit, and the device under test slot respectively to monitor the IV waveform of the device under test.

[0019] A second aspect of the present invention provides a junction-to-shell thermal resistance test method, which is implemented based on the aforementioned GaN power device comprehensive aging stress test system, and comprises:

[0020] A1: Solder the GaN chip sample to the Al substrate, and lead out three pins in the order of gate, drain, and source to connect to the device under test slot of the aging stress test system;

[0021] A2: Test the relationship between drain-source on-state voltage drop and junction temperature at different temperature points to obtain the junction temperature calibration curve;

[0022] A3: Burn the linear function corresponding to the junction temperature calibration curve into the digital signal processor chip;

[0023] A4: Set the gate drive voltage value of the device under test through the DC / DC step-down voltage regulator circuit on the main circuit, select the power cycle mode and set the test parameters in this mode; install the device under test into the device under test slot;

[0024] A5: The host computer module sends the test parameters and the instruction to start aging to the digital signal processor chip. The central control system first opens the power cycle mode channel, and inputs the timing of the water pump solenoid valve, the gate drive circuit, and the aging current power circuit into the main circuit module in sequence. The main circuit module then inputs the processed signal into the device under test, and opens the gate channel, the water pump solenoid valve channel, and the load current channel at the same time, so that the device starts to heat up under the condition of load current stress, and then closes all channels to enter the cooling stage. After the temperature drops to the preset temperature, it starts to heat up again and enters the next power cycle.

[0025] A7: The digital signal processor chip opens the test current channel and injects a 200mA test current into the device under test to obtain the voltage drop across the drain and source of the device under test. The analog signal then passes through the sampling circuit, ADC conversion circuit, and signal conditioning circuit in the main circuit and enters the digital signal processor chip to infer the real-time junction temperature of the device under test according to the preset junction temperature calibration curve. Finally, the data is sent to the host computer module through the communication serial port, and the host computer module draws a real-time junction temperature curve.

[0026] A8: The shell temperature of the device under test is collected through a thermocouple buried in the groove between the device under test and the heat conducting sheet of the device under test slot through thermal conductive silicone grease. The collected electrical signal enters the digital signal processor chip for processing through the ADC sampling circuit and conditioning circuit and is fed back to the host computer module for shell temperature chart drawing, thereby achieving the purpose of online monitoring;

[0027] A9: By obtaining the real-time junction temperature and case temperature, through R TH =(Tj-Tc) / P load calculation formula to obtain real-time thermal resistance, and feed the data back to the host computer module, through which the host computer module draws charts to achieve online monitoring of the junction-to-case thermal resistance of the device under test.

[0028] A third aspect of the present invention provides a leakage current testing method, which is implemented based on the aforementioned GaN power device comprehensive aging stress testing system, and the leakage current testing method includes:

[0029] B1: Place the DUT into the DUT slot and apply thermal grease evenly on the contact surface;

[0030] B2: Set the temperature and gate-source voltage bias or drain-source voltage bias in the host computer module, and select high-temperature gate bias or high-temperature reverse bias mode for testing;

[0031] B3: After the test starts, the host computer module sends instructions to the digital signal processor chip, and then the digital signal processor chip opens the water pump solenoid valve, and the industrial liquid cooler heats the coolant until the temperature reaches the preset value. The digital signal processor chip then opens the gate-source channel or drain-source channel to apply high-temperature gate bias or high-temperature reverse bias voltage stress to the device under test;

[0032] B4: During the aging process, the digital signal processor chip opens the test voltage channel and inputs the test voltage to the gate-source or drain-source of the device under test. The leakage current obtained is processed into a digital signal by the sampling circuit, ADC conversion circuit and conditioning circuit and then processed by the digital signal processor chip. After obtaining the real-time leakage current data, it is fed back to the host computer module through the I / O interface. The host computer module draws the chart to realize the function of online monitoring of leakage current.

[0033] A fourth aspect of the present invention provides a dynamic on-resistance test method, which is implemented based on the aforementioned GaN power device comprehensive aging stress test system, and includes:

[0034] C1: In the aging state, set the drain-source voltage value, gate-source voltage value, and double-pulse current value of the double-pulse test in the host computer module;

[0035] C2: Use a differential probe to connect to the drain and source ends of the device under test to measure the drain-source voltage; connect a ground probe to the gate-source of the device under test to measure its gate-source voltage; add a clamp circuit with a preset resolution to the source and drain ends of the device under test, and connect another ground probe to both ends of this clamp circuit; finally, measure the drain-source current through a coaxial resistor connected between the source and ground of the device under test; connect the measurement points in these four main circuits to the oscilloscope through probes;

[0036] C3: Send a dynamic on-resistance test command. After the upper computer module responds, it sends the command to the lower computer through the I / O interface. The preset program built into the digital signal processor chip sends a PWM signal to the main circuit module to start the double pulse test. At the same time, the gate drive channel and the drain-source power loop channel are turned on. The corresponding PWM signal generated by the digital signal processor chip controls the opening and closing of the device through the gate drive circuit, thereby obtaining the required double pulses.

[0037] C4: by performing several groups of double pulse tests on the device under test, finally obtaining several groups of double pulse test waveforms of the device under test;

[0038] C5: Several groups of double pulse test waveforms of the device under test, the voltage drop across the device under test, and the current of the device under test are transmitted to the host computer module through the I / O interface, and the host computer module calculates the dynamic on-resistance of the device under test by Ohm's law; among them, the voltage drop across the device under test is measured by the clamping circuit, and the current of the device under test is measured by the coaxial resistance.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention integrates three aging stress modes, namely, high temperature reverse bias, high temperature gate bias and power cycle, on one platform, and can flexibly adjust the operating environment temperature, load current / voltage, device on-time and gate drive conditions to meet the diverse testing requirements of different GaN power devices. At the same time, it can also monitor the junction temperature, case temperature, leakage current, junction-case thermal resistance and dynamic on-resistance of the device under test online. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A connection diagram of a GaN power device comprehensive aging stress test system provided in this embodiment;

[0042] Figure 2 A curve diagram of drain-source on-state voltage drop and junction temperature under 200mA provided in this embodiment;

[0043] Figure 3 A schematic diagram of the working timing in the power cycle mode provided in this embodiment;

[0044] Figure 4A schematic diagram of the connection and measurement points between the oscilloscope and the main circuit provided in this embodiment;

[0045] Figure 5 This is a timing diagram for testing dynamic on-resistance using the double pulse method provided in this embodiment. DETAILED DESCRIPTION

[0046] The accompanying drawings are only used for illustrative purposes and are not to be construed as limiting the present invention;

[0047] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0048] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0049] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0050] In addition, in the description of this application, unless otherwise specified, "multiple" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0051] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0052] Example 1

[0053] Please refer to Figure 1 , This embodiment provides a GaN power device comprehensive aging stress test system, the system includes a host computer module, a central control system, a main circuit module, a power module, an oscilloscope, a temperature control module and a device under test slot, wherein the central control system stores a high temperature reverse bias mode program, a high temperature gate bias mode program, and a power cycle mode program;

[0054] The host computer module is connected to the central control system through an I / O interface; the host computer module is used to send control commands to the central control system;

[0055] The central control system is respectively connected to the main circuit module, the power module and the temperature control module in communication; the central control system is used to receive commands from the host computer to control the temperature control module, the power module and the main circuit module;

[0056] The power supply module is connected to the main circuit module;

[0057] The main circuit module is connected to the oscilloscope;

[0058] The temperature control module is connected to the device under test slot;

[0059] The device under test slot is connected to the main circuit module.

[0060] It should be noted that the power cycle mode can be further divided into the constant conduction time mode and the constant junction temperature fluctuation mode. In terms of software, both power cycle modes can be implemented through the preset program in the digital signal processor chip of the central control system. In terms of hardware, the power cycle aging test often requires applying a drain-source load current to the device under test to increase the junction temperature, and then cooling it down to complete a power cycle, and during this period, the thermal parameters and dynamic parameters of the device under test are monitored online; therefore, in terms of hardware, the power module is required to heat the device under test with a large current through the power circuit of the main circuit, and the real-time electrical parameters of the device under test are extracted through the test circuit and the ADC conversion and conditioning circuit, and the working state of the device under test is controlled through the gate drive circuit, and the cooling mode of the temperature control module is used to control the water pump solenoid valve switch through the DSP to cool the device under test. Finally, the data is fed back to the host computer after being processed by the central control system.

[0061] It should be noted that in software, the high-temperature gate bias mode can also be adjusted through the preset program of the digital signal processor chip of the central control system for parameter adjustment, data feedback, etc. In hardware, the high-temperature gate bias requires continuous high-temperature stress and gate bias voltage stress, so a power module is needed. A stable voltage is input to the gate-source ends of the device under test through the power management module on the main circuit. In terms of high temperature, the ceramic gasket attached under the device under test is heated through the temperature control module, and the temperature is stabilized within an allowable range. And the leakage current of the device under test is monitored through the ADC conversion and signal conditioning module of the power module and the main circuit.

[0062] It should be noted that, similar to high temperature gate bias, the high temperature reverse bias mode can also be adjusted in software through the DSP preset program of the central control system for parameter adjustment, data feedback, etc.; in hardware, the high voltage module in the power module is required to continuously apply a large voltage between the drain and source of the device under test. In terms of high temperature, the ceramic gasket attached under the device under test is heated by the temperature control module, and the temperature is stabilized within an allowable range. In terms of online monitoring of leakage current, the module used is the same as the module required for high temperature gate bias.

[0063] In a specific embodiment, the host computer module is composed of a program based on a computer.

[0064] In a specific embodiment, the central control system includes a digital signal processor chip (DSP) and an auxiliary circuit, wherein the digital signal processor chip stores a high-temperature reverse bias mode program, a high-temperature gate bias mode program, and a power cycle mode program; the digital signal processor chip is connected to the auxiliary circuit via a detachable pin header.

[0065] In a specific embodiment, the main circuit module includes a PCB board and a power transformer circuit, a signal conditioning circuit, a power circuit, a clamping circuit, a MOS switch circuit, an ADC circuit, a gate drive circuit, an off-state stress time control circuit, a high-voltage power supply circuit, an auxiliary power supply circuit, and a DC / DC step-down voltage regulator circuit arranged on the PCB board.

[0066] In a specific embodiment, the temperature control module includes an industrial liquid cooler, a water pump solenoid valve and a water pipeline; the device under test slot includes a heat conductive sheet; the temperature control module is connected to the heat conductive sheet through a water pump solenoid valve and a water pipeline.

[0067] In a specific embodiment, the heat conductive sheet is provided with a groove, a thermocouple is provided in the groove, and the thermocouple is connected to the ADC circuit and the signal conditioning circuit.

[0068] In a specific embodiment, the oscilloscope includes a differential probe and a ground probe; the differential probe and the ground probe are used to be externally connected to the clamp circuit, the power circuit, and the device under test slot respectively to monitor the IV waveform of the device under test.

[0069] Example 2

[0070] This embodiment provides a junction-to-shell thermal resistance test method, which is implemented based on a GaN power device comprehensive aging stress test system described in Embodiment 1. The junction-to-shell thermal resistance test method includes:

[0071] A1: Solder the GaN chip sample to the Al substrate, and lead out three pins in the order of gate, drain, and source to connect to the device under test slot of the aging stress test system;

[0072] Specifically, the GaN chip sample is welded to the Al substrate, and three pins are led out in the order of gate (G), drain (D) and source (S) for accessing the device under test slot of the aging test system.

[0073] A2: Test the relationship between drain-source on-state voltage drop and junction temperature at different temperature points to obtain the junction temperature calibration curve;

[0074] Specifically, four temperature points, 25°C, 50°C, 75°C, and 100°C, are selected to obtain the following Figure 2 The drain-source on-state voltage drop and junction temperature curve is shown in the figure under the condition of test current of 200mA. It can be seen that when the gate is turned on, the drain-source on-state voltage drop of the GaN device is linearly related to the junction temperature and shows a positive temperature coefficient.

[0075] A3: Burn the linear function corresponding to the junction temperature calibration curve into the digital signal processor chip;

[0076] Specifically, the core DSP chip of the central control system is removed from the pin header, and the linear function of the junction temperature calibration curve of the device is burned into the DSP through a computer and a simulator.

[0077] A4: Set the gate drive voltage value of the device under test through the DC / DC step-down voltage regulator circuit on the main circuit, select the power cycle mode and set the test parameters in this mode; install the device under test into the device under test slot;

[0078] Specifically, turn on the host computer, the slave computer (including the central control system and the main circuit), the oscilloscope, the water pump solenoid valve power supply, and the liquid cooler power supply equipment of the upper computer in turn, enter the upper computer human-computer interaction program, check whether the communication between the upper computer and the slave computer is normal, set the gate drive voltage value of the GaN power device through the DC / DC buck regulator module on the main circuit, and set the power cycle mode, load current size, cycle period, conduction time and other test parameters required for this experiment. After confirmation, install the device under test into the device under test slot, use a screwdriver to adjust the device under test to fit tightly with the ceramic gasket, close the DUT box to facilitate precise temperature control and avoid the influence of ambient temperature; select the power cycle mode, click to start the test, and the power cycle test begins.

[0079] A5: The host computer module sends the test parameters and the aging start instruction to the digital signal processor chip. The central control system first opens the power cycle mode channel. Figure 3 The timing of the water pump solenoid valve, gate drive circuit, and aging current power circuit shown are sequentially input into the main circuit module, and then the main circuit module inputs the processed signal into the device under test, and simultaneously opens the gate channel, the water pump solenoid valve channel, and the load current channel, so that the device starts to heat up under the condition of load current stress, and then closes all channels to enter the cooling stage. After the temperature drops to the preset temperature, it starts to heat up again and enters the next power cycle;

[0080] A7: The digital signal processor chip opens the test current channel and injects a 200mA test current into the device under test to obtain the voltage drop across the drain and source of the device under test. The analog signal then passes through the sampling circuit, ADC conversion circuit, and signal conditioning circuit in the main circuit and enters the digital signal processor chip to infer the real-time junction temperature of the device under test according to the preset junction temperature calibration curve. Finally, the data is sent to the host computer module through the communication serial port, and the host computer module draws a real-time junction temperature curve.

[0081] A8: The shell temperature of the device under test is collected through a thermocouple buried in the groove between the device under test and the heat conducting sheet of the device under test slot through thermal conductive silicone grease. The collected electrical signal enters the digital signal processor chip for processing through the ADC sampling circuit and conditioning circuit and is fed back to the host computer module for shell temperature chart drawing, thereby achieving the purpose of online monitoring;

[0082] A9: By obtaining the real-time junction temperature and case temperature, through R TH =(Tj-Tc) / P load calculation formula to obtain real-time thermal resistance, and feed the data back to the host computer module, through which the host computer module draws charts to achieve online monitoring of the junction-to-case thermal resistance of the device under test;

[0083] Specifically, after reaching the preset power cycle aging period, the DSP control device automatically stops running and automatically lowers the internal temperature of the DUT slot box to room temperature. At the same time, the host computer saves all online monitoring data as historical data and stores it in the computer.

[0084] Example 3

[0085] This embodiment provides a leakage current testing method, which is implemented based on a GaN power device comprehensive aging stress testing system described in Embodiment 1. The leakage current testing method includes:

[0086] B1: Place the DUT into the DUT slot and apply thermal grease evenly on the contact surface;

[0087] B2: Set the temperature and gate-source voltage bias or drain-source voltage bias in the host computer module, and select high-temperature gate bias or high-temperature reverse bias mode for testing;

[0088] B3: After the test starts, the host computer module sends instructions to the digital signal processor chip, and then the digital signal processor chip opens the water pump solenoid valve, and the industrial liquid cooler heats the coolant until the temperature reaches the preset value. The digital signal processor chip then opens the gate-source channel or drain-source channel to apply high-temperature gate bias or high-temperature reverse bias voltage stress to the device under test;

[0089] B4: During the aging process, the digital signal processor chip opens the test voltage channel and inputs the test voltage to the gate source or drain source of the device under test. The leakage current obtained is processed into a digital signal by the sampling circuit, ADC conversion circuit and conditioning circuit. The digital signal processor chip processes the real-time leakage current data and feeds it back to the host computer module through the I / O interface. The host computer module draws the chart to realize the function of online monitoring of leakage current.

[0090] Specifically, after reaching the aging time preset by the host computer, the DSP chip receives the command of the host computer and automatically turns off the gate-source or drain-source voltage stress. At the same time, the liquid cooler starts to cool the temperature in the DUT slot box to room temperature through the water pipeline. The host computer also stores all online monitoring data in the computer as historical data.

[0091] Example 4

[0092] This embodiment provides a dynamic on-resistance test method, which is implemented based on a GaN power device comprehensive aging stress test system described in Embodiment 1. The dynamic on-resistance test method includes:

[0093] C1: In the aging state, set the drain-source voltage value, gate-source voltage value, and double-pulse current value of the double-pulse test in the host computer module;

[0094] Specifically, the magnitude of the double pulse current is determined by the detachable inductor in the main circuit double pulse test module, and is obtained according to the expression:

[0095]

[0096] C2: Please refer to Figure 4 , use a differential probe to connect to the drain and source ends of the device under test to measure the drain-source voltage; connect a ground probe to the gate-source of the device under test to measure its gate-source voltage; add a clamp circuit with a preset resolution to the source and drain ends of the device under test, and connect another ground probe to both ends of this clamp circuit; finally, measure the drain-source current through a coaxial resistor connected between the source and ground of the device under test; connect the measurement points in these four main circuits to the oscilloscope through probes;

[0097] C3: Send a dynamic on-resistance test command. After the upper computer module responds, it sends the command to the lower computer through the I / O interface. The preset program built into the digital signal processor chip sends a PWM signal to the main circuit module to start the double pulse test. At the same time, the gate drive channel and the drain-source power loop channel are turned on. The corresponding PWM signal generated by the digital signal processor chip controls the opening and closing of the device through the gate drive circuit, thereby obtaining the required double pulses.

[0098] C4: by performing several groups of double pulse tests on the device under test, finally obtaining several groups of double pulse test waveforms of the device under test;

[0099] Specifically, the double pulse test sequence is as follows: Figure 5 As shown in the figure: before t0, the device under test first undergoes off-state stress for a certain period of time. At t0, the first gate signal rising edge of the device under test arrives, the device under test is turned on, the oscilloscope is triggered and starts to capture the signal, and the drain-source voltage drop of the device is measured by the clamping circuit, and the drain-source current also increases linearly. At t1, the gate control signal of the device under test switches to a low level, and the device is turned off at this time. t1 to t2 is the off-time of the device. At t2, the gate rising edge of the device under test arrives again, and the device is turned on again. The magnitude of the drain-source current at this time is almost equal to the current at the end of the first pulse. At t3, the device under test is turned off again, and a complete set of double pulse tests is completed. It enters a set off-state stress time and is ready to automatically start the next double pulse test, so as to achieve the purpose of multiple sets of double pulse tests of the dynamic on-resistance of the device.

[0100] C5: Several sets of double pulse test waveforms of the device under test, the voltage drop across the device under test, and the current of the device under test are transmitted to the host computer module through the I / O interface, and the host computer module calculates the dynamic on-resistance of the device under test by Ohm's law; the voltage drop across the device under test is measured by the clamping circuit, and the current of the device under test is measured by the coaxial resistance;

[0101] It should be noted that the voltage measured by the clamp circuit is the sum of the voltage drops of the device under test and the diode in the clamp circuit. The actual device conduction voltage drop needs to be calculated by subtracting the diode conduction voltage drop from the measured value.

[0102] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A GaN power device comprehensive aging stress test system, characterized in that: The system comprises a host computer module, a central control system, a main circuit module, a power module, an oscilloscope, a temperature control module and a slot for a device under test, wherein the central control system stores a high-temperature reverse bias mode program, a high-temperature gate bias mode program and a power cycle mode program; The host computer module is connected to the central control system through an I / O interface; the host computer module is used to send control commands to the central control system; The central control system is respectively connected to the main circuit module, the power module and the temperature control module in communication; the central control system is used to receive commands from the host computer to control the temperature control module, the power module and the main circuit module; The power supply module is connected to the main circuit module; The main circuit module is connected to the oscilloscope; The temperature control module is connected to the device under test slot; The device under test slot is connected to the main circuit module.

2. A GaN power device comprehensive aging stress test system according to claim 1, characterized in that: The host computer module is composed of a program based on a computer.

3. The GaN power device comprehensive aging stress test system according to claim 1, characterized in that: The central control system includes a digital signal processor chip and an auxiliary circuit, wherein the digital signal processor chip stores a high-temperature reverse bias mode program, a high-temperature gate bias mode program, and a power cycle mode program; the digital signal processor chip is connected to the auxiliary circuit via a detachable pin header.

4. The GaN power device comprehensive aging stress test system according to claim 1, characterized in that: The main circuit module includes a PCB board and a power transformer circuit, a signal conditioning circuit, a power circuit, a clamping circuit, a MOS switch circuit, an ADC circuit, a gate drive circuit, an off-state stress time control circuit, a high-voltage power supply circuit, an auxiliary power supply circuit, and a DC / DC step-down voltage stabilization circuit arranged on the PCB board.

5. The GaN power device comprehensive aging stress test system according to claim 1, characterized in that: The temperature control module includes an industrial liquid cooler, a water pump solenoid valve and a water pipeline; the device under test slot includes a heat conducting sheet; the temperature control module is connected to the heat conducting sheet through a water pump solenoid valve and a water pipeline.

6. A GaN power device comprehensive aging stress test system according to claim 5, characterized in that: The heat conducting sheet is provided with a groove, a thermocouple is provided in the groove, and the thermocouple is connected to the ADC circuit and the signal conditioning circuit.

7. A GaN power device comprehensive aging stress test system according to claim 4, characterized in that: The oscilloscope comprises a differential probe and a ground probe; the differential probe and the ground probe are respectively used to be externally connected to the clamp circuit, the power circuit and the device under test slot to monitor the IV waveform of the device under test.

8. A junction-to-shell thermal resistance test method, the junction-to-shell thermal resistance test method is implemented based on a GaN power device comprehensive aging stress test system according to any one of claims 1 to 7, characterized in that: The junction-to-case thermal resistance test method comprises: A1: Solder the GaN chip sample to the Al substrate, and lead out three pins in the order of gate, drain, and source to connect to the device under test slot of the aging stress test system; A2: Test the relationship between drain-source on-state voltage drop and junction temperature at different temperature points to obtain the junction temperature calibration curve; A3: Burn the linear function corresponding to the junction temperature calibration curve into the digital signal processor chip; A4: Set the gate drive voltage value of the device under test through the DC / DC step-down voltage regulator circuit on the main circuit, select the power cycle mode and set the test parameters in this mode; install the device under test into the device under test slot; A5: The host computer module sends the test parameters and the instruction to start aging to the digital signal processor chip. The central control system first opens the power cycle mode channel, and inputs the timing of the water pump solenoid valve, the gate drive circuit, and the aging current power circuit into the main circuit module in sequence. The main circuit module then inputs the processed signal into the device under test, and opens the gate channel, the water pump solenoid valve channel, and the load current channel at the same time, so that the device starts to heat up under the condition of load current stress, and then closes all channels to enter the cooling stage. After the temperature drops to the preset temperature, it starts to heat up again and enters the next power cycle. A7: The digital signal processor chip opens the test current channel and injects a 200mA test current into the device under test to obtain the voltage drop across the drain and source of the device under test. The analog signal then passes through the sampling circuit, ADC conversion circuit, and signal conditioning circuit in the main circuit and enters the digital signal processor chip to infer the real-time junction temperature of the device under test according to the preset junction temperature calibration curve. Finally, the data is sent to the host computer module through the communication serial port, and the host computer module draws a real-time junction temperature curve. A8: The shell temperature of the device under test is collected through a thermocouple buried in the groove between the device under test and the heat conducting sheet of the device under test slot through thermal conductive silicone grease. The collected electrical signal enters the digital signal processor chip for processing through the ADC sampling circuit and conditioning circuit and is fed back to the host computer module for shell temperature chart drawing, thereby achieving the purpose of online monitoring; A9: By obtaining the real-time junction temperature and case temperature, through R TH =(Tj-Tc) / P load calculation formula to obtain real-time thermal resistance, and feed the data back to the host computer module, through which the host computer module draws charts to achieve online monitoring of the junction-to-case thermal resistance of the device under test.

9. A leakage current testing method, the leakage current testing method is implemented based on a GaN power device comprehensive aging stress testing system according to any one of claims 1 to 7, characterized in that: The leakage current testing method comprises: B1: Place the DUT into the DUT slot and apply thermal grease evenly on the contact surface; B2: Set the temperature and gate-source voltage bias or drain-source voltage bias in the host computer module, and select high-temperature gate bias or high-temperature reverse bias mode for testing; B3: After the test starts, the host computer module sends instructions to the digital signal processor chip, and then the digital signal processor chip opens the water pump solenoid valve, and the industrial liquid cooler heats the coolant until the temperature reaches the preset value. The digital signal processor chip then opens the gate-source channel or drain-source channel to apply high-temperature gate bias or high-temperature reverse bias voltage stress to the device under test; B4: During the aging process, the digital signal processor chip opens the test voltage channel and inputs the test voltage to the gate-source or drain-source of the device under test. The leakage current obtained is processed into a digital signal by the sampling circuit, ADC conversion circuit and conditioning circuit and then processed by the digital signal processor chip. After obtaining the real-time leakage current data, it is fed back to the host computer module through the I / O interface. The host computer module draws the chart to realize the function of online monitoring of leakage current.

10. A dynamic on-resistance test method, the dynamic on-resistance test method is implemented based on a GaN power device comprehensive aging stress test system according to any one of claims 1 to 7, characterized in that: The dynamic on-resistance test method comprises: C1: In the aging state, set the drain-source voltage value, gate-source voltage value, and double-pulse current value of the double-pulse test in the host computer module; C2: Use a differential probe to connect to the drain and source ends of the device under test to measure the drain-source voltage; connect a ground probe to the gate-source of the device under test to measure its gate-source voltage; add a clamp circuit with a preset resolution to the source and drain ends of the device under test, and connect another ground probe to both ends of this clamp circuit; finally, measure the drain-source current through a coaxial resistor connected between the source and ground of the device under test; connect the measurement points in these four main circuits to the oscilloscope through probes; C3: Send a dynamic on-resistance test command. After the upper computer module responds, it sends the command to the lower computer through the I / O interface. The preset program built into the digital signal processor chip sends a PWM signal to the main circuit module to start the double pulse test. At the same time, the gate drive channel and the drain-source power loop channel are turned on. The corresponding PWM signal generated by the digital signal processor chip controls the opening and closing of the device through the gate drive circuit, thereby obtaining the required double pulses. C4: by performing several groups of double pulse tests on the device under test, finally obtaining several groups of double pulse test waveforms of the device under test; C5: Several groups of double pulse test waveforms of the device under test, the voltage drop across the device under test, and the current of the device under test are transmitted to the host computer module through the I / O interface, and the host computer module calculates the dynamic on-resistance of the device under test by Ohm's law; among them, the voltage drop across the device under test is measured by the clamping circuit, and the current of the device under test is measured by the coaxial resistance.

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