Processing method, device and system suitable for custom CPU instruction
By introducing a custom instruction execution module into the target processor, the extension and execution of custom instructions are realized, which solves the problem of insufficient processor instruction expansion in the prior art, improves the instruction execution efficiency of the CPU and simplifies the modification process of custom instructions.
Patent Information
- Application Number
- CN202411501561.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-03-04
AI Technical Summary
In the prior art, the processor's instruction expansion is insufficient and it is difficult to meet practical application needs, especially in terms of the expansion and execution efficiency of custom CPU instructions.
A processing method is provided to realize the extension and execution of custom instructions by introducing a custom instruction execution module into the target processor and configuring its adaptive connection with the target processor. The method includes parsing the instruction type of the instruction to be executed, sending the instruction to be executed and the source register data to the custom instruction execution module, performing decoding processing and instruction calculation, and generating and sending the instruction calculation results to the target processor.
It realizes flexible expansion and efficient execution of custom CPU instructions, improves the CPU's instruction execution efficiency, and does not need to modify the instruction encoding inside the target processor, simplifying the modification and expansion process of custom instructions.
Smart Images
Figure CN119556983A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a processing method, device and system, and in particular to a processing method, device and system suitable for customizing CPU instructions. Background Art
[0002] An instruction is the smallest unit of a processor's operation (such as addition, subtraction, multiplication, and division, or reading / writing memory data), and an instruction set is a set of instructions. With the architecture of the instruction set, different processor hardware implementations can be used to design processors with different performances.
[0003] The specific hardware implementation of the processor is called microarchitecture. Although different microarchitecture implementations may result in differences in performance and cost, for processors that follow the same instruction set architecture, the software can run completely on the corresponding processor without any modification. Therefore, the instruction set architecture can be understood as an abstract layer, which constitutes a bridge and interface between the underlying hardware of the processor and the software running on it, and is also an important abstract layer in current computer processors.
[0004] Based on the modular CPU architecture, users can flexibly choose different instruction set combinations to meet different application scenarios. For example, for small-area, low-power embedded scenarios, users can choose simple instruction set combinations to reduce power consumption and area while meeting functional requirements; while for high-performance application operating system scenarios, more complex instruction set combinations can be selected to improve performance, and their common parts can be compatible with each other.
[0005] For instruction expansion, the main methods currently used include memory-mapped coprocessor, coherent accelerator and direct expansion of local CPU instruction set, but all of them have some shortcomings in use, specifically:
[0006] For memory-mapped coprocessors, when executing extended custom instructions, the CPU registers cannot be accessed, and additional logic is required to connect the processing logic to the system bus.
[0007] For coherent accelerators, independent register sets require separate data transfers when operating. In real-time applications, the ability to stall the CPU can wreak havoc on instruction flow, and stalling data-dependent instructions can negatively impact determinism.
[0008] To directly expand the local CPU instruction set, you need to invest time in the RTL of the CPU core and comprehensively consider the impact of each instruction.
[0009] It can be seen from the above description that in the prior art, instruction extension for processors has some deficiencies and is difficult to meet actual application requirements. Summary of the invention
[0010] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method, device and system for processing custom CPU instructions, which flexibly implement the expansion of custom instructions and improve the instruction execution efficiency of the CPU.
[0011] According to the technical solution provided by the present invention, a processing method suitable for customizing CPU instructions includes:
[0012] Providing a target processor and a custom instruction execution module for executing custom instructions, and configuring the custom instruction execution module to be adaptively connected to the target processor;
[0013] For the received instruction to be executed, the target processor parses the instruction type of the instruction to be executed, and when the instruction to be executed is a custom instruction adapted to the custom instruction execution module, the target processor sends the current instruction to be executed and the source register data corresponding to the current instruction to be executed to the custom execution module;
[0014] The custom execution module decodes the received instruction to be executed to determine the execution type of the instruction to be executed after the decoding process, wherein the execution type of the instruction to be executed includes a pipeline instruction or a non-pipeline instruction;
[0015] Based on the instruction type of the instruction to be executed, the custom instruction execution module performs instruction operation processing on the source register data that is adapted to the instruction to be executed, so as to generate an instruction operation result after the instruction operation processing, and send the instruction operation result to the target processor.
[0016] The custom instruction execution module includes a pipeline instruction execution unit and a non-pipeline instruction execution unit, wherein:
[0017] When the execution type of the instruction to be executed is a pipeline instruction, the pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and send the instruction operation result to the target processor in the next clock cycle;
[0018] When the execution type of the instruction to be executed is non-pipeline execution, the non-pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and immediately send the instruction operation result to the target processor.
[0019] The target processor is connected to the custom instruction execution module through a custom instruction interface, where:
[0020] When the instruction to be executed is a custom instruction, the target processor sends the current instruction to be executed and the source register data to the custom instruction interface, and configures the enable signal of the custom instruction interface to be in a valid state, so that the custom instruction interface sends the instruction to be executed and the source register data to the custom instruction execution module;
[0021] The generated instruction operation results are sent by the custom instruction execution module to the target processor through the custom instruction interface.
[0022] After the custom instruction execution module determines the execution type of the instruction to be executed through decoding processing, the execution type of the instruction to be executed is sent to the target processor through the custom instruction interface.
[0023] The target processor writes the received instruction operation result into the destination register.
[0024] When the target processor parses the instruction type of the to-be-executed instruction as a non-customized instruction, the target processor directly performs instruction operation processing adapted to the to-be-executed instruction, and writes the generated instruction operation result into the destination register.
[0025] For the instruction to be executed, configuring the instruction type code in the instruction to be executed;
[0026] The target processor determines the instruction type of the received instruction to be executed according to the instruction type code in the instruction to be executed.
[0027] For the instruction to be executed, configuring the execution type code in the instruction to be executed;
[0028] When the user-defined instruction execution module decodes the instruction to be executed, it determines the execution type of the instruction to be executed according to the execution type code in the instruction to be executed.
[0029] A processing device suitable for custom CPU instructions, comprising at least a target processor and a custom instruction execution module adapted to be connected to the target processor, wherein for any instruction to be executed, the target processor and the custom instruction execution module adopt the processing method to process the instruction so as to write the instruction operation result into the destination register after processing.
[0030] A processing system suitable for customizing CPU instructions comprises at least the processing device described above, and utilizes the processing device to process instructions to be executed.
[0031] Advantages of the present invention: The present invention can separate the customizable custom instructions from the instructions of the internal instruction set of the target processor, which is convenient for modifying the custom instructions in different application scenarios to improve the efficiency of the target processor; the custom instruction execution module is adaptively connected to the target processor through the custom instruction interface, and when modifying the custom instruction, there is no need to change the instruction encoding inside the target processor, and for the target processor, at runtime, the custom instruction execution module can be regarded as an internal module, so that the expansion of the custom instructions can be flexibly realized, and the instruction execution efficiency of the CPU can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 The figure is a structural block diagram of an embodiment of the processing device of the present invention.
[0033] Figure 2 It is a schematic diagram of an embodiment of the present invention in which a target processor and a custom instruction interface perform data transmission when processing a custom instruction.
[0034] Figure 3 It is a flow chart of processing instructions to be executed according to the present invention. DETAILED DESCRIPTION
[0035] The present invention will be further described below in conjunction with specific drawings and embodiments.
[0036] In order to flexibly implement the expansion of custom instructions and improve the instruction execution efficiency of the CPU, the present invention provides a processing method suitable for custom CPU instructions. Specifically, the processing method includes:
[0037] Providing a target processor and a custom instruction execution module for executing custom instructions, and configuring the custom instruction execution module to be adaptively connected to the target processor;
[0038] For the received instruction to be executed, the target processor parses the instruction type of the instruction to be executed, and when the instruction to be executed is a custom instruction adapted to the custom instruction execution module, the target processor sends the current instruction to be executed and the source register data corresponding to the current instruction to be executed to the custom execution module;
[0039] The custom execution module decodes the received instruction to be executed to determine the execution type of the instruction to be executed after the decoding process, wherein the execution type of the instruction to be executed includes a pipeline instruction or a non-pipeline instruction;
[0040] Based on the instruction type of the instruction to be executed, the custom instruction execution module performs instruction operation processing on the source register data that is adapted to the instruction to be executed, so as to generate an instruction operation result after the instruction operation processing, and send the instruction operation result to the target processor.
[0041] It is understandable that the target processor can adopt an existing commonly used CPU, such as the target processor can be an ARM processor that executes reduced instruction set (RISCV), and the type of the target processor can be selected as needed to meet the actual application scenario requirements. In order to achieve the expansion of custom instructions and the efficiency of instruction execution, a custom instruction execution module should also be provided, wherein the custom instruction execution module is used to execute custom instructions. Here, executing custom instructions specifically refers to being able to execute custom instructions. Therefore, the custom instruction execution module should be related to the custom instructions, and specifically be based on being able to execute custom instructions.
[0042] During the specific implementation, the custom instruction execution module should be configured to adapt and connect with the target processor. The custom instruction execution module and the target processor are adapted and connected, which specifically means that data interaction can be achieved between the custom instruction execution module and the target processor. For example, the target processor can send custom instructions to the custom instruction execution module, and the custom instruction execution module can send the instruction operation results to the target processor. The specific adaptation connection method will be described in detail below.
[0043] When working, the instruction to be executed should be sent to the target processor, so that the target processor can parse the instruction to be executed, and determine the instruction type of the instruction to be executed after parsing. It can be understood that the target processor parses the instruction to be executed mainly to determine whether the instruction to be executed is a custom instruction, wherein, when the instruction to be executed is a custom instruction, the current instruction to be executed should be sent to the custom instruction execution module, otherwise, the target processor should directly process the instruction to be executed. It should be noted that when the instruction to be executed is parsed as not being a custom instruction, the instruction to be executed is a non-custom instruction, wherein the non-custom instruction is an instruction in the native instruction set of the target processor to which it belongs. At this time, the target processor can directly process the instruction to be executed.
[0044] In one embodiment of the present invention, for the instruction to be executed, an instruction type code is configured in the instruction to be executed;
[0045] The target processor determines the instruction type of the received instruction to be executed according to the instruction type code in the instruction to be executed.
[0046] In order to determine the instruction type of the instruction to be executed, the instruction type code can be configured in the instruction to be executed. The method of configuring the instruction type code can be consistent with the existing one. For example, when designing the native instruction set inside the target processor, a certain encoding space should be reserved. Taking the 32-bit RISCV instruction as an example, a value (such as 7'b1110000) can be specified in the opcode bit segment, that is, [6:0], and the value of the opcode bit segment is pointed to the custom instruction. In this way, the instruction type code is configured in the instruction to be executed.
[0047] For the received instructions to be executed, the target processor will decode the instructions to be executed. In the decoding stage, if the value of the opcode bit segment is detected to be 7'b1110000, the target processor can determine that the current instruction to be executed is a custom instruction, otherwise, the instruction to be executed is a non-custom instruction. It can be understood that when the instruction to be executed is a non-custom instruction, the value of the opcode bit segment should not be 7'b1110000. Of course, in the specific implementation, other methods can also be used to determine the instruction type of the instruction to be executed. The method of determining the instruction type of the instruction to be executed can be selected according to needs, and will not be listed here one by one.
[0048] In one embodiment of the present invention, when the target processor parses the instruction type of the instruction to be executed as a non-customized instruction, the target processor directly performs instruction operation processing adapted to the instruction to be executed, and writes the generated instruction operation result into the destination register.
[0049] It can be seen from the above description that when the instruction to be executed is a non-custom instruction, the current instruction to be executed can be operated by the target processor, that is, the instruction operation adapted to the instruction to be executed is performed. Generally, the instruction to be executed contains the corresponding instruction operation and the corresponding source register address. The corresponding source register data can be obtained through the source register address. The instruction operation is to perform corresponding operation processing on the obtained source register data. The instruction operation can be the addition, subtraction, multiplication, division and other operations mentioned above. The type of instruction operation can be determined according to actual needs.
[0050] After the target processor completes the instruction operation processing, it will generate the instruction operation result, and then the instruction operation result can be written into the destination register. In the specific implementation, the target processor completes the instruction operation processing and generates the instruction operation result in a manner consistent with the prior art. Writing the instruction operation result into the destination register means storing the instruction operation result into the destination register. The address of the destination register can also be generally obtained through the instruction to be executed.
[0051] As can be seen from the above description, the target processor can decode the instruction to be executed to determine the instruction type of the instruction to be executed. In addition, the address of the source register and the source register data in the source register can be obtained. In order to meet the processing of the custom instruction execution module, when it is determined that the instruction to be executed is a custom execution, the target processor should send the instruction to be executed and the corresponding source register data to the custom instruction execution module.
[0052] After receiving the instructions to be executed and the source register data sent by the target processor, the custom instruction execution module should decode the instructions to be executed to determine the execution type of the instructions to be executed after decoding. Specifically, the execution type of the instructions to be executed includes pipeline instructions or non-pipeline instructions. Determining the execution type of the instructions to be executed mainly determines the way to perform instruction operations on the source register data.
[0053] It should be noted that when determining the execution type of the instruction to be executed, it is mainly determined whether the execution type of the instruction to be executed is a pipeline execution instruction. In one embodiment of the present invention, for the instruction to be executed, an execution type code is configured in the instruction to be executed; when the custom instruction execution module decodes the instruction to be executed, the execution type of the instruction to be executed is determined according to the execution type code in the instruction to be executed.
[0054] In specific implementation, when determining the execution type of the instruction to be executed, a feasible method may be: the execution type of the instruction to be executed may be determined by the encoding. Taking the 32-bit RISCV instruction as an example, when the opcode bit segment is 7'b1110000 and the func3 field (14:12) is 3'b100, it can be determined that the execution type of the current instruction to be executed is a pipeline instruction. When the func3 field is 3'b000, it can be determined that the execution type of the current instruction to be executed is a non-pipelined instruction. Of course, other methods can also be used to determine the execution type of the custom execution instruction, which will not be explained one by one here.
[0055] In one embodiment of the present invention, the custom instruction execution module includes a pipeline instruction execution unit and a non-pipeline instruction execution unit, wherein:
[0056] When the execution type of the instruction to be executed is a pipeline instruction, the pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and send the instruction operation result to the target processor in the next clock cycle;
[0057] When the execution type of the instruction to be executed is non-pipeline execution, the non-pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and immediately send the instruction operation result to the target processor.
[0058] Figure 1 An embodiment of a custom instruction execution module is shown in the figure. In the figure, the custom instruction execution module includes a decoder, a pipeline instruction execution unit and a non-pipeline instruction execution unit, wherein the decoder can be used to perform decoding processing on the instruction to be executed. The decoder can adopt an existing commonly used form, specifically based on whether it can meet the decoding processing of the instruction to be executed and determine the execution type of the instruction to be executed.
[0059] After the execution type of the instruction to be executed is determined by the decoder, the custom instruction execution module should configure the pipeline instruction execution unit or the non-pipeline instruction execution unit to perform corresponding instruction operations on the source register data. If the execution type of the instruction to be executed is a pipeline instruction, the pipeline instruction execution unit should be configured to perform instruction operations on the source register data. When the execution type of the instruction to be executed is a non-pipeline instruction, the non-pipeline instruction execution unit should be configured to perform corresponding instruction operations on the source register data.
[0060] It should be understood that the meanings of the pipeline instructions and non-pipeline instructions of the instructions to be executed are consistent with the prior art. In addition, the methods and processes of using the pipeline instruction execution unit and the non-pipeline instruction execution unit to perform the corresponding instruction operation processing can be consistent with the prior art. For example, when designing a custom instruction execution module, for pipeline instructions, the logic is usually more complicated. For example, if it contains logic such as multiplication, it is necessary to use registers for output, and the operation logic is designed according to the content of the custom instruction; for non-pipeline instructions, pure combinational logic can be used for operation and output. If it is necessary to implement the extension of SIMD (Single Instruction, Multiple Data) instructions, the multiplication or other more complex instructions in the SIMD instructions can be implemented in the pipeline instruction execution unit, and other simple instructions can be implemented in the non-pipeline instruction execution unit. The specific methods and processes for instruction operation processing will not be repeated here.
[0061] Specifically, after the instruction operation is processed, a corresponding instruction operation result will be generated. After the instruction operation result is obtained in the custom instruction execution module, the instruction operation result should be sent to the target processor, and the target processor writes the received instruction operation result into the destination register; among them, the instruction operation result and the destination register can refer to the above description, which will not be repeated here.
[0062] It should be noted that custom instructions of different execution types will affect the scheduling logic of the target processor. In one embodiment of the present invention, if the execution type of the instruction to be executed is a pipeline instruction, the target processor needs to wait for one clock cycle to obtain the returned instruction operation result; if the execution type of the instruction to be executed is a non-pipeline instruction, the target processor can only obtain the returned instruction operation result in the current clock cycle, thereby meeting the corresponding execution timing requirements of pipeline instructions and non-pipeline instructions.
[0063] In one embodiment of the present invention, the target processor is connected to the custom instruction execution module via a custom instruction interface, wherein:
[0064] When the instruction to be executed is a custom instruction, the target processor sends the current instruction to be executed and the source register data to the custom instruction interface, and configures the enable signal of the custom instruction interface to be in a valid state, so that the custom instruction interface sends the instruction to be executed and the source register data to the custom instruction execution module;
[0065] The generated instruction operation results are sent by the custom instruction execution module to the target processor through the custom instruction interface.
[0066] Figure 1 An embodiment of the adaptive connection between the target processor and the custom instruction execution module is shown in the figure. In the figure, the target processor is adaptively connected to the custom instruction execution module through a custom instruction interface, that is, the custom instruction interface is connected to the target processor and to the custom instruction execution module, so as to utilize the custom instruction interface to realize data interaction between the target processor and the custom instruction execution module. The following is an example of the method and process of realizing data interaction using the custom instruction interface.
[0067] It can be seen from the above description that after receiving the instruction to be executed, the target processor should decode the instruction to be executed to determine the instruction type of the instruction to be executed. Specifically, when it is determined that the instruction to be executed is a custom instruction, the target processor sends the current instruction to be executed and the source registered data to the custom instruction interface, and configures the enable signal of the custom instruction interface to be in a valid state, such as Figure 2 As shown, thereafter, the custom instruction interface can send the current instruction to be executed and the source register data to the custom instruction execution module.
[0068] In specific implementation, the custom instruction interface can also perform necessary processing on the instruction to be executed. After processing the instruction to be executed, instruction data can be obtained. At this time, the obtained instruction data and source register data can be sent to the custom instruction execution module, such as Figure 1 Of course, Figure 1 The instruction data in may also be the same as the instruction to be executed. At this time, the custom instruction interface does not need to process the instruction to be executed, that is, it only passes the instruction to be executed to the custom instruction execution module. The processing of the instruction to be executed by the custom instruction interface can be selected according to actual needs, based on the actual application scenario requirements, and will not be repeated here.
[0069] In one embodiment of the present invention, after the custom instruction execution module determines the execution type of the instruction to be executed through decoding processing, the execution type of the instruction to be executed is sent to the target processor through the custom instruction interface; specifically, if it is determined that the execution type of the instruction to be executed is a pipeline instruction, the custom instruction execution module sends a pipeline flag signal to the custom instruction interface, so as to send the pipeline flag signal to the target processor via the custom instruction interface; if it is determined that the execution type of the instruction to be executed is a non-pipeline instruction, the custom instruction execution module sends a non-pipeline flag signal to the custom instruction interface, so as to send the non-pipeline flag signal to the target processor via the custom instruction interface.
[0070] In addition, the instruction operation results generated in the custom instruction execution module should also be sent to the target processor through the custom instruction interface. Figure 1 In the example, the destination register data is the operation result data, and of course, the operation result data should also include the address information of the destination register. It is understandable that during the data exchange between the target processor and the custom instruction execution module, the custom instruction interface should remain in an enabled and valid state.
[0071] From the above description, a processing device suitable for custom CPU instructions can be obtained. In one embodiment of the present invention, it at least includes a target processor and a custom instruction execution module adapted to be connected to the target processor, wherein for any instruction to be executed, the target processor and the custom instruction execution module adopt the processing method described above to process it so as to write the instruction operation result into the destination register after processing.
[0072] Specifically, the target processor and the custom instruction execution module can refer to the above description. When processing the instruction to be executed, Figure 3 A complete processing flow is shown in Figure 3 The processing of the instructions to be executed is described in detail. It should be noted that: Figure 3 The CPU in is the target processor.
[0073] Figure 3 The method for processing the instruction to be executed is shown in FIG. 1 , which includes the following steps:
[0074] Step S00: During the operation of the target processor, a new instruction to be executed is received;
[0075] Step S01: According to the encoding information of the instruction to be executed, the instruction type of the instruction to be executed is judged to determine whether the instruction to be executed is a custom instruction; the method of judging the instruction type of the instruction to be executed can refer to the above description. It can be understood that the instruction encoding and content of the custom instruction can be fully customized, that is, the instructions can be added or reduced according to the specific design purpose of the CPU. If the instruction type of the instruction to be executed is a custom instruction, jump to step S02, otherwise jump to step S09
[0076] Step S02: When the instruction type is a custom instruction, the CPU needs to send the instruction to be executed to the custom instruction interface, and read the source register data according to the source register address contained in the current instruction to be executed, that is, the source register data is also sent to the custom instruction interface, and the enable signal of the custom instruction interface is set to be valid;
[0077] Step S03: after receiving a valid enable signal, the custom instruction interface sends the received instruction data and source register data to the custom instruction execution module;
[0078] Step S04: the decoder in the custom instruction execution module determines whether the instruction to be executed is a pipeline instruction according to the instruction code, and informs the CPU through the custom instruction interface;
[0079] Step S05: Determine whether the instruction to be executed is a pipeline type instruction, if so, jump to step S06, otherwise jump to step S07;
[0080] Step S06: the pipeline instruction execution unit operates on the source register data, and outputs the instruction operation result to the custom instruction interface in the next clock cycle;
[0081] Step S07: the non-pipelined instruction execution unit operates on the source register data, and outputs the instruction operation result to the custom instruction interface in the current clock cycle;
[0082] Step S08: the custom instruction interface returns the instruction operation result to the CPU;
[0083] Step S09: When the instruction to be executed is not a custom instruction, the CPU can complete the corresponding instruction operation;
[0084] Step S10: The CPU writes the instruction operation result into the destination register, and the instruction operation is completed.
[0085] Furthermore, a processing system suitable for custom CPU instructions can be obtained. In one embodiment of the present invention, it at least includes the processing device, and uses the processing device to process the instructions to be executed.
[0086] Specifically, the processing device can be applied to the corresponding device, that is, to form an instruction processing system, and the processing device can be used to implement the method and process of processing the instructions to be executed. Figure 3 As well as the corresponding instructions above, they will not be repeated here.
[0087] From the above description, it can be seen that the present invention can separate the customizable custom instructions from the instructions of the internal instruction set of the target processor, which is convenient for modifying the custom instructions in different application scenarios to improve the efficiency of the target processor; the custom instruction execution module is connected to the target processor through a custom instruction interface. When modifying the custom instructions, there is no need to change the instruction encoding inside the target processor, and for the target processor, the custom instruction execution module can be regarded as an internal module during runtime.
[0088] Furthermore, compared with the memory mapping coprocessor method, the present invention can directly access the registers of the target processor, and does not require additional logic to connect the processing logic to the system bus, reducing the delay of instruction processing. Compared with the coherent accelerator method, the present invention does not require separate data transmission, and will not interfere with the operating state of the target processor and will not affect the instruction flow; compared with the direct expansion of the local CPU instruction set method, the present invention does not need to invest time in the RTL (register transfer level) of the CPU core, and does not need to consider other instructions that have been designed, which is convenient for expanding and modifying instructions.
Claims
1. A processing method suitable for custom CPU instructions, characterized in that: The processing method comprises: Providing a target processor and a custom instruction execution module for executing custom instructions, and configuring the custom instruction execution module to be adaptively connected to the target processor; For the received instruction to be executed, the target processor parses the instruction type of the instruction to be executed, and when the instruction to be executed is a custom instruction adapted to the custom instruction execution module, the target processor sends the current instruction to be executed and the source register data corresponding to the current instruction to be executed to the custom execution module; The custom execution module decodes the received instruction to be executed to determine the execution type of the instruction to be executed after the decoding process, wherein the execution type of the instruction to be executed includes a pipeline instruction or a non-pipeline instruction; Based on the instruction type of the instruction to be executed, the custom instruction execution module performs instruction operation processing on the source register data that is adapted to the instruction to be executed, so as to generate an instruction operation result after the instruction operation processing, and send the instruction operation result to the target processor.
2. The processing method suitable for custom CPU instructions according to claim 1, characterized in that: The custom instruction execution module includes a pipeline instruction execution unit and a non-pipeline instruction execution unit, wherein: When the execution type of the instruction to be executed is a pipeline instruction, the pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and send the instruction operation result to the target processor in the next clock cycle; When the execution type of the instruction to be executed is non-pipeline execution, the non-pipeline instruction execution unit is configured to perform corresponding instruction operation processing on the source register data, and immediately send the instruction operation result to the target processor.
3. The processing method suitable for custom CPU instructions according to claim 2, characterized in that: The target processor is connected to the custom instruction execution module through a custom instruction interface, where: When the instruction to be executed is a custom instruction, the target processor sends the current instruction to be executed and the source register data to the custom instruction interface, and configures the enable signal of the custom instruction interface to be in a valid state, so that the custom instruction interface sends the instruction to be executed and the source register data to the custom instruction execution module; The generated instruction operation results are sent by the custom instruction execution module to the target processor through the custom instruction interface.
4. The processing method suitable for custom CPU instructions according to claim 3 is characterized in that: After the custom instruction execution module determines the execution type of the instruction to be executed through decoding processing, the execution type of the instruction to be executed is sent to the target processor through the custom instruction interface.
5. The processing method suitable for custom CPU instructions according to any one of claims 1 to 4, characterized in that: The target processor writes the received instruction operation result into the destination register.
6. The processing method suitable for custom CPU instructions according to any one of claims 1 to 4, characterized in that: When the target processor parses the instruction type of the to-be-executed instruction as a non-customized instruction, the target processor directly performs instruction operation processing adapted to the to-be-executed instruction, and writes the generated instruction operation result into the destination register.
7. The processing method suitable for custom CPU instructions according to any one of claims 1 to 4, characterized in that: For the instruction to be executed, configuring the instruction type code in the instruction to be executed; The target processor determines the instruction type of the received instruction to be executed according to the instruction type code in the instruction to be executed.
8. The processing method suitable for custom CPU instructions according to any one of claims 1 to 4, characterized in that: For the instruction to be executed, configuring the execution type code in the instruction to be executed; When the user-defined instruction execution module decodes the instruction to be executed, it determines the execution type of the instruction to be executed according to the execution type code in the instruction to be executed.
9. A processing device suitable for customizing CPU instructions, characterized in that: At least includes a target processor and a custom instruction execution module adapted to be connected to the target processor, wherein for any instruction to be executed, the target processor and the custom instruction execution module adopt the processing method described in any one of claims 1 to 8 to process the instruction so as to write the instruction operation result into the destination register after processing.
10. A processing system suitable for customizing CPU instructions, characterized in that: The method comprises at least the processing device according to claim 9, and uses the processing device to process the instructions to be executed.