STDCell pin adaptive selection method and related equipment

Abstract

The invention discloses an STDCell pin adaptive selection method and related equipment, and the method comprises the steps: carrying out the preprocessing operation of basic design rule check data, so as to obtain the rule data needed by a DRC rule engine through calculation; reading a user chip design file to perform pre-design operation to form pre-design data; generating a 3D space candidate VIA access point coordinate set of the metal layer where the pin is located, and generating a three-dimensional DRC evaluation value corresponding to each candidate coordinate; according to a VIA generation rule, pre-generated VIA information and pin physical information, performing physical information matching operation based on geometric operation to generate combined data with a three-dimensional DRC evaluation value; according to the three-dimensional DRC evaluation value in the combined data, performing optimization operation by adopting a target optimal algorithm so as to determine optimal combined data and a sequence thereof; and performing wiring access operation based on the optimal combination data and the sequence thereof to generate constrained six-degree-of-freedom wiring information.

Description

Technical Field

[0001] The present specification relates to the field of electronic design automation, and more specifically, the present application relates to an STDCell pin adaptive selection method and related equipment. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, FinFET (Fin Field-Effect Transistor) technology has gradually become mainstream. FinFET technology is widely used in high-performance computing and low-power design due to its smaller size, lower power consumption and higher performance. However, the introduction of FinFET technology also brings more complex design rules and wiring challenges.

[0003] In the FinFET process, it is necessary to consider not only the design rules of two-dimensional space (such as line width, spacing, alignment, etc.), but also the three-dimensional design rules (such as cross-layer spacing, VIA layout, and inter-layer interference). Traditional design rule checking methods are difficult to handle these complex rules efficiently. The multi-mask technology in the FinFET process limits the wiring direction, resulting in aggravated wiring congestion problems. The wiring schemes generated by traditional methods often have a large number of violations in subsequent DRC checks, requiring multiple rework adjustments. The pins of the standard cell (STDCell) play a core role in physical layout and logical connection. Reasonable pin selection directly affects the wiring length, signal delay, and DRC compliance. Existing methods lack pin optimization selection strategies under three-dimensional space and multi-dimensional constraints.

[0004] Therefore, it is necessary to propose a FinFET process STD Cell pin adaptive selection method and related equipment to improve the intelligence level of the FinFET process STD Cell pin adaptive selection. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a FinFET process STD Cell pin adaptive selection method, comprising: Preprocessing the basic design rule check data to calculate engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; Reading a user chip design file to perform a pre-design operation to form pre-design data, wherein the pre-design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; Generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the above-mentioned 3D design rule check rules, the above-mentioned physical information, the above-mentioned logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; Performing a physical information matching operation based on geometric operations according to VIA generation rules, pre-generated VIA information and the above-mentioned pin physical information to generate combined data with three-dimensional DRC evaluation values, wherein the above-mentioned combined data includes candidate coordinate values, three-dimensional DRC evaluation values ​​corresponding to the above-mentioned candidate coordinates, DRC evaluation values ​​of the candidate coordinates and VIA information; According to the three-dimensional DRC evaluation values ​​in the combined data, an optimization operation is performed using a target optimal algorithm to determine the most optimized combined data and its sequence; A wiring access operation is performed based on the above-mentioned optimized combination data and its sequence to generate wiring information with six degrees of freedom with constraints.

[0007] In a feasible implementation, it also includes: According to the above-mentioned optimized combination data, VIA position and type, multi-layer metal spacing rules and constraints between upper and lower VIA layers, a three-dimensional DRC rule determination operation is performed, and an evaluation value is calculated according to a multi-dimensional linear prediction function to correct the above-mentioned three-dimensional DRC evaluation value.

[0008] In a feasible implementation, it also includes: Before the bottom metal of VIA is matched with the pin metal, the DRC rules of each metal are processed separately, and the rule merging and elimination operation is performed to determine the minimum rule set required for matching the bottom metal of VIA with the pin metal. After the bottom metal of the VIA is matched with the pin metal, the DRC rules of the metal block after fusion and the DRC rules of the metal block before fusion are merged and resolved to obtain the above VIA generation rules.

[0009] In a feasible implementation manner, the above rule merging and resolution operation includes a logical operation and a geometric operation.

[0010] In a feasible implementation, the three-dimensional DRC evaluation value is generated based on the routing direction and quantity that the candidate coordinates can carry, the DRC violation information caused by the routing, and the DRC violation information caused by the combined metal shape.

[0011] In a feasible implementation, the three-dimensional design rule checking rules are obtained by performing an expansion operation based on the current design rule checking rules in the LEF file, and the expansion operation includes a first expansion operation and a second expansion operation. The first expansion operation is performed based on expert knowledge and logical combination and resolution operations, and the second expansion operation is generated based on known prediction values ​​through an optimization algorithm that satisfies the confidence interval setting. The optimization algorithm includes a linear programming method, a genetic algorithm, a simulated annealing algorithm, and an artificial intelligence-generated content domain-specific model.

[0012] In a feasible implementation, the above-mentioned target optimization algorithm includes one or more of quick sort, binary tree, multi-objective optimization and linear programming.

[0013] In a second aspect, the present application proposes a FinFET process STD Cell pin adaptive selection device, comprising: A preprocessing unit, used for performing a preprocessing operation on the basic design rule checking data to calculate and obtain engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule checking rules and three-dimensional design rule checking rules; A front-end design unit, used to read a user chip design file to perform a front-end design operation and form front-end design data, wherein the front-end design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; A first generating unit is used to generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the above-mentioned 3D design rule checking rules, the above-mentioned physical information, the above-mentioned logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; A second generating unit is used to perform a physical information matching operation based on a geometric operation according to a VIA generation rule, pre-generated VIA information and the above-mentioned pin physical information to generate combined data with a three-dimensional DRC evaluation value, wherein the above-mentioned combined data includes a candidate coordinate value, a three-dimensional DRC evaluation value corresponding to the above-mentioned candidate coordinate, a DRC evaluation value of the candidate coordinate and the VIA information; An optimization unit, used to perform an optimization operation using a target optimal algorithm according to the three-dimensional DRC evaluation value in the combined data to determine the most optimized combined data and its sequence; The wiring unit is used to perform wiring access operations based on the above-mentioned optimized combination data and its sequence to generate constrained six-degree-of-freedom wiring information.

[0014] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of the FinFET process STDCell pin adaptive selection method as described in any one of the above-mentioned first aspects when executing the computer program stored in the memory.

[0015] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the FinFET process STD Cell pin adaptive selection method of any one of the first aspects is implemented.

[0016] In summary, this method identifies and parses the complex rules in the FinFET process through preprocessing operations on standard file formats such as LEF and Lib, and generates two-dimensional design rule checking and three-dimensional design rule checking rules. Expert knowledge, logical combination and resolution operations are used to predict known rules, and potential rules are inferred by combining linear programming, genetic algorithms, simulated annealing and other algorithms, and stored in the rule engine database to ensure the comprehensiveness and efficiency of the rules. According to the physical information of the metal layer where the pin is located and the wiring track grid information, the three-dimensional space candidate coordinates are automatically generated, and the three-dimensional DRC evaluation value is generated by combining the wiring direction, wiring quantity and DRC violation information. Using multiple target optimal algorithms such as quick sorting, binary tree, multi-objective optimization and linear programming, efficient optimization of candidate data under rule constraints is achieved, providing the best reference for subsequent wiring. Through the physical size and logical network information of STDCell, the pin access mode is generated to provide the optimal access order for the automatic routing algorithm, significantly reducing the wiring complexity. Each pin of each STDCell is evaluated and a set of evaluation values ​​is generated. Sorting and screening are used to ensure that the optimal coordinates are given priority when selecting pins. It supports multiple mask technology in FinFET process and adopts six degrees of freedom routing (including X, Y, Z directions and rotational degrees of freedom) to significantly improve routing flexibility. The three-dimensional DRC evaluation value generated by preprocessing can significantly reduce the congestion and violations that may occur during the routing process, and reduce the rework cost in subsequent DRC inspections. The target optimal algorithm flexibly selects methods such as quick sorting, binary tree, multi-objective optimization and linear programming, and automatically switches or combines according to different scenarios to balance multi-objective requirements such as routing density, performance, and DRC compliance. Rules and data support a variety of storage structures (such as lists, queues, stacks, etc.) to adapt to different computing needs and improve the efficiency of algorithm operation. The method proposed in this application significantly reduces design time and labor costs through full process automation from rule preprocessing to optimization to routing generation. The optimization selection based on the evaluation value and multi-degree-of-freedom support during the routing process ensure the reliability and electrical performance of the routing, and can adapt to the high requirements of the FinFET process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of the process of an adaptive selection method for STD Cell pins of a FinFET process provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a FinFET process STD Cell pin adaptive selection device provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a FinFET process STD Cell pin adaptive selection electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0019] See also Figure 1 , is a schematic diagram of a process of an adaptive selection method for STD Cell pins of a FinFET process provided in an embodiment of the present application, the method comprising: S110, performing a preprocessing operation on the basic design rule check data to calculate and obtain engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; For example, the basic design rule check data can be obtained through standard file formats such as LEF (Library Exchange Format) and Lib (Library File) provided by the wafer factory. The file format follows the LEF54\LEF55\LEF58 standards. Then identify the rules of mature processes and FinFET (FinField-Effect Transistor) processes, where mature processes use binary groups to identify and store rules. For the rules of FinFET processes, it is also necessary to infer three-dimensional DRC rules based on the limited DRC (DesignRule Check) rules in the LEF file. For example: For simple prediction values, they are obtained based on expert knowledge combined with logical combination and resolution operations. For potential unknown prediction values, they are obtained based on known prediction values ​​through an optimization algorithm that satisfies the confidence interval setting. The above-mentioned optimal algorithms include linear programming, genetic algorithms, simulated annealing, and AIGC (Artificial Intelligence Generated Content) field-specific models as support. The DRC rules after preprocessing and operation are stored in the rule engine rule database TechDatabase through an N-layer binary tree storage. The computer storage methods include but are not limited to lists, vectors, tuples, queues, stacks, objects, etc. for use in subsequent processes.

[0020] S120, reading the user chip design file to perform a pre-design operation to form pre-design data, wherein the pre-design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; Exemplarily, the STDCell (Standard Cell) pin information in the user chip design file is read, including the design source file, i.e., HDL (Hardware Description Language), Verilog (Verilog Hardware Description Language), etc., SDC file (Synopsys Design Constraints), and chip design parameters. The chip design parameters include, but are not limited to: area, coordinates, voltage, capacitance, RC (Resistance and Capacitance), utilization, clock cycle, TNS (Total Negative Slack), WNS (Worst Negative Slack), number of DRC violations, and specific STDCells that need to be specified. Specific STDCells include, but are not limited to, buffer BUFFERCell, Filler Cell, Tie Hi Cell, Tie LoCell, and through-hole files that need to be specified. After obtaining the above design information, the pre-processing process forms the front-end design data and stores it in the front-end design database DesignDatabase, which includes the network Net composed of all signal paths. The network includes the STDCell pins on all network paths, as well as all other information related to the design. The data in the database is stored in the computer in the form of lists, vectors, tuples, queues, stacks, objects, etc. for use in subsequent processes. The information of the STDCell pins is extracted from the front-end design database DesignDatabase. The information of the STDCell pins includes the STDCell information corresponding to the pins, the physical information such as the pin name, size, coordinates, etc., the logical network information between the pins, and the evaluation value of the pin access point. The STDCell pin information can be stored in a priority queue.

[0021] S130, generating a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the above-mentioned 3D design rule check rule, the above-mentioned physical information, the above-mentioned logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generating a 3D DRC evaluation value corresponding to each candidate coordinate; Exemplarily, according to the above-mentioned three-dimensional design rule checking rules, the above-mentioned physical information, the above-mentioned logical network information and the 3D wiring track grid information covered by the metal layer where the pin is located, a 3D space candidate VIA access point coordinate set of the metal layer where the pin is located is generated. The 3D space candidate coordinates in the 3D space candidate VIA access point coordinate set include both the physical relative coordinates of the chip on the actual wafer and the node coordinates of the logical wiring track. According to the wiring direction and quantity that the coordinate can carry and the DRC violation information caused by the wiring, a comprehensive pre-judgment is performed to generate a 3D (three-dimensional) DRC evaluation value for each candidate coordinate. The above-mentioned evaluation is performed for each pin of each STDCell and a set of evaluation value sets corresponding to the STDCell is generated. The pin access mode of the STDCell is established according to the size information of the STDCell. This mode provides an optimal access sequence for the subsequent automatic wiring algorithm to select pins.

[0022] S140, performing a physical information matching operation based on geometric operations according to VIA generation rules, pre-generated VIA information and the above-mentioned pin physical information to generate combined data with three-dimensional DRC evaluation values, wherein the above-mentioned combined data includes candidate coordinate values, three-dimensional DRC evaluation values ​​corresponding to the above-mentioned candidate coordinates, DRC evaluation values ​​of the candidate coordinates and VIA information; Exemplarily, according to the VIA generation rules and pre-generated VIA information, geometric operations (intersection, union, projection distance, Manhattan distance, Euclidean distance, etc.) are performed with the corresponding pin physical information to realize its physical information matching operation, and the pin information is associated with the 3DDRC evaluation value to complete the combination of pins, access point coordinates, and VIA with DRC constraint evaluation values.

[0023] S150, performing an optimization operation using a target optimal algorithm according to the three-dimensional DRC evaluation value in the combined data to determine the most optimized combined data and its sequence; Exemplarily, after the target optimal algorithm optimizes the combined data, the subsequent automatic routing algorithm accesses the pins. Since the combined data has three-dimensional evaluation value information, it ensures that the pin coordinates can be selected by the automatic routing algorithm when the pins are selected. The computer storage methods include lists, vectors, tuples, queues, stacks, objects, etc. for subsequent processes. The target optimal algorithms include quick sort, binary tree, multi-objective optimization, linear programming, etc.

[0024] S160 , performing a wiring access operation based on the above-mentioned optimized combination data to generate wiring information with six degrees of freedom with constraints.

[0025] For example, for the multi-mask process technology used in FinFET, the metal layer wiring is supported to perform wiring access operations in 6 degrees of freedom (i.e., the X, Y, and Z directions in 3D space, and the corresponding rotational degrees of freedom), and 6 degrees of freedom access options are given for each set of access point coordinates. Each access option needs to be sorted according to the 3D DRC evaluation value of the coordinate to meet the wiring algorithm's need for optimal selection of access points. This function effectively solves the wiring direction restrictions introduced by multiple masks in traditional wiring methods, significantly reduces congestion, and uses pre-processed 3D DRC evaluation values, so that potential DRC violations are greatly reduced during the DRC inspection process after the subsequent wiring is completed.

[0026] In summary, this method identifies and parses the complex rules in the FinFET process through preprocessing operations on standard file formats such as LEF and Lib, and generates two-dimensional design rule checking and three-dimensional design rule checking rules. Expert knowledge, logical combination and resolution operations are used to predict known rules, and potential rules are inferred by combining linear programming, genetic algorithms, simulated annealing and other algorithms, and stored in the rule engine database to ensure the comprehensiveness and efficiency of the rules. According to the physical information of the metal layer where the pin is located and the wiring track grid information, the three-dimensional space candidate coordinates are automatically generated, and the three-dimensional DRC evaluation value is generated by combining the wiring direction, wiring quantity and DRC violation information. Using multiple target optimal algorithms such as quick sorting, binary tree, multi-objective optimization and linear programming, efficient optimization of candidate data under rule constraints is achieved, providing the best reference for subsequent wiring. Through the physical size and logical network information of STDCell, the pin access mode is generated to provide the optimal access order for the automatic routing algorithm, significantly reducing the wiring complexity. Each pin of each STDCell is evaluated and a set of evaluation values ​​is generated. Sorting and screening are used to ensure that the optimal coordinates are given priority when selecting pins. It supports multiple mask technology in FinFET process and adopts six degrees of freedom routing (including X, Y, Z directions and rotational degrees of freedom) to significantly improve routing flexibility. The three-dimensional DRC evaluation value generated by preprocessing can significantly reduce the congestion and violations that may occur during the routing process, and reduce the rework cost in subsequent DRC inspections. The target optimal algorithm flexibly selects methods such as quick sorting, binary tree, multi-objective optimization and linear programming, and automatically switches or combines according to different scenarios to balance multi-objective requirements such as routing density, performance, and DRC compliance. Rules and data support a variety of storage structures (such as lists, queues, stacks, etc.) to adapt to different computing needs and improve the efficiency of algorithm operation. The method proposed in this application significantly reduces design time and labor costs through full process automation from rule preprocessing to optimization to routing generation. The optimization selection based on the evaluation value and multi-degree-of-freedom support during the routing process ensure the reliability and electrical performance of the routing, and can adapt to the high requirements of the FinFET process.

[0027] In some examples, the method further includes: According to the above-mentioned optimized combination data, VIA position and type, multi-layer metal spacing rules and constraints between upper and lower VIA layers, a three-dimensional DRC rule determination operation is performed, and an evaluation value is calculated according to a multi-dimensional linear prediction function to correct the above-mentioned three-dimensional DRC evaluation value.

[0028] Exemplarily, 3D BlockBox can be introduced in this step. 3D BlockBox is a three-dimensional space constraint engine for processing multi-layer metal and VIA layout rules. In the complex situation of multiple metal layers and multiple condition judgments, it realizes rapid evaluation through the following steps. Locate the access point coordinates, that is, determine the location where the VIA is placed, which is the starting point for 3D rule judgment. Determine the VIA information, which includes the size and type of the VIA, as well as the metal layer and target connection layer where it is located. Call TechDatabase, which contains technical rules, including specific rules such as the spacing requirements between upper and lower adjacent metal layers and upper and lower adjacent VIA layers.

[0029] According to the information provided by TechDatabase, rule determination is performed in 3D space. Multi-metal layer spacing rule detection, specifically: verifying the spacing requirements of the upper and lower metal layers to ensure that the minimum spacing rules of the manufacturing process are met. Constraint checks between upper and lower VIA layers include: calculating the actual spacing between the VIA layer and its adjacent VIA layer to determine whether it meets the process rules. Multi-layer metal spacing rules include: integrating the combined constraints of multi-layer metal and VIA to ensure that the rule determination is comprehensive and accurate.

[0030] To further optimize the spacing determination and layout of VIA, a multidimensional linear prediction function is used to calculate the 3D DRC evaluation value. The input variables include access point coordinates, upper and lower layer spacing, VIA type, multi-layer metal spacing rules, and constraints between upper and lower VIA layers. The importance of each rule is quantified using a multidimensional linear prediction function combined with a weight parameter to generate a comprehensive evaluation value. The results of the 3D DRC are dynamically adjusted based on the evaluation value calculated in this step to avoid rule omissions or overly conservative routing strategies.

[0031] Through the method provided in this embodiment, 3D BlockBox can predict and avoid possible rule conflicts in advance when generating VIA placement coordinates. Ensure that the selected coordinates can meet all rules and reduce the complexity of subsequent manual adjustments. Engineers can directly use VIA layouts that have passed 3D DRC evaluation to reduce iteration time. Avoid VIA layouts that violate process rules and reduce the risk of failure in manufacturing.

[0032] In some examples, the method further includes: Before the bottom metal of VIA is matched with the pin metal, the DRC rules of each metal are processed separately, and the rule merging and elimination operation is performed to determine the minimum rule set required for matching the bottom metal of VIA with the pin metal. When the bottom metal of the VIA is matched with the pin metal, the DRC rules of the metal block after fusion and the DRC rules of the metal block before fusion are merged and resolved to obtain the above VIA generation rules.

[0033] In some examples, the rule merging and resolving operations include logical operations and geometric operations.

[0034] Exemplarily, when the bottom metal of VIA has not yet been matched with the pin metal, the DRC rules of the bottom metal and the pin metal are analyzed and processed respectively. The independent rules of each metal are merged, and the repeated, redundant or contradictory rules are eliminated to generate a minimized rule set. The purpose of this step is to simplify the DRC rules and improve the efficiency of subsequent design. Determine the minimum rule set required for VIA matching to lay the foundation for the next metal matching operation.

[0035] In chip design, VIA and its connected underlying metal and pin metal need to follow complex design rule checks (DRC). When these metal areas are matched and merged into a whole, that is, when the underlying metal of VIA and the pin metal are matched, there may be overlaps or conflicts between the rules, so it is necessary to merge and resolve the DRC rules of the metal block after fusion and the DRC rules of the metal block before fusion to achieve rule unification and optimization.

[0036] When the underlying metal of the VIA and the pin metal complete geometric or functional matching, a new fused metal block is formed. The fused metal block needs to simultaneously meet the DRC rules corresponding to the fused metal block and all independent DRC rules of the metal block before fusion. These DRC rules include but are not limited to process requirements such as size, spacing, and shape.

[0037] In order to avoid repeated and conflicting rules from interfering with the design process, rule resolution technology is used to simplify multiple rules into a unified rule set, which can be resolved by combining logical operations and set operations.

[0038] Logical operations are used to process the logical relationship of rule attributes. AND operations can be used to combine rules that must be satisfied at the same time. For example, VIA and minimum spacing of metal blocks are applicable at the same time. OR operations can be used to process rules that can satisfy either of them. For example, compatible rule selection under different processes is allowed. NOT operations can exclude unnecessary rules or specific conditions. XOR operations select one between mutually exclusive rules, such as when the process requires exception handling for a special case.

[0039] Geometric operations are used to handle the spatial relationships and constraints between metal blocks. Intersection can be used to calculate the common area of ​​metal block rules before merging, retaining the necessary overlapping rules. Union can be used to merge the valid areas of all metal block rules to cover all possible design ranges. Projection distance can measure the constraints of rules in a specific direction, such as horizontal or vertical spacing requirements. Manhattan distance can measure spacing using path length and is suitable for gridded design rules. Euclidean distance can directly measure the shortest distance between two points for accurate calculation.

[0040] For completely identical rules (such as the same minimum spacing), they are directly merged into a single rule. In the case of rule conflicts, the higher priority rule can override the lower priority rule according to the rule priority. It is also possible to generate a compromise rule through logical operations (such as taking the maximum spacing or the most relaxed restrictions). In the special case of rule conflicts, it is also possible to combine multi-dimensional evaluation functions to dynamically optimize the rule parameters.

[0041] The unified rule set generated after rule merging and resolution can be seamlessly integrated into the rapid evaluation module, avoiding the impact of multiple checks on evaluation efficiency, ensuring that all rules are consistently applicable without omissions or conflicts, and efficiently handling rule constraints in multi-layer metal and multi-VIA layouts.

[0042] For example, the width of the VIA bottom metal is 3nm, while the minimum width of the pin metal is 5nm. When the rules are merged, the intersection of the rules is determined to be 5nm (a stricter restriction) through logical operations. If there are conflicting rules (such as a requirement of less than 5nm in a certain direction), it is adjusted to 5nm through geometric calculations. Ultimately, it is used to determine whether the subsequent VIA layout meets the overall rules.

[0043] The merging and elimination function of multiple DRC rules for pins and VIAs proposed in the embodiment of the present application effectively integrates independent rules before fusion through logical operations and geometric operations, providing an optimized rule set for the rapid evaluation module. This method not only improves the efficiency of rule adaptation, but also significantly reduces the risk of design conflicts, ensuring that the layout design meets the complex requirements of the manufacturing process.

[0044] In some examples, the three-dimensional DRC evaluation value is generated based on the routing direction, quantity, DRC violation information caused by the routing, and DRC violation information caused by the combined metal shape that the candidate coordinates can carry.

[0045] For example, in chip design, the 3D DRC evaluation value is an important indicator for evaluating whether a candidate coordinate meets the design rule (DRC) requirements in a 3D layout. It generates routing direction, routing quantity, and DRC violation information that may be caused by routing based on the candidate coordinates. The 3D DRC evaluation value is a numerical quantitative indicator used to measure the ability of a candidate coordinate to carry routing while meeting the design rules. The lower the evaluation value, the more likely the location is to generate DRC violations, and the higher the evaluation value, the more suitable the location is for routing.

[0046] Routing in different directions (horizontal, vertical, diagonal) may be subject to different rules, such as spacing requirements, crossing restrictions, etc. The restrictions on routing direction directly affect the availability of candidate coordinates.

[0047] The number of routes a candidate coordinate can carry is affected by the space resources around it. Coordinates with lower number of routes may be more likely to cause conflicts or violations.

[0048] DRC violation information includes the type of rule violation, such as insufficient spacing, overlap, overcrowding, etc. The severity of the violation can have a significant impact on the assessment value.

[0049] Specifically, the evaluation value can be determined by the following methods: S210, initializing candidate coordinates: selecting a candidate coordinate as a routing evaluation object.

[0050] S220, Direction and quantity analysis: Calculate the availability of the routing of the coordinate in different directions and count the number of routings that can be supported.

[0051] S230, Violation Analysis: Check the type and number of DRC violations that may be caused by routing.

[0052] S240. Calculate comprehensive evaluation value: Calculate the evaluation value comprehensively based on direction, quantity and violation information.

[0053] Assume that the 3D DRC evaluation value of the candidate coordinates is , can be calculated by the following formula: in: is the comprehensive availability score of the wiring direction (the value range is as follows , higher values ​​indicate better directional availability). is the number of routings supported by the candidate coordinates. is the comprehensive severity score of the DRC violation (the range is as follows , with higher values ​​indicating more severe violations). are weight factors for direction, quantity, and violation, satisfying , designers can adjust according to actual needs.

[0054] (1) Comprehensive availability score of the wiring direction The routing restrictions in different directions can be calculated based on the candidate coordinates: For direction Wiring availability (such as score). is the total number of directions (such as horizontal, vertical, diagonal, etc.).

[0055] (2) Number of routing paths supported by candidate coordinates It can be calculated by counting the idle resources around the candidate coordinates: (3) Overall severity score of DRC violations Based on the type and number of violations, a composite severity score can be calculated: Violation Type Severity score (e.g. score). Violation Type Frequency of occurrence.

[0056] By selecting the high-scoring candidate coordinates corresponding to the 3D DRC evaluation value through the evaluation value, the routing efficiency can be improved. The low-scoring candidate coordinates can be modified or excluded to reduce the risk of DRC violation. Dynamically adjust according to specific design requirements The 3D DRC evaluation value provides a quantitative way to guide layout optimization by comprehensively considering the routing direction, quantity, and violation information. Its formula and weight factors are flexible and adjustable, suitable for design scenarios of different complexity.

[0057] In some examples, the above-mentioned three-dimensional design rule checking rules are obtained by performing expansion operations based on the current design rule checking rules in the LEF file, and the above-mentioned expansion operations include a first expansion operation and a second expansion operation. The above-mentioned first expansion operation is based on expert knowledge and logical combination and resolution operations, and the above-mentioned second expansion operation is generated based on known prediction values ​​through an optimization algorithm that meets the confidence interval setting. The above-mentioned optimization algorithms include linear programming methods, genetic algorithms, simulated annealing algorithms, and artificial intelligence-generated content domain-specific models.

[0058] Exemplarily, the expansion of 3D design rule checking rules (DRC rules) is performed in two different ways, with the goal of better predicting and handling complex 3D routing rules in the automatic routing process, especially in advanced processes such as FinFET. These expansion operations are based on the design rules provided in the LEF file, combined with expert knowledge and optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence generation models, to improve the accuracy and efficiency of design rule checking.

[0059] LEF (Library Exchange Format) file is one of the standard file formats in IC design, which is used to describe standard cell layout information and wiring rules. LEF file contains basic design rules for manufacturing process, such as metal layer width, spacing, via size and spacing, etc. These rules provide the initial two-dimensional design rule checking framework, and with the increase of process complexity, especially the introduction of three-dimensional FinFET process, traditional two-dimensional design rules need to be expanded and enhanced to meet the requirements of three-dimensional wiring.

[0060] The first expansion operation is based on expert knowledge and logical combination and resolution operations. In the first expansion operation, the expert's expertise is the core part of the expansion rules. Based on years of experience and specific manufacturing processes, experts propose additional design rules that may not be clearly defined in the LEF file. These rules usually involve interference between cross-layer metal lines, signal integrity requirements, and best practices for via layout. Logical combination refers to the combination through logical reasoning based on the rules defined by experts. For example, if rule A and rule B exist at the same time, a new rule C is generated to handle more complex situations. Logical combination can help deal with the interaction between different metal layers.

[0061] The resolution operation is used to eliminate conflicting or redundant rules. In complex 3D designs, multiple rules may conflict or repeat. The resolution operation can delete or simplify these rules through mathematical or logical operations to ensure that the final DRC rules are consistent and efficient.

[0062] Through the combination of these expert knowledge and logical operations, the first expansion operation can generate a more flexible and practical set of three-dimensional design rules to adapt to the complex FinFET process environment.

[0063] The second expansion operation is based on a domain-specific optimization algorithm, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, which are used to predict and generate new design rules. This model is trained with a large amount of historical data, including previous design rule check results, predicted values, and other related wiring information. When designing, some design rules and wiring information are already known, which can be used as input data to provide to the optimization algorithm, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models to predict more unknown design rules.

[0064] Confidence intervals are used to measure the reliability of predictions from optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models. When the model generates new design rules, confidence intervals provide a measure to ensure that these predictions are based on sufficiently reliable data and reasonable speculation. If the confidence interval is too large, it means that the model's predictions may have greater uncertainty, while a smaller confidence interval indicates that the predictions are more accurate.

[0065] Based on known prediction values ​​and confidence intervals, optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models can generate new 3D design rules, especially in complex cross-layer wiring or via distribution situations. These rules may be difficult to accurately define with human experience, but through optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, more reasonable expansion results can be obtained. This approach can make up for the limitations of expert knowledge, especially when faced with large amounts of data or extremely complex designs.

[0066] In the actual design process, the first expansion operation and the second expansion operation can complement each other. Expert knowledge and logical operations can ensure the basic rationality of the rules and handle common complex situations in design, while optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence generation models, further supplement and optimize the rules through big data prediction and analysis.

[0067] The extended rules can better cope with complex 3D design scenarios, especially the 3D rule checking of cross-layer wiring in FinFET process nodes. In the actual design process, the tool will perform design rule checking and evaluation based on these extended rules to ensure that the design meets the requirements of the manufacturing process and avoid rework caused by rule violations.

[0068] The method proposed in the embodiment of the present application enhances the basic design rule checking capability in the LEF file through two extension operations. The first extension operation relies on expert knowledge, logical combination and resolution operations to generate more flexible and applicable design rules; the second extension operation uses optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, to generate more complex three-dimensional design rules using known prediction values ​​and confidence intervals. The combination of the two effectively improves the accuracy and efficiency of design rule checking, especially in three-dimensional process environments such as FinFET, ensuring that the final design meets manufacturing requirements.

[0069] In some examples, the target optimization algorithm includes one or more of quick sort, binary tree, multi-objective optimization, and linear programming.

[0070] Exemplarily, after the target optimal algorithm optimizes the combined data, the subsequent automatic routing algorithm accesses the pins. Since the combined data has three-dimensional evaluation value information, it ensures that the pin coordinates can be selected by the automatic routing algorithm when the pins are selected. The target optimal algorithm includes quick sort, binary tree, multi-objective optimization, linear programming, etc.

[0071] It should be noted that, based on the pin access point DRC pre-check of the distributed DRC rule engine, the number of CPU Cores of the software running environment can be obtained, and the entire DesignDatabase can be divided according to the number of CPU Cores. The divided DesignDatabase is allocated to each CPU Core to run the above method, and the overall design is merged in the shared area after the parallel operation is completed.

[0072] In summary, this method realizes the DRC rule preprocessing function of the metal layer of the STDCell pin, and can support the complex three-dimensional design rules of the FinFET process, including rule analysis, merging and splitting across multiple metal layers and via layers. Through rule resolution and logical combination technology, undefined three-dimensional DRC rules are predicted and improved to solve the limitation that the traditional 2D rule engine cannot recognize 3D rules. According to the three-dimensional DRC evaluation value, a set of access point candidates is established for each pin of each STDCell to form an evaluation value list. The access point set is sorted and the optimal pin is selected first to avoid DRC violations and congestion problems in the subsequent routing process. It supports automatic generation of undefined VIAs in LEF files, which can solve the difficulties of manual operations in nano-level design and greatly improve design efficiency. Six-degree-of-freedom routing is supported in the metal layer of the FinFET process, including three directions of X, Y, and Z and rotational freedom. The waste of routing resources caused by direction restrictions in traditional routing methods is significantly reduced, and the routing resources of low-level metal layers are released. By releasing massive routing resources, the routing congestion of low-level metal layers is greatly reduced, and the scalability of chip design is improved. Before selecting the pin access point, DRC preprocessing is used to generate candidate access points that meet the rules, significantly reducing the occurrence of violations in the subsequent routing steps. An integrated distributed DRC engine can also be used to pre-check violations when generating pin access points to avoid potential violations in advance. The rule optimization and pre-checking functions reduce the cost of violation discovery and rework in the subsequent unified DRC inspection process. STDCell pin generation, adaptive selection and subsequent detailed routing design steps are seamlessly connected to form an efficient and integrated design tool chain. The combination of distributed computing and automated algorithms greatly improves design efficiency and can be applied to ultra-large-scale chip design tasks. In view of the characteristics of multiple mask technology in FinFET process, the support for routing access point selection and routing direction is optimized. Avoid the waste of resources caused by the single routing direction in multiple mask technology, and improve the routing density and design flexibility. Through automated pin selection and routing access point generation, the inefficiency caused by manual adjustment is avoided and the design cycle is shortened. It can solve DRC violations through preprocessing and pre-checking in the early stage of design, greatly reduce the number of violations in subsequent DRC checks, and improve the overall design accuracy. Applicable to 32nm and below processes, this method is designed for FinFET processes and solves the complex issues of standard cell pin selection and wiring in advanced processes. By optimizing design rules and improving wiring resource utilization, it supports high-density, high-performance chip design requirements.

[0073] In the second aspect, the present application also proposes a FinFET process STDCell pin adaptive selection device, such as Figure 2 As shown, including: A preprocessing unit 21 is used to perform a preprocessing operation on the basic design rule checking data to calculate the engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule checking rules and three-dimensional design rule checking rules; A pre-design unit 22 is used to read the user chip design file to perform pre-design operations and form pre-design data, wherein the pre-design data includes pin data of the standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; The first generating unit 23 is used to generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the above-mentioned 3D design rule checking rules, the above-mentioned physical information, the above-mentioned logical network information and the 3D wiring track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; The second generating unit 24 is used to perform a physical information matching operation based on a geometric operation according to the VIA generation rule, the pre-generated VIA information and the above-mentioned pin physical information to generate combined data with a three-dimensional DRC evaluation value, wherein the above-mentioned combined data includes a candidate coordinate value, a three-dimensional DRC evaluation value corresponding to the above-mentioned candidate coordinate, a DRC evaluation value of the candidate coordinate and the VIA information; An optimization unit 25 is used to perform an optimization operation using a target optimal algorithm according to the three-dimensional DRC evaluation value in the combined data to determine the most optimized combined data and its sequence; The wiring unit 26 is used to perform wiring access operations based on the above-mentioned optimized combination data and the sequence thereof to generate constrained six-degree-of-freedom wiring information.

[0074] The above-mentioned FinFET process STDCell pin adaptive selection device can also perform the following steps: Preprocessing the basic design rule check data to calculate engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; Reading a user chip design file to perform a pre-design operation to form pre-design data, wherein the pre-design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; Generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the above-mentioned 3D design rule check rules, the above-mentioned physical information, the above-mentioned logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; Performing a physical information matching operation based on geometric operations according to VIA generation rules, pre-generated VIA information and the above-mentioned pin physical information to generate combined data with three-dimensional DRC evaluation values, wherein the above-mentioned combined data includes candidate coordinate values, three-dimensional DRC evaluation values ​​corresponding to the above-mentioned candidate coordinates, DRC evaluation values ​​of the candidate coordinates and VIA information; According to the three-dimensional DRC evaluation values ​​in the combined data, an optimization operation is performed using a target optimal algorithm to determine the most optimized combined data and its sequence; A wiring access operation is performed based on the above-mentioned optimized combination data and its sequence to generate wiring information with six degrees of freedom with constraints.

[0075] In a feasible implementation, it also includes: According to the above-mentioned optimized combination data, VIA position and type, multi-layer metal spacing rules and constraints between upper and lower VIA layers, a three-dimensional DRC rule determination operation is performed, and an evaluation value is calculated according to a multi-dimensional linear prediction function to correct the above-mentioned three-dimensional DRC evaluation value.

[0076] In a feasible implementation, it also includes: Before the bottom metal of VIA is matched with the pin metal, the DRC rules of each metal are processed separately, and the rule merging and elimination operation is performed to determine the minimum rule set required for matching the bottom metal of VIA with the pin metal. After the bottom metal of the VIA is matched with the pin metal, the DRC rules of the metal block after fusion and the DRC rules of the metal block before fusion are merged and resolved to obtain the above VIA generation rules.

[0077] In a feasible implementation manner, the above rule merging and resolution operation includes a logical operation and a geometric operation.

[0078] In a feasible implementation, the three-dimensional DRC evaluation value is generated based on the routing direction and quantity that the candidate coordinates can carry, the DRC violation information caused by the routing, and the DRC violation information caused by the combined metal shape.

[0079] In a feasible implementation, the three-dimensional design rule checking rules are obtained by performing an expansion operation based on the current design rule checking rules in the LEF file, and the expansion operation includes a first expansion operation and a second expansion operation. The first expansion operation is performed based on expert knowledge and logical combination and resolution operations, and the second expansion operation is generated based on known prediction values ​​through an optimization algorithm that satisfies the confidence interval setting. The optimization algorithm includes a linear programming method, a genetic algorithm, a simulated annealing algorithm, and an artificial intelligence-generated content domain-specific model.

[0080] In a feasible implementation, the above-mentioned target optimization algorithm includes one or more of quick sort, binary tree, multi-objective optimization and linear programming.

[0081] In summary, this device realizes the DRC rule preprocessing function of the metal layer of the STDCell pin, and can support the complex three-dimensional design rules of the FinFET process, including rule analysis, merging and splitting across multiple metal layers and via layers. Through rule resolution and logical combination technology, undefined three-dimensional DRC rules are predicted and improved to solve the limitation that the traditional 2D rule engine cannot recognize 3D rules. According to the three-dimensional DRC evaluation value, a candidate set of access points is established for each pin of each STDCell to form an evaluation value list. The access point set is sorted, and the optimal pin is selected first to avoid DRC violations and congestion problems in the subsequent wiring process. It supports automatic generation of undefined VIAs in LEF files, which can solve the difficulties of manual operations in nano-level design and greatly improve design efficiency. Six-degree-of-freedom wiring is supported in the metal layer of the FinFET process, including three directions of X, Y, and Z and rotational freedom. The waste of wiring resources caused by direction restrictions in traditional wiring methods is significantly reduced, and the wiring resources of low-level metal layers are released. By releasing massive wiring resources, the routing congestion of low-level metal layers is greatly reduced, and the scalability of chip design is improved. Before selecting the pin access point, DRC preprocessing is used to generate candidate access points that meet the rules, significantly reducing the occurrence of violations in the subsequent routing steps. An integrated distributed DRC engine can also be used to pre-check violations when generating pin access points to avoid potential violations in advance. The rule optimization and pre-checking functions reduce the cost of violation discovery and rework in the subsequent unified DRC inspection process. STDCell pin generation, adaptive selection and subsequent detailed routing design steps are seamlessly connected to form an efficient and integrated design tool chain. The combination of distributed computing and automated algorithms greatly improves design efficiency and can be applied to ultra-large-scale chip design tasks. In view of the characteristics of multiple mask technology in FinFET process, the support for routing access point selection and routing direction is optimized. Avoid the waste of resources caused by the single routing direction in multiple mask technology, and improve the routing density and design flexibility. Through automated pin selection and routing access point generation, the inefficiency caused by manual adjustment is avoided and the design cycle is shortened. It can solve DRC violations through preprocessing and pre-checking in the early stage of design, greatly reduce the number of violations in subsequent DRC checks, and improve the overall design accuracy. Applicable to 32nm and below processes, this method is designed for FinFET processes and solves the complex issues of standard cell pin selection and wiring in advanced processes. By optimizing design rules and improving wiring resource utilization, it supports high-density, high-performance chip design requirements.

[0082] like Figure 3As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor. When the processor 320 executes the computer program 311, the steps of any method of adaptive selection of STD Cell pins of the above-mentioned FinFET process are implemented.

[0083] Since the electronic device introduced in this embodiment is a device used to implement a FinFET process STDCell pin adaptive selection device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0084] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0085] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0086] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0087] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0088] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0090] An embodiment of the present application also provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the process of adaptive selection of FinFET process STD Cell pins in the corresponding embodiment.

[0091] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. Available media may be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)), etc.

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0093] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0094] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0096] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0097] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A FinFET process STD Cell pin adaptive selection method, characterized in that: include: Preprocessing the basic design rule check data to calculate engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; Reading a user chip design file to perform a pre-design operation to form pre-design data, wherein the pre-design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; Generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the 3D design rule check rule, the physical information, the logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; Performing a physical information matching operation based on geometric operations according to VIA generation rules, pre-generated VIA information and the pin physical information to generate combined data with three-dimensional DRC evaluation values, wherein the combined data includes candidate coordinate values, three-dimensional DRC evaluation values ​​corresponding to the candidate coordinates, DRC evaluation values ​​of the candidate coordinates and VIA information; According to the three-dimensional DRC evaluation value in the combined data, an optimization operation is performed using a target optimal algorithm to determine the most optimized combined data and its sequence; A wiring access operation is performed based on the optimized combination data and the sequence thereof to generate wiring information with six degrees of freedom with constraints.

2. The FinFET process STD Cell pin adaptive selection method according to claim 1, characterized in that: Also includes: A three-dimensional DRC rule determination operation is performed based on the optimized combination data, VIA position and type, multi-layer metal spacing rules and constraints between upper and lower VIA layers, and an evaluation value is calculated based on a multi-dimensional linear prediction function to correct the three-dimensional DRC evaluation value.

3. The FinFET process STD Cell pin adaptive selection method according to claim 2, characterized in that: Also includes: Before the bottom metal of VIA is matched with the pin metal, the DRC rules of each metal are processed separately, and the rule merging and elimination operation is performed to determine the minimum rule set required for matching the bottom metal of VIA with the pin metal; After the bottom metal of the VIA is matched with the pin metal, the DRC rules of the metal block after fusion and the DRC rules of the metal block before fusion are merged and resolved to obtain the VIA generation rules.

4. The FinFET process STD Cell pin adaptive selection method according to claim 3, characterized in that: The rule merging and resolving operation includes a logical operation and a geometric operation.

5. The FinFET process STD Cell pin adaptive selection method according to claim 1, characterized in that: The three-dimensional DRC evaluation value is generated based on the routing direction and quantity that the candidate coordinates can carry, the DRC violation information caused by the routing, and the DRC violation information caused by the combined metal shape.

6. The FinFET process STD Cell pin adaptive selection method according to claim 1, characterized in that: The three-dimensional design rule checking rules are obtained by performing an expansion operation based on the current design rule checking rules in the LEF file. The expansion operation includes a first expansion operation and a second expansion operation. The first expansion operation is performed based on expert knowledge and logical combination and resolution operations. The second expansion operation is generated based on known predicted values ​​through an optimization algorithm that satisfies a confidence interval setting. The optimization algorithm includes a linear programming method, a genetic algorithm, a simulated annealing algorithm, and an artificial intelligence-generated content domain-specific model.

7. The FinFET process STD Cell pin adaptive selection method according to claim 1, characterized in that: The target optimization algorithm includes one or more of quick sort, binary tree, multi-objective optimization and linear programming.

8. A FinFET process STD Cell pin adaptive selection device, characterized in that: include: A preprocessing unit, used for performing a preprocessing operation on the basic design rule checking data to calculate and obtain engine rule data required for the DRC rule engine, wherein the engine rule data includes two-dimensional design rule checking rules and three-dimensional design rule checking rules; A front-end design unit, used to read a user chip design file to perform a front-end design operation and form front-end design data, wherein the front-end design data includes pin data of a standard cell, and the pin data of the standard cell includes physical information corresponding to the pin and logical network information between the pins; A first generating unit, configured to generate a set of 3D spatial candidate VIA access point coordinates of the metal layer where the pin is located according to the 3D design rule checking rule, the physical information, the logical network information and the 3D routing track grid information covered by the metal layer where the pin is located, and generate a 3D DRC evaluation value corresponding to each candidate coordinate; A second generating unit is used to perform a physical information matching operation based on a geometric operation according to a VIA generation rule, pre-generated VIA information and the pin physical information to generate combined data with a three-dimensional DRC evaluation value, wherein the combined data includes a candidate coordinate value, a three-dimensional DRC evaluation value corresponding to the candidate coordinate, a DRC evaluation value of the candidate coordinate and VIA information; An optimization unit, configured to perform an optimization operation using a target optimal algorithm according to the three-dimensional DRC evaluation value in the combination data, so as to determine the most optimized combination data and its sequence; A wiring unit is used to perform wiring access operations based on the optimized combination data and the sequence thereof to generate wiring information with six degrees of freedom with constraints.

9. An electronic device, comprising: A memory and a processor, characterized in that the processor is used to implement the steps of the FinFET process STD Cell pin adaptive selection method as described in any one of claims 1 to 7 when executing the computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the FinFET process STD Cell pin adaptive selection method according to any one of claims 1 to 7 are implemented.

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