Phase interpolator including current limiting resistor and capacitor array

Abstract

The invention discloses a phase interpolator comprising a current limiting resistor and a capacitor array. In order to improve the linearity of the phase interpolator and reduce the duty ratio distortion, the phase interpolator comprises a core circuit and a buffer, the core circuit receives a first input clock and a second input clock and outputs a core clock; the buffer receives a first clock, and the output end of the buffer leads out an output clock; in addition, the core clock is connected to the first end of the current-limiting resistor, and the second end of the current-limiting resistor is connected with the input end of the capacitor array. The first clock is led out from the input end of the capacitor array. According to the invention, the linearity can be improved, the clock jitter phenomenon in the chip can be reduced, and the duty ratio distortion can also be reduced.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a phase interpolator comprising a current limiting resistor and a capacitor array. Background Art

[0002] As a key component of integrated circuits, the register clock driver (RCD) chip has the fundamental function of implementing necessary buffering and amplification processing for the address, instruction, and control signals from the memory controller. This process ensures the high fidelity and timeliness of the signal during transmission to the dynamic random access memory (DRAM), effectively suppressing signal attenuation and deformation, which is particularly important in high-density memory layouts. The data buffer (DB) chip that works in conjunction with it focuses on transferring and caching the data signal flow between the memory controller and DRAM, further consolidating the reliability and efficiency of data transmission.

[0003] The joint deployment of RCD and DB chips builds an integrated system that works together to fully cover the four key signals of memory operations - all-round buffering processing of address, command, control and data signals. It not only enhances the purity of the signal, but also greatly improves the overall performance and stability of the memory system.

[0004] In practical applications, if a memory module only embeds an RCD chip, the module is specifically referred to as a Registered Dual In-line Memory Module (RDIMM). RDIMM improves signal strength and is particularly suitable for servers and workstations with huge memory requirements. It can effectively alleviate signal conflicts and enhance system compatibility.

[0005] On the contrary, when the memory module combines the integrated solution of RCD and DB, the module is defined as a Load Reduced Dual In-line Memory Module (LRDIMM). The core design concept of LRDIMM is to use DB chips to effectively reduce the load pressure of the memory bus, so that the system can accommodate more DRAM units and operate without worrying about signal interference and power supply limitations, providing a crucial technical innovation for high-performance computing systems that aim to maximize memory expansion potential and reduce energy consumption.

[0006] The present invention is intended to be applied to a clock signal transmission path of a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) protocol.

[0007] However, in this field, how to improve the linearity of the phase interpolator and reduce the duty cycle distortion is a technical problem that needs to be solved urgently. Summary of the invention

[0008] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows: A phase interpolator comprising a current limiting resistor and a capacitor array, the phase interpolator also comprising a core circuit and a buffer; the core circuit receives a first input clock and a second input clock, and outputs a core clock; the buffer receives the first clock, and the output end of the buffer leads to the output clock; in addition, the core clock is connected to the first end of the current limiting resistor, and the second end of the current limiting resistor is connected to the input end of the capacitor array; the input end of the capacitor array leads to the first clock.

[0009] Furthermore, the buffer is an AC type buffer.

[0010] Furthermore, the capacitor array at least includes a first transmission gate, a second transmission gate, a first capacitor and a second capacitor.

[0011] Further, the first end of the first transmission gate and the first end of the second transmission gate are both input ends of the capacitor array.

[0012] Furthermore, the second end of the first transmission gate is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded; the second end of the second transmission gate is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded.

[0013] Furthermore, in the buffer, the first clock is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the third transmission gate, the second end of the third transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock.

[0014] Furthermore, the PMOS tube in the core circuit is connected to the device working voltage through a first resistor, and the NMOS tube in the core circuit is grounded through a second resistor.

[0015] Furthermore, the phase interpolator includes a plurality of core circuits, and each core circuit is powered by an independent LDO power tube.

[0016] The technical solution of the present invention has the following beneficial technical effects: (1) Improve linearity and reduce clock jitter inside the chip; (2) Reduce duty cycle distortion.

[0017] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the block diagram of the phase interpolator; Figure 2 It is the core circuit diagram of the phase interpolator of the present invention; Figure 3 It is a signal logic schematic diagram of the present invention; Figure 4 is a system block diagram of the phase interpolator of the present invention; Figure 5 It is a schematic diagram of the connection relationship between the capacitor array and the core circuit of the present invention; Figure 6 1 is a circuit diagram of a buffer according to the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0021] Figure 1 The reference clock is the input of the clock phase mixing module, and the reference clock can be the output clock from the phase-locked loop.

[0022] According to the reference clock, the clock phase mixing module outputs multiple clocks with different phases. For example, the clock phase mixing module outputs 8 clocks with different phases, and the phase difference between adjacent clocks is 45°. Then, through a multiplexer, specifically, an eight-to-two multiplexer, two adjacent clocks are selected as input signals of the core circuit.

[0023] Then, the multiplexer and the core circuit are controlled respectively through the thermometer code, and finally the core clock is output.

[0024] Figure 2 This is the core circuit diagram of the phase interpolator of the present invention. In the core circuit of the phase interpolator, the first end of the first PMOS tube P1 is connected to the device operating voltage (Voltage Drain-to-Drain, VDD), the second end of the first PMOS tube P1 is connected to the first end of the third PMOS tube P3, the second end of the third PMOS tube P3 is connected to the output node, the output node is connected to the first end of the first NMOS tube N1, the second end of the first NMOS tube N1 is connected to the first end of the third NMOS tube N3, and the second end of the third NMOS tube N3 is grounded.

[0025] In addition, the gate of the third NMOS transistor N3 and the gate of the first PMOS transistor P1 are connected to the second input clock CLK_IN2. The selection signal SEL is connected to the gate of the first NMOS transistor N1, and the inverted selection signal Connected to the gate of the third PMOS tube P3.

[0026] A first end of the second PMOS tube P2 is connected to the device operating voltage, a second end of the second PMOS tube P2 is connected to a first end of the fourth PMOS tube P4, a second end of the fourth PMOS tube P4 is connected to an output node, the output node is connected to a first end of the second NMOS tube N2, a second end of the second NMOS tube N2 is connected to a first end of the fourth NMOS tube N4, and a second end of the fourth NMOS tube N4 is grounded.

[0027] In addition, the gate of the fourth NMOS transistor N4 and the gate of the second PMOS transistor P2 are connected to the first input clock CLK_IN1. The selection signal SEL is connected to the gate of the fourth PMOS transistor P4, and the inverted selection signal Connected to the gate of the second NMOS tube N2.

[0028] The output node outputs a core clock.

[0029] Further, the selection signal SEL is a bit in a thermometer code.

[0030] In the present invention, the enable signal and the inverted enable signal are respectively used to control switches of different lines, in order to cover different frequencies, such as 1.4 GHz to 3.2 GHz.

[0031] The present invention uses the core circuit in the prior art, which has the disadvantages of high power consumption, narrow coverage, and poor linearity. In addition, the buffer after the core circuit in the prior art uses a DC buffer, and the duty cycle of the final output clock is distorted.

[0032] However, the present invention can also use a new core circuit. Figure 2 The first PMOS transistor P1 and the second PMOS transistor P2 of the core circuit shown are connected to VDD through at least the first resistor, and the third NMOS transistor N3 and the fourth NMOS transistor N4 are grounded through at least the second resistor. In other words, the PMOS transistor in the core circuit is connected to VDD through the first resistor, and the NMOS transistor in the core circuit is grounded through the second resistor. This embodiment can further improve the linearity of the core clock.

[0033] Figure 3 This is a signal logic diagram of the present invention. In the figure, VDD is the device operating voltage (Voltage Drain-to-Drain, VDD), and T is time.

[0034] The inventors have found through analysis that the factors affecting the linearity t1 of the phase interpolator are mainly: the phase difference between the two input clocks and the short-circuit time of the input clock and the slope x of the core clock.

[0035] Specifically, when the instantaneous current flowing through the phase interpolator is I1, the average current consumed is I2, and the parasitic capacitance of the phase interpolator is CL, the slope x of the core clock satisfies: .

[0036] The smaller the slope x of the core clock is, the better the linearity of the core clock is. The present invention considers improving the linearity of the core clock from two perspectives: VDD and parasitic capacitance CL.

[0037] In view of Figure 2 The disadvantages of the core circuit are: Figure 4 It is a system block diagram of the phase interpolator of the present invention, which includes current limiting resistors and capacitor arrays in addition to the core circuit.

[0038] According to the above analysis, the current limiting resistor can effectively reduce VDD, and increasing the capacitance value of the capacitor array is equivalent to increasing the CL value in the formula of the slope x of the core clock. These two methods work together to reduce the slope x of the core clock and improve the linearity of the core clock.

[0039] Specifically, the VDD of the phase interpolator can be provided by a low dropout linear regulator (LDO). The core circuit is Figure 2 The core circuit shown in FIG. 1 outputs a core clock.

[0040] The phase interpolator generally includes multiple core circuits, the outputs of which are connected together to output a core clock, while the logic control circuit outputs a thermometer code, in which one bit is used to control a core circuit.

[0041] Furthermore, in order to improve the power supply capability and the stable driving capability, an independent LDO power tube is provided for each of the multiple core circuits to power the core circuit.

[0042] The logic control circuit is common technical knowledge in this field, and usually includes a decoder, etc. The present invention is not limited to a specific form. After the core clock passes through the current limiting resistor and capacitor array, a first clock is obtained, and the first clock is finally used as the input of the buffer, and the buffer outputs the output clock.

[0043] Figure 5 The core circuit outputs a core clock, which is connected to the first end of the current limiting resistor, and the second end of the current limiting resistor is connected to the input end of the capacitor array.

[0044] The capacitor array includes a plurality of transmission gates and capacitors. For example, it includes at least two transmission gates and two capacitors, namely, a first transmission gate, a second transmission gate, a first capacitor, and a second capacitor. The first end of the first transmission gate and the first end of the second transmission gate are both input ends of the capacitor array.

[0045] The second end of the first transmission gate is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded. The second end of the second transmission gate is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded.

[0046] The input end of the capacitor array also leads out a first clock, which is used as an input signal of the buffer.

[0047] Figure 6 : is a circuit diagram of a buffer of the present invention. The input of the buffer is a first clock, the first clock is connected to the first end of the third capacitor C3, the second end of the third capacitor C3 is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the third transmission gate, the second end of the third transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock. In other words, the output end of the buffer leads to the output clock.

[0048] Due to the use of an AC type buffer, the present invention can have smaller duty cycle distortion compared to the conventional use of a DC type buffer.

[0049] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0050] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A phase interpolator comprising a current limiting resistor and a capacitor array, characterized in that: The phase interpolator also includes a core circuit and a buffer; The core circuit receives a first input clock and a second input clock, and outputs a core clock; The buffer receives a first clock, and an output terminal of the buffer leads to an output clock; also, The core clock is connected to a first end of a current limiting resistor, and a second end of the current limiting resistor is connected to an input end of a capacitor array; The first clock is led out from the input end of the capacitor array.

2. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 1, characterized in that: The buffer is an AC type buffer.

3. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 2, characterized in that: The capacitor array at least includes a first transmission gate, a second transmission gate, a first capacitor and a second capacitor.

4. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 3, characterized in that: The first end of the first transmission gate and the first end of the second transmission gate are both input ends of the capacitor array.

5. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 4, characterized in that: The second end of the first transmission gate is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded; The second end of the second transmission gate is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded.

6. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 5, characterized in that: In the buffer, the first clock is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the third transmission gate, the second end of the third transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock.

7. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 6, characterized in that: The PMOS tube in the core circuit is connected to the device working voltage through a first resistor, and the NMOS tube in the core circuit is grounded through a second resistor.

8. The phase interpolator comprising a current limiting resistor and a capacitor array according to claim 7, characterized in that: The phase interpolator includes multiple core circuits, and each core circuit is powered by an independent LDO power tube.

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