High-power-density electric automobile vehicle-mounted charger circuit

Abstract

The invention relates to a high-power-density electric automobile vehicle-mounted charger circuit which comprises an input EMI filtering module, a front-stage PFC converter, a rear-stage LLC converter, a signal sampling and control circuit and an auxiliary power supply circuit. Aiming at the electromagnetic interference challenge caused by the improvement of the switching frequency of the charger, the method comprises the following steps of: firstly, detecting the instant that the voltages of six half-bridge arms in a front-stage PFC (Power Factor Correction) converter and a rear-stage LLC (Logical Link Control) converter rapidly change, comprehensively judging whether the EMI (Electro-Magnetic Interference) of the charger exceeds a set threshold value or not, and adjusting the time delay between the switching step edges of output nodes of the six half-bridge arms; and therefore, the EMI peak value is reduced. And secondly, a gate driving circuit in the signal sampling and control circuit uses a CMTI filtering module, so that the anti-electromagnetic interference capability is improved. The scheme of the invention can be widely applied to various charger power supply systems.

Description

Technical Field

[0001] The invention relates to a high-power-density on-board charger circuit for an electric vehicle, belonging to the technical field of new energy vehicles. Background Art

[0002] One of the core bottlenecks facing the current market promotion of electric vehicles is the battery life of electric vehicles and whether the battery charging is convenient. Whether the power battery charging is convenient is subject to the development of charger technology, which is generally divided into on-board and off-board. Off-board chargers mainly use DC charging, which can realize high-power charging of power batteries. The charging power can reach 60kW to 200kW, which can meet the fast charging needs of consumers under specific circumstances. However, when charging the power battery in this way, the electric vehicle needs to drive into a specific charging station with charging piles to complete the charging. Therefore, the charging site is relatively limited, and the current number of charging stations cannot meet market demand. The on-board charger is installed inside the electric vehicle, and the output power is generally between 3.3kW and 22kW. Although the charging power is low, compared with the off-board charger, its main advantage is that it is flexible and convenient to use, and can meet the needs of home charging. Therefore, it has become one of the essential core functional modules of electric vehicles.

[0003] Since the on-board charger is installed inside the car, it is limited by its volume and mass, and its development direction is high power density and high working efficiency. In order to achieve the power density and efficiency improvement of the on-board charger, the most direct technical means is to increase the switching frequency of the power switching device. Most of the on-board chargers currently sold on the market use ordinary silicon-based MOSFET / IGBT as power switching devices, which makes the operating frequency of the converter not high, resulting in the large volume and weight of the magnetic components of the charger, and it is impossible to achieve the high power density requirements of the on-board charger. Wide bandgap power semiconductor devices represented by SiC and GaN have shown excellent switching performance. The converter based on wide bandgap power switching devices can achieve comprehensive improvements in operating frequency, conversion efficiency and converter volume compared to traditional silicon-based MOSFET / IGBT.

[0004] However, the high-frequency switching speed of wide-bandgap power switching devices also brings serious electromagnetic interference challenges, which may cause system performance degradation or even interfere with other devices. Therefore, achieving high power density improvement of on-board chargers in complex electromagnetic interference environments is an indispensable part of the design and implementation of on-board chargers, and has become a bottleneck problem in the implementation of high power density on-board chargers for electric vehicles. Summary of the invention

[0005] Based on the existing technology, the present invention aims at the electromagnetic interference problem faced in the implementation process of high power density on-board charger, and proposes a low electromagnetic interference electric vehicle high power density on-board charger circuit with high anti-interference characteristics, which has important practical significance for improving the long-term stability of the overall electric vehicle power system.

[0006] The high power density electric vehicle on-board charger circuit provided by the present invention comprises: an input EMI filter module, a front-stage PFC converter, a rear-stage LLC converter, an AC input voltage V in The rectified voltage signal is output through the input EMI filter module and connected to the first input terminal and the second input terminal of the front-stage PFC converter. The output of the front-stage PFC converter is the DC bus voltage V dc , the subsequent LLC converter converts the DC bus voltage V dc Further transformation to obtain the output DC charging voltage V out , V out The output charging current is I out ; Also includes signal sampling and control circuit and auxiliary power supply circuit;

[0007] The signal sampling and control circuit performs a control on the AC input voltage V in , the voltage and current state of the front-stage PFC converter, and the voltage and current state of the rear-stage LLC converter are sampled in real time, and the states of the power switch devices in the front-stage PFC converter and the rear-stage LLC converter are modulated and controlled respectively through the power switch control signal; the auxiliary power supply circuit is used to generate different types of power supply voltages required by various circuits in the signal sampling and control circuit;

[0008] The front-stage PFC converter includes: a first half bridge arm composed of power switch devices M1 and power switch devices M2, a second half bridge arm composed of power switch devices MQ1 and power switch devices MQ2, an inductor L, a diode D1, a diode D2, and a capacitor Cbus, wherein the capacitor Cbus is connected between two output ends of a bridge circuit composed of power switch devices M1 to M4; the output node of the first half bridge arm is V sw1 , connected to the right end of the inductor L, and also connected to the anode of the diode D1 and the cathode of the diode D2; the left end of the inductor L is connected to the first input terminal of the previous PFC converter, and the right end of the inductor L is output to the node V sw1 The current is I L ; The output node of the second half bridge arm is V sw2 , connected to the second input terminal of the previous PFC converter; the gate control signals of the power switch device M1 and the power switch device M2 are S1 and S2 respectively, and the gate control signals of the power switch device MQ1 and the power switch device MQ2 are Q1 and Q2 respectively;

[0009] The post-stage LLC converter comprises: power switch devices M3-M6 form a bridge circuit at the input end, power switch devices M7-M10 form a bridge circuit at the output end, resonant inductor Lr1, resonant capacitor Cr1, and inductor Lm are located on the primary side of transformer T, and resonant inductor Lr2 and resonant capacitor Cr2 are located on the secondary side of transformer T; the two input ends of the bridge circuit formed by power switch devices M3-M6 are connected to the two output ends of the pre-stage PFC converter; the output capacitor Cout is connected between the two output ends of the bridge circuit formed by power switch devices M7-M10;

[0010] The power switch device M3 and the power switch device M4 form a third half bridge arm, and the output node of the third half bridge arm is V sw3 ; The power switch device M5 and the power switch device M6 form a fourth half bridge arm, and the output node of the fourth half bridge arm is V sw4 ; The power switch device M7 and the power switch device M8 form the fifth half bridge arm, and the output node of the fifth half bridge arm is V sw5 ; The power switch device M9 and the power switch device M10 form the sixth half bridge arm, and the output node of the sixth half bridge arm is V sw6 ;

[0011] The gate control signals of the power switch device M3 and the power switch device M4 are S3 and S4 respectively, the gate control signals of the power switch device M5 and the power switch device M6 are S5 and S6 respectively, the gate control signals of the power switch device M7 and the power switch device M8 are S7 and S8 respectively, and the gate control signals of the power switch device M9 and the power switch device M10 are S9 and S10 respectively; the node V sw3 Connected to the left end of the resonant inductor Lr1, node V sw3 The current output to the resonant inductor Lr1 is I Lr1 , the right end of the resonant inductor Lr1 is connected to the primary side of the transformer T;

[0012] The signal sampling and control circuit performs a voltage V in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 The state and current I L ,I Lr1 and I outThe state is sampled in real time, and control signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, and S10 are processed to control the gates of power switching devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, and M10 respectively, thereby realizing modulation control of the states of the front-stage PFC converter and the post-stage LLC converter.

[0013] Specifically, the signal sampling and control circuit includes: 6 step voltage sampling circuits, 3 current sampling circuits, 3 voltage sampling circuits, a wide input voltage range ADC circuit, a charger working state control circuit, 10 wide bandgap power device drive circuits, and 2 MOSFET drive circuits;

[0014] The six step voltage sampling circuits respectively sense the output node V sw1 , the output node V of the second half bridge arm sw2 , the output node V of the third half bridge arm sw3 , the output node V of the fourth half bridge arm sw4 , the output node V of the fifth half bridge arm sw5 , the output node V of the sixth half bridge arm sw6 Real-time sampling of voltage status;

[0015] The three current sampling circuits respectively sense the current I Lr1 、Current I out 、Current I L The three voltage sampling circuits sample the AC input voltage V in , output DC charging voltage V out , DC bus voltage V dc Real-time sampling of the status;

[0016] The sampling voltages of all the sampling circuits are connected to the wide input voltage range ADC circuit, which performs analog-to-digital conversion on all the sampling voltages. in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 Convert to DV quantization code in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DVsw5 、DV sw6 , respectively, the current I Lr1 ,I out and I L Convert to quantization code DI Lr1 ,DI out and DI L ; All quantization codes enter the charger working state control circuit, and are processed to output control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10; control signals DS1 and DS2 are respectively passed through the first wide bandgap power device drive circuit and the second wide bandgap power device drive circuit to generate control signals S1 and S2; control signals DQ1 and DQ2 are respectively passed through two MOSFET drive circuits to generate control signals Q1 and Q2; control signals DS3~DS10 are respectively passed through the third wide bandgap power device drive circuit to the tenth wide bandgap power device drive circuit to generate control signals S3, S4, S5, S6, S7, S8, S9, and S10.

[0017] Specifically, the step voltage sampling circuit is composed of a voltage differential conductance circuit and a resistor proportional amplifier circuit in cascade, the resistor proportional amplifier circuit includes an operational amplifier and resistors R51, R52, R53, and R54, the input end of the voltage differential conductance circuit is connected to the sampled voltage, the output end of the voltage differential conductance circuit is connected to the negative input end and the positive input end of the operational amplifier through resistors R51 and R52 respectively, the output end of the operational amplifier is connected to the negative input end of the operational amplifier through resistor R53, and the positive input end of the operational amplifier is grounded through resistor R54; the amplification factor is proportional to R53 / ;

[0018] After using the voltage differential conduction circuit, the output node V sw1 ~V sw6 The rapid change of voltage signal will be converted into a corresponding step voltage signal, the voltage amplitude of which is similar to V sw1 ~V sw6 The switching slope is proportional to the EMI source’s energy.

[0019] The 10 wide bandgap power device drive circuits and 2 MOSFET drive circuits are all implemented by capacitor isolation gate drive circuits; the capacitor isolation gate drive circuit is functionally divided into a control chip responsible for input control signal modulation and a drive chip responsible for signal demodulation and output drive, and the two chips are coupled by 4 high-voltage capacitors to realize signal transmission between chips, and the control chip and the drive chip are packaged and integrated to obtain a capacitor isolation gate drive chip; the control chip includes an OOK modulation and transmission circuit, the OOK modulation and transmission circuit are respectively connected to an OSC generation circuit and two high-voltage capacitors, and the OOK modulation signal sent by the control chip adopts a differential mode and is coupled and transmitted to the drive chip through two high-voltage capacitors; the drive chip includes: another two high-voltage capacitors, an OOK demodulation receiving circuit, and a high-voltage output drive circuit, the OOK modulation signal is coupled and transmitted to the OOK demodulation receiving circuit through another two high-voltage capacitors, and the output of the OOK demodulation receiving circuit is then connected to the high-voltage output drive circuit, and finally the drive signal is output.

[0020] The OOK modulation transmission circuit adds a CMTI filter module at the output end of the differential OOK modulation circuit. The CMTI filter module includes a capacitor Cftp, a capacitor Cftn, a resistor Rftp, and a resistor Rftn. The output end of the differential OOK modulation circuit is respectively connected to the left end of the capacitor Cftp and the left end of the capacitor Cftn, the right end of the capacitor Cftp is connected to the upper end of the resistor Rftp and outputs a differential signal DXP, the right end of the capacitor Cftn is connected to the lower end of the resistor Rftp and outputs a differential signal DXN, the lower end of the resistor Rftp is connected to the upper end of the resistor Rftn and is grounded; the capacitor Cftp and the resistor Rftp constitute a high-pass filter input to the DXP end, and the capacitor Cftn and the resistor Rftn constitute a high-pass filter input to the DXN end; the low-frequency common-mode noise coupled to the DXP and DXN ends by the driver chip through the high-voltage capacitor will be filtered out by the two differential high-pass filters, thereby reducing the influence of common-mode interference and improving the common-mode transient immunity.

[0021] Specifically, the layout of the OOK modulation transmission circuit includes: an OOK modulation logic gate, a buffer Buff_p, a buffer Buff_n, a Cftp capacitor array, a Cftn capacitor array, an Rftp resistor array, an Rftn resistor array, and DXP and DXN signal line wiring areas;

[0022] The overall layout of the OOK modulation transmission circuit is symmetrical on the left and right. The uppermost side is the Rftp resistor array and Rftn resistor array layout area arranged horizontally, the lower center is the OOK modulation logic gate layout area, the left and right sides of the OOK modulation logic gate layout area are the buffer Buff_p layout area and the buffer Buff_n layout area respectively, the left side of the buffer Buff_p layout area is the Cftp capacitor array layout area, and the right side of the buffer Buff_n layout area is the Cftn capacitor array layout area;

[0023] DXP and DXN routing are transmitted from bottom to top in a completely symmetrical manner; the output signals of buffers Buff_p and Buff_n and DXP and DXN signals are differential pulse signals with frequencies greater than GHz. Signal routing uses 45-degree line turns, and sharp corners should be avoided at the turns of signal lines. At the same time, wide metal lines are used to reduce parasitic inductance and resistance effects;

[0024] In addition, ground shielding rings are used on the outside of all layout areas.

[0025] The charger working state control circuit includes: 12 data registers, 12 data subtractors, a charger voltage and current state comprehensive judgment processing circuit, a power switch waveform generation circuit and a memory for storing charger voltage and current signals and waveform reference data; the quantization code DV in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 ,DI Lr1 ,DI out and DI L The 12 data registers are connected to 12 data subtractors, and the 12 reference data D output by the memory are connected to 12 data subtractors. r1 ~D r12 Subtract and get 12 state margin data D re1 ~D re12 , connected to the charger voltage and current state comprehensive judgment processing circuit; the charger voltage and current state comprehensive judgment processing circuit will be based on 12 state margin data D re1 ~D re12 The mode control signal Dcon is generated by performing a comprehensive operation with the margin reference data Dref output by the memory, and the mode control signal Dcon is connected to the power switch waveform generating circuit; finally, the power switch waveform generating circuit generates control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10 according to the mode control signal Dcon and the reference waveform data Dwave output by the memory.

[0026] The mode control signal Dcon output by the charger voltage and current state comprehensive judgment processing circuit needs to include a control word reflecting characteristic parameters including output power, switching frequency, EMI, and reliability.

[0027] Through the moment when the voltage of the output node of the first to sixth half-bridge arms of the nodes changes rapidly, it is comprehensively judged whether the EMI interference of the charger exceeds the set value, and the control signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, S10 are adjusted through the charger working state control circuit to control the gates of the power switch devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, M10 respectively, so as to realize the modulation control of the states of the front-stage PFC converter and the rear-stage LLC converter;

[0028] If the EMI interference intensity exceeds the set threshold, the charger voltage and current state comprehensive judgment processing circuit will modify the EMI control word in the mode control signal Dcon, adjust the delay between the switch step edges of nodes Vsw1~Vsw6, reduce the time overlap of EMI interference sources, and thus reduce the EMI peak.

[0029] The overall working process of the present invention is as follows: after the power supply is powered on, the charger is turned on and reset; then, the charger working state control circuit outputs the initial mode control signal Dcon and the initial control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10, and the charger starts power conversion and has power output; thereafter, the signal sampling and control circuit starts to detect the current and voltage signals in the front-stage PFC converter and the rear-stage LLC converter, and digitally quantizes the detected current and voltage signals, and the state margin data obtained by subtracting the quantization code from the reference signal is the state error; the charger working state control circuit calculates the adjustment mode control signal Dcon according to the state error, and then adjusts the control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10; the charger starts to enter the normal working state.

[0030] The advantages of the present invention are: in response to the electromagnetic interference challenge brought about by the increase in the switching frequency of the charger, the present invention first detects the moment when the voltage of the six half-bridge arms in the front-stage PFC converter and the rear-stage LLC converter changes rapidly, comprehensively judges whether the EMI interference of the charger exceeds the set threshold, and adjusts the delay between the switching step edges of the six half-bridge arm output nodes, thereby reducing the EMI peak. Secondly, the gate drive circuit in the signal sampling and control circuit of the present invention uses a CMTI filter module to improve the anti-electromagnetic interference capability. The solution of the present invention can be widely used in various types of charger power supply systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a circuit structure block diagram of a high power density on-board charger for electric vehicles according to the present invention.

[0032] Figure 2 This is a block diagram of the signal sampling and control circuit of the present invention.

[0033] Figure 3 This is an embodiment of the voltage sampling circuit of the present invention.

[0034] Figure 4 This is an embodiment of the current sampling circuit of the present invention.

[0035] Figure 5 This is an embodiment of the step voltage sampling circuit of the present invention.

[0036] Figure 6 It is a schematic diagram of the working principle of the step voltage sampling circuit of the present invention.

[0037] Figure 7 It is a structural block diagram of the capacitor isolation gate driving circuit of the present invention.

[0038] Figure 8 This is a structural diagram of the high CMTIOOK modulation and transmission circuit of the present invention.

[0039] Fig. 9 It is a schematic diagram of the layout design of the high CMTIOOK modulation and transmission circuit of the present invention.

[0040] Fig.10 It is a structural block diagram of the charger working state control circuit of the present invention.

[0041] Fig.11 This is a flow chart of the charger working state control of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0043] like Figure 1 As shown, the present invention adopts a two-stage vehicle charger overall structure, including: an input EMI filter module 1, a front-stage PFC converter 2, and a rear-stage LLC converter 3. The present invention adds a signal sampling and control circuit 4 and an auxiliary power supply circuit 5 on the basis of the above-mentioned main power conversion circuit board.

[0044] AC input voltage V in Enter the input EMI filter module 1, obtain the rectified voltage signal and enter the front-stage PFC converter 2; the output of the front-stage PFC converter 2 is the DC bus voltage V dc The subsequent LLC converter 3 converts the bus voltage V dc Further transformation to obtain the output DC charging voltage V out , V out The output charging current is I out; Signal sampling and control circuit 4 for AC input voltage V in The voltage and current state of the front-stage PFC converter 2 and the voltage and current state of the rear-stage LLC converter 3 are sampled in real time, and the states of the power switch devices in the front-stage PFC converter 2 and the rear-stage LLC converter 3 are modulated and controlled respectively through the power switch control signal. The auxiliary power supply circuit 5 is used to generate different types of power supply voltages required by various circuits in the signal sampling and control circuit 4.

[0045] like Figure 1 As shown in the left dashed box, the front-stage PFC converter 2 includes an inductor L, a first half bridge arm composed of power switch devices M1 and M2, a second half bridge arm composed of power switch devices MQ1 and MQ2, diodes D1 and D2, and a capacitor Cbus. The output node of the first half bridge arm is V sw1 , connected to the right end of the inductor L, and also connected to the anode of the diode D1 and the cathode of the diode D2; the left end of the inductor L is connected to the first input terminal of the front-stage PFC converter 2, and the right end of the inductor L is output to the node V sw1 The current is I L ; The output node of the second half bridge arm is V sw2 , connected to the second input terminal of the front-stage PFC converter 2; the gate control signals of the power switch devices M1 and M2 are S1 and S2 respectively; the gate control signals of the power switch devices MQ1 and MQ2 are Q1 and Q2 respectively.

[0046] like Figure 1 As shown in the dotted line box on the right, the post-stage LLC converter 3 includes a resonant inductor Lr1, a resonant inductor Lr2, an inductor Lm, a transformer T, a resonant capacitor Cr1, a resonant capacitor Cr2, a third half bridge arm composed of power switch devices M3 and M4, a fourth half bridge arm composed of power switch devices M5 and M6, a fifth half bridge arm composed of power switch devices M7 and M8, a sixth half bridge arm composed of power switch devices M9 and M10, and an output capacitor Cout. The power switch devices M3-M6 form a bridge circuit at the input end, and the power switch devices M7-M10 form a bridge circuit at the output end. The two input ends of the bridge circuit composed of the power switch devices M3-M6 are connected to the two output ends of the pre-stage PFC converter 2; the output capacitor Cout is connected between the two output ends of the bridge circuit composed of the power switch devices M7-M10.

[0047] Among them, the output node of the third half bridge arm is V sw3 , the output node of the fourth half bridge arm is V sw4 , the output node of the fifth half bridge arm is V sw5 , the output node of the sixth half bridge arm is V sw6; The gate control signals of the power switch devices M3 and M4 are S3 and S4 respectively, the gate control signals of the power switch devices M5 and M6 are S5 and S6 respectively, the gate control signals of the power switch devices M7 and M8 are S7 and S8 respectively, and the gate control signals of the power switch devices M9 and M10 are S9 and S10 respectively; the node V sw3 Connected to the left end of the resonant inductor Lr1, node V sw3 The current output to the resonant inductor Lr1 is I Lr1 .

[0048] The signal sampling and control circuit 4 is used for voltage V in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 The state and current I L ,I Lr1 and I out The state is sampled and processed in real time to generate drive signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, S10 to control the gates of power switching devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, M10 respectively, thereby realizing modulation control of the states of the front-stage PFC converter 2 and the rear-stage LLC converter 3.

[0049] Figure 1 In the high power density electric vehicle on-board charger circuit shown, the input EMI filter module 1 is mainly used to suppress external electromagnetic interference from being transmitted to the subsequent PFC converter 2 through the mains, and can also prevent the converter's own high-frequency electromagnetic interference from entering the power grid.

[0050] The main functions of the front-stage PFC converter 2 are:

[0051] (1) Provide stable and adjustable DC voltage for the subsequent converter;

[0052] (2) Achieve power factor correction;

[0053] (3) Ensure that the charger can operate normally under non-rated conditions, such as sudden changes in grid voltage or unstable grid voltage frequency.

[0054] The main functions of the post-stage LLC converter 3 are:

[0055] (1) The DC bus voltage can be stepped up or down, and constant voltage / constant current output can be achieved to meet the charging requirements of the load;

[0056] (2) Realize electrical isolation between the power grid and the load to improve the safety performance of the system.

[0057] The signal sampling and control circuit 4 is mainly composed of a control circuit and its peripheral signal sampling circuit, and controls the on-board charger by cooperating with the sampling circuit and the driving circuit.

[0058] Figure 2 This is a block diagram of the signal sampling and control circuit 4 of the present invention, and the circuit includes: first to sixth step voltage sampling circuits, first to third current sampling circuits, first to third voltage sampling circuits, a wide input voltage range ADC circuit, a charger working state control circuit, first to tenth wide bandgap power device drive circuits, a first MOSFET drive circuit, and a second MOSFET drive circuit.

[0059] The first to sixth step voltage sampling circuits are used to sample the output node V sw1 ~V sw6 The voltage state is sampled in real time; the first current sampling circuit samples the current I Lr1 The state of the second current sampling circuit is real-time sampling of the current I out The third current sampling circuit samples the current I L The first voltage sampling circuit samples the AC input voltage V in The state is sampled in real time, and the second voltage sampling circuit samples the output DC charging voltage V out The third voltage sampling circuit samples the DC bus voltage V dc The status is sampled in real time.

[0060] The wide input voltage range ADC circuit performs analog-to-digital conversion on the sampling voltages of all the above sampling circuits, and converts the voltage V in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 Convert to DV quantization code in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 , respectively, the current I Lr1 ,I out and I LConvert to quantization code DI Lr1 ,DI out and DI L All the above quantization codes enter the charger working state control circuit, and are processed to generate gate control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10; signals DS1 and DS2 enter the first wide bandgap power device drive circuit and the second wide bandgap power device drive circuit respectively, and generate drive signals S1 and S2 respectively; signals DQ1 and DQ2 enter the first MOSFET drive circuit and the second MOSFET drive circuit respectively, and generate drive signals Q1 and Q2 respectively; signals DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10 enter the third to tenth wide bandgap power device drive circuits respectively, and generate drive signals S3, S4, S5, S6, S7, S8, S9, and S10 respectively.

[0061] Figure 2 The signal sampling and control circuit 4 given uses three voltage sampling circuits to respectively in 、V dc 、V out For sampling, 6 step voltage sampling circuits are used to sample the voltage V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 For sampling, three current sampling circuits are used to respectively sample the current I L ,I Lr1 and I out The state is sampled in real time; it is converted into quantization code DV in turn in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 ,DI Lr1 ,DI out and DI LThe charger working state control circuit generates gate control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10 according to all the above quantization codes; and then generates drive signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, and S10 through processing by the drive circuit to control the gates of power switch devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, and M10 respectively, thereby realizing modulation control of the states of the front-stage PFC converter 2 and the rear-stage LLC converter 3.

[0062] In the existing on-board charger implementation scheme, the signal sampling and control circuit usually only processes the voltage V in 、V dc 、V out And the current I Lr1 ,I out and I L Sampling is performed, and the state of the front-stage PFC converter 2 and the rear-stage LLC converter 3 in the charger is controlled according to the state of these voltage and current signals. This control method can achieve high-efficiency precise control of the output charging voltage and current of the charger, but it is difficult to complete the detection and control of the electromagnetic interference characteristics of the charger. The solution of the present invention, based on the traditional control method, adds the first to sixth step voltage sampling circuits to respectively sample the output nodes V sw1 ~V sw6 The voltage status is sampled in real time.

[0063] Usually, the main EMI interference source of the power conversion system is the fast-changing high-power voltage and current node signals. In the two-level conversion on-board charger provided by the present invention, the EMI interference source is the output node of each half-bridge arm. Therefore, the main source of electromagnetic interference of the charger of the present invention is the output node V of the first to sixth half-bridge arms. sw1 ~V sw6 The present invention detects the moment when the voltage of the output nodes of the six half-bridge arms changes rapidly, and then comprehensively judges whether the EMI interference of the charger exceeds the set value, and adjusts the driving signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, S10 through the charger working state control circuit to control the gates of the power switch devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, M10, respectively, so as to realize the modulation control of the states of the front-stage PFC converter 2 and the rear-stage LLC converter 3, and reduce EMI interference.

[0064] Figure 3 for Figure 2An embodiment of a medium voltage sampling circuit. The circuit uses a standard resistor proportional amplifier circuit, and the amplification factor is proportional to R3 / (R1+R2). in 、V dc 、V out The maximum amplitude is greater than 200V, so for voltage V in 、V dc 、V out For sampling, it is necessary to use an amplification factor less than one for signal sampling, so that the sampled signal does not exceed the input range of the wide input voltage range ADC circuit.

[0065] Figure 4 for Figure 2 An embodiment of a current sampling circuit in the invention. The circuit is composed of a Hall current sensor and a resistor proportional amplifier circuit in cascade connection, and the amplification factor is proportional to R43 / (R41+R42). Since the current I Lr1 ,I out and I L There is a large difference in the maximum amplitude of the current I Lr1 ,I out and I L For sampling, it is necessary to use R43 with different resistance values ​​to achieve different amplification factors for signal sampling, so that the sampling signal does not exceed the input range of the wide input voltage range ADC circuit.

[0066] Figure 5 for Figure 2 An embodiment of a medium step voltage sampling circuit. The circuit is composed of a voltage differential conductance circuit and a resistor proportional amplifier circuit in cascade connection, and the amplification factor is proportional to R53 / (R51+R52). Since the output nodes V sw1 ~V sw6 There is a big difference in the maximum step slope amplitude, and different resistance values ​​of R53 are needed to achieve different amplification factors for signal sampling, so that the sampling signal does not exceed the input range of the wide input voltage range ADC circuit.

[0067] Figure 6 The schematic diagram of the working principle of the step voltage sampling circuit is shown in Figure 2. As mentioned above, the main EMI interference source of the power conversion system is the fast-changing high-power voltage and current node signals, and the steeper the voltage change slope of the high-current power device switch signal, the greater the EMI interference generated. The slope of the voltage signal can be detected by differential derivation. Figure 6 As shown, before time t0, V sw The signal is stable and unchanged, the differential step signal V st The output is 0; when V swThe signal has a step-up process at time t0-t1. Through the differential conduction circuit processing, the differential step signal V st will become a voltage of dV / dt; during the time interval t1-t2, V sw The signal remains stable again, and the differential step signal V st The output is 0; when V sw The signal has a step-down process at time t2-t3. Through the differential conduction circuit processing, the differential step signal V st will become a voltage of -dV / dt; after t3, V sw The signal remains stable again, and the differential step signal V st The output is 0.

[0068] It can be seen that after using the differential conduction circuit, the output nodes V sw1 ~V sw6 The rapid change of voltage signal will be converted into the corresponding step voltage signal V st1～6 , and V st1～6 The voltage amplitude is related to V sw1～6 The switching slope is proportional to the EMI source’s energy.

[0069] The scheme of the present invention realizes power density improvement by adopting the high-frequency switching speed of wide-bandgap power switching devices, which also brings serious electromagnetic interference challenges. In the vehicle charger described in the present invention, the high-voltage input EMI filter module 1, the front-stage PFC converter 2, and the rear-stage LLC converter 3 are high-voltage strong-electric modules, and the signal sampling and control circuit 4 is a typical weak-electric module. The functional circuit of the internal output control strong-electric module of the signal sampling and control circuit 4 is a high-voltage gate drive circuit. In order to ensure the stable operation of the system, the high-voltage gate drive circuit must have a very high ability to resist instantaneous changes in common-mode voltage (high CMTI common-mode transient immunity). For this reason, the wide-bandgap power device drive circuit and the MOSFET drive circuit described in the present invention are all implemented using a capacitive isolation gate drive circuit.

[0070] Figure 7The figure shows the block diagram of the capacitive isolation gate drive circuit. The circuit is functionally divided into a left control IC responsible for input control signal modulation and a right drive IC responsible for signal demodulation and output drive. The two chips are coupled by four high-voltage capacitors to achieve signal transmission between the chips. The left control IC and the right drive IC are packaged and integrated to obtain a capacitive isolation gate drive IC. The left control IC mainly includes an OOK TX circuit (OOK modulation and transmission circuit), an OSC generation circuit, and two high-voltage capacitors HV cap. The OOK modulated signal sent by the left control IC is transmitted into the right drive IC through two high-voltage capacitors HV cap coupling in differential mode; the functional modules integrated in the right drive IC include: two HV caps, a high-voltage output drive circuit, and an OOK RX circuit (OOK demodulation and receiving circuit).

[0071] Figure 7 In the isolation gate drive circuit shown, the external digital input signal Din; the OOK modulation transmission circuit modulates the clock signal of more than GHz output by the digital input signal Din and the OSC generation circuit to obtain differential transmission data DXP and DXN, and generates differential transmission data TXP and TXN at the right end of the left high-voltage capacitor through capacitive coupling; TXP and TXN are respectively connected to the left end of the right high-voltage capacitor, and differential reception data RXP and RXN are obtained at the right end of the right high-voltage capacitor through capacitive coupling; RXP and RXN enter the OOK demodulation receiving circuit, and the input pulse signal Drxin is obtained after processing; Drxin finally enters the high-voltage output drive circuit to generate an output drive signal GO with a large drive current. Since OOK signal modulation requires the use of an oscillation signal of more than GHz, the OOK TX circuit and its layout design will greatly affect its performance.

[0072] Figure 8The figure shows an embodiment of the OOK TX circuit of the present invention, in which a CMTI filter module is added on the basis of the traditional differential OOK modulation circuit. The 1.8V data input signal Din and the control signal Ctrl are passed through an AND gate to generate a modulation input signal Dinok, and then Dinok is logically processed with the delayed and inverted clock signal of OSC, and the complementary modulation signals are output through the drive of buffers Buff_p and Buff_n, and finally DXP and DXN are obtained through the CMTI filter. The CMTI filter module is composed of capacitors Cftp, Cftn and resistors Rftp and Rftn. The capacitor Cftp and the resistor Rftp constitute a high-pass filter input to the DXP end, and the capacitor Cftn and the resistor Rftn constitute a high-pass filter input to the DXN end. The low-frequency common-mode noise coupled to the DXP and DXN ends by the right-side driver IC through the high-voltage capacitor will be filtered out by the two differential high-pass filters, thereby reducing the influence of common-mode interference and improving the CMTI characteristics. Since the OSC signal, DXP ​​and DXN signal lines are all pulse signals with frequencies greater than GHz, the DXP and DXN port layout design requires strict differential matching design.

[0073] A layout design implementation example of the OOK TX circuit of the present invention is as follows Fig. 9 As shown, it includes OOK modulation logic gate, buffer Buff_p and Buff_n, Cftp capacitor array, Cftn capacitor array and Rftp resistor array, Rftn resistor array and other layout areas, as well as DXP, DXN signal line wiring area. The overall layout of the OOK TX circuit is symmetrical. The CMTI filter circuit composed of Cftp, Cftn capacitor array and Rftp, Rftn resistor array requires strict matching design. The top side is the Rftp, Rftn resistor array layout area, the lower center is the OOK modulation logic gate, the two sides are symmetrical for the buffer Buff_p and Buff_n layout area, and the two sides are symmetrical for the Cftp capacitor array layout area and the Cftn capacitor array layout area. The two capacitors can be realized using existing capacitor layout implementation measures. The output OOK signal modulation signal DXP and DXN routing adopts a completely symmetrical transmission from bottom to top; the output of buffers Buff_p and Buff_n and DXP / DXN are differential pulse signals with a frequency greater than GHz. The signal routing adopts a 45-degree line turn, and the signal line should avoid sharp corners at the turn. At the same time, wide metal wires are used to reduce parasitic inductance and resistance effects. In addition, all the outer sides of the layout area are all grounded shielding rings.

[0074] Fig.10 for Figure 2The structural block diagram of the charger working state control circuit. The circuit includes: 12 data registers, 12 data subtractors, a charger voltage and current state comprehensive judgment processing circuit, a power switch waveform generation circuit, and a memory for storing charger voltage and current signals and waveform reference data. The quantization code DV in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 ,DI Lr1 ,DI out and DI L The outputs of the 12 data registers enter 12 data subtractors and are compared with the 12 reference data D output by the memory. r1 ~D r12 Subtract and get 12 state margin data D re1 ~D re12 ; The comprehensive judgment and processing circuit of the charger voltage and current state will be based on 12 state margin data D re1 ~D re12 The mode control signal Dcon is generated by comprehensive calculation with the margin reference data Dref output by the memory; finally, the power switch waveform generating circuit generates gate control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10 according to the mode control signal Dcon and the reference waveform data Dwave output by the memory.

[0075] The charger working state control circuit of the present invention inputs the quantization code DV in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 ,DI Lr1 ,DI out and DI L Subtract the reference data to get 12 state margin data D re1 ~D re12 Then the charger voltage and current state comprehensive judgment processing circuit will be based on the 12 state margin data D re1 ~D re12The residual reference data Dref is used to perform comprehensive calculations to generate the mode control signal Dcon; finally, the power switch waveform generation circuit generates 12 gate control signals according to the mode control signal Dcon and the reference waveform data Dwave. The above process mainly realizes the precise control of the performance of the on-board charger through 12 input quantization codes and the final 12 output gate control signals. The key links are:

[0076] (1) 12 reference data D r1 ~D r12 , the residual reference data Dref, and the reference waveform data Dwave need to be centered on the values ​​of the typical working state of the on-board charger, while covering the extreme conditions that may occur during the working process of the charger;

[0077] (2) The judgment and processing algorithm used by the comprehensive judgment and processing circuit of the charger voltage and current state needs to be based on 12 state margin data D re1 ~D re12 The working state of the charger is accurately calculated based on the residual reference data Dref, and a mode control signal Dcon is generated.

[0078] For 12 reference data D r1 ~D r12 The generation of the residual reference data Dref and the reference waveform data Dwave requires the modeling of the operating parameters of the charger circuit and the testing of the actual parameters. Only by sampling a large amount of experimental data and then performing statistical analysis can the distribution range of the above reference data and the central value of the reference data be determined. In addition, the data accuracy (number of bits) of the reference data also has an important influence on the control accuracy of the above charger working state control circuit. However, the number of bits of the reference data is directly related to the hardware complexity of the charger working state control circuit. The higher the accuracy, the greater the hardware overhead, and an ADC circuit with the same bit accuracy is required. The following is the D corresponding to the quantization code DVout. r5 , D re5 The normal voltage range of Vout is 220V-360V. The high-precision ADC circuit adopts 16-bit precision. Then the reference value of Vout=290V can be set as the center value. At this time, DVout can be calibrated to 10000000000000000. re5 The setting needs to be determined by statistical analysis based on the deviation value of the actual test, and different temperature environments, humidity conditions and physical vibration environments need to be tested. out The maximum offset from 1000000000000000 is an absolute value of X, then D re5 Set to half of X, i.e. D re5 =X / 2, X is the absolute value less than DVout The reference waveform data Dwave can be realized by using a traditional digital square wave or sawtooth wave generation method, which is realized by a data generator and a DAC.

[0079] For the discrimination processing algorithm adopted by the comprehensive discrimination processing circuit of the charger voltage and current state, the algorithm model such as PID algorithm and artificial intelligence neural network algorithm can be used for implementation. When setting the parameters of the algorithm model, it is necessary to consider the performance parameters of the actual charger, including comprehensive indicators such as output power, switching frequency, EMI index, and reliability index. Therefore, the mode control signal Dcon output by the comprehensive discrimination processing circuit of the charger voltage and current state needs to include a control word reflecting characteristic parameters such as output power, switching frequency, EMI, and reliability. For example, if the mode control signal Dcon is set to a 16-bit control word d15-d0, then d15-d12 can be set as the output power control word for output power control; d11-d8 can be set as the switching power control word for switching frequency control; d7-d4 can be set as the EMI control word for EMI control; d3-d0 can be set as the output power control word for reliability control.

[0080] The present invention controls the EMI interference of the charger by first detecting DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 to determine the EMI interference intensity; if the EMI interference intensity exceeds the set threshold, the charger voltage and current state comprehensive judgment processing circuit will set and modify the EMI control words d7-d4 in the mode control signal Dcon, and adjust the output nodes V sw1 ~V sw6 The delay between the switching step edges reduces the time overlap of EMI interference sources, thereby reducing the EMI peak.

[0081] Fig.11This is a flow chart of the charger working state control of the present invention. After the power supply is powered on, the charger starts to reset; then, the charger working state control circuit outputs the initial mode control signal Dcon and 12 initial gate control signals, and the charger starts power conversion and has power output; after that, the signal sampling and control circuit starts to detect the current and voltage signals on the main power conversion circuit board, and digitally quantizes the detected current and voltage signals, and calculates the difference between the quantization code and the reference signal to obtain the state error (state margin data); the charger working state control circuit calculates the adjustment mode control signal Dcon according to the state error, and then adjusts the gate control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10; the charger starts to enter the normal working state.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. High power density electric vehicle on-board charger circuit, including input EMI filter module (1), front-stage PFC converter (2), rear-stage LLC converter (3), AC input voltage V in The rectified voltage signal is outputted through the input EMI filter module (1) and connected to the first input terminal and the second input terminal of the front-stage PFC converter (2). The output of the front-stage PFC converter (2) is the DC bus voltage V dc The subsequent LLC converter (3) converts the DC bus voltage V dc Further transformation to obtain the output DC charging voltage V out , V out The output charging current is I out Its characteristics are: It also includes a signal sampling and control circuit (4) and an auxiliary power supply circuit (5); The signal sampling and control circuit (4) processes the AC input voltage V in , the voltage and current state of the front-stage PFC converter (2), and the voltage and current state of the rear-stage LLC converter (3) are sampled in real time, and the states of the power switch devices in the front-stage PFC converter (2) and the rear-stage LLC converter (3) are modulated and controlled respectively through power switch control signals; the auxiliary power supply circuit (5) is used to generate different types of power supply voltages required by various circuits in the signal sampling and control circuit (4); The front-stage PFC converter (2) comprises: a first half bridge arm composed of a power switch device M1 and a power switch device M2, a second half bridge arm composed of a power switch device MQ1 and a power switch device MQ2, an inductor L, a diode D1, a diode D2, and a capacitor Cbus, wherein the capacitor Cbus is connected between two output ends of a bridge circuit composed of power switch devices M1 to M4; the output node of the first half bridge arm is V sw1 , connected to the right end of the inductor L, and also connected to the anode of the diode D1 and the cathode of the diode D2; the left end of the inductor L is connected to the first input end of the front-stage PFC converter (2), and the right end of the inductor L is output to the node V sw1 The current is I L ; The output node of the second half bridge arm is V sw2 , connected to the second input terminal of the preceding PFC converter (2); the gate control signals of the power switch device M1 and the power switch device M2 are S1 and S2 respectively, and the gate control signals of the power switch device MQ1 and the power switch device MQ2 are Q1 and Q2 respectively; The post-stage LLC converter (3) comprises: power switch devices M3-M6 forming a bridge circuit at the input end, power switch devices M7-M10 forming a bridge circuit at the output end, a resonant inductor Lr1, a resonant capacitor Cr1, and an inductor Lm located on the primary side of a transformer T, and a resonant inductor Lr2 and a resonant capacitor Cr2 located on the secondary side of the transformer T; the two input ends of the bridge circuit formed by the power switch devices M3-M6 are connected to the two output ends of the pre-stage PFC converter (2); the output capacitor Cout is connected between the two output ends of the bridge circuit formed by the power switch devices M7-M10; The power switch device M3 and the power switch device M4 form a third half bridge arm, and the output node of the third half bridge arm is V sw3 ; The power switch device M5 and the power switch device M6 form a fourth half bridge arm, and the output node of the fourth half bridge arm is V sw4 ; The power switch device M7 and the power switch device M8 form the fifth half bridge arm, and the output node of the fifth half bridge arm is V sw5 ; The power switch device M9 and the power switch device M10 form the sixth half bridge arm, and the output node of the sixth half bridge arm is V sw6 ; The gate control signals of the power switch device M3 and the power switch device M4 are S3 and S4 respectively, the gate control signals of the power switch device M5 and the power switch device M6 are S5 and S6 respectively, the gate control signals of the power switch device M7 and the power switch device M8 are S7 and S8 respectively, and the gate control signals of the power switch device M9 and the power switch device M10 are S9 and S10 respectively; the node V sw3 Connected to the left end of the resonant inductor Lr1, node V sw3 The current output to the resonant inductor Lr1 is I Lr1 , the right end of the resonant inductor Lr1 is connected to the primary side of the transformer T; The signal sampling and control circuit (4) controls the voltage V in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 The state and current I L ,I Lr1 and I out The state of the front-stage PFC converter (2) and the rear-stage LLC converter (3) are modulated and controlled by the control signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9 and S10 to control the gates of the power switch devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9 and M10 respectively.

2. The high power density electric vehicle onboard charger circuit according to claim 1 is characterized in that: The signal sampling and control circuit (4) comprises: 6 step voltage sampling circuits, 3 current sampling circuits, 3 voltage sampling circuits, a wide input voltage range ADC circuit, a charger working state control circuit, 10 wide bandgap power device drive circuits, and 2 MOSFET drive circuits; The six step voltage sampling circuits respectively sense the output node V sw1 , the output node V of the second half bridge arm sw2 , the output node V of the third half bridge arm sw3 , the output node V of the fourth half bridge arm sw4 , the output node V of the fifth half bridge arm sw5 , the output node V of the sixth half bridge arm sw6 Real-time sampling of voltage status; The three current sampling circuits respectively sense the current I Lr1 、Current I out 、Current I L Real-time sampling of the status; The three voltage sampling circuits respectively sense the AC input voltage V in , output DC charging voltage V out , DC bus voltage V dc Real-time sampling of the status; The sampling voltages of all the sampling circuits are connected to the wide input voltage range ADC circuit, which performs analog-to-digital conversion on all the sampling voltages. in 、V dc 、V out 、V sw1 、V sw2 、V sw3 、V sw4 、V sw5 、V sw6 Convert to DV quantization code in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 , respectively, the current I Lr1 ,I out and I L Convert to quantization code DI Lr1 ,DI out and DI L ; All quantization codes enter the charger working state control circuit, and are processed to output control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10; control signals DS1 and DS2 are respectively passed through the first wide bandgap power device drive circuit and the second wide bandgap power device drive circuit to generate control signals S1 and S2; control signals DQ1 and DQ2 are respectively passed through two MOSFET drive circuits to generate control signals Q1 and Q2; control signals DS3 to DS10 are respectively passed through the third wide bandgap power device drive circuit to the tenth wide bandgap power device drive circuit to generate control signals S3, S4, S5, S6, S7, S8, S9, and S10.

3. The high power density electric vehicle onboard charger circuit according to claim 2 is characterized in that: The step voltage sampling circuit is composed of a voltage differential conductance circuit and a resistor proportional amplifier circuit in cascade, the resistor proportional amplifier circuit includes an operational amplifier and resistors R51, R52, R53 and R54, the input end of the voltage differential conductance circuit is connected to the sampled voltage, the output end of the voltage differential conductance circuit is connected to the negative input end and the positive input end of the operational amplifier through resistors R51 and R52 respectively, the output end of the operational amplifier is connected to the negative input end of the operational amplifier through resistor R53, and the positive input end of the operational amplifier is grounded through resistor R54; the amplification factor is proportional to R53 / (R51+R52); After using the voltage differential conduction circuit, the output node V sw1 ~V sw6 The rapid change of voltage signal will be converted into a corresponding step voltage signal, the voltage amplitude of which is similar to V sw1 ~V sw6 The switching slope is proportional to the EMI source’s energy.

4. The high power density electric vehicle onboard charger circuit according to claim 2 is characterized in that: The 10 wide bandgap power device drive circuits and the 2 MOSFET drive circuits are all implemented using capacitor isolation gate drive circuits; The capacitive isolation gate driving circuit is functionally divided into a control chip responsible for input control signal modulation and a driving chip responsible for signal demodulation and output driving. The two chips are coupled by four high-voltage capacitors to realize signal transmission between the chips. The control chip and the driving chip are packaged and integrated to obtain a capacitive isolation gate driving chip; the control chip includes an OOK modulation and transmission circuit, which is respectively connected to an OSC generation circuit and two high-voltage capacitors. The OOK modulation signal sent by the control chip is transmitted into the driving chip through two high-voltage capacitor coupling in a differential mode; the driving chip includes: another two high-voltage capacitors, an OOK demodulation receiving circuit, and a high-voltage output driving circuit. The OOK modulation signal is transmitted into the OOK demodulation receiving circuit through another two high-voltage capacitor coupling. The output of the OOK demodulation receiving circuit is then connected to the high-voltage output driving circuit to finally output the driving signal.

5. The high power density electric vehicle onboard charger circuit according to claim 4 is characterized in that: The OOK modulation transmission circuit adds a CMTI filter module at the output end of the differential OOK modulation circuit. The CMTI filter module includes a capacitor Cftp, a capacitor Cftn, a resistor Rftp, and a resistor Rftn. The output end of the differential OOK modulation circuit is respectively connected to the left end of the capacitor Cftp and the left end of the capacitor Cftn, the right end of the capacitor Cftp is connected to the upper end of the resistor Rftp and outputs a differential signal DXP, the right end of the capacitor Cftn is connected to the lower end of the resistor Rftp and outputs a differential signal DXN, the lower end of the resistor Rftp is connected to the upper end of the resistor Rftn and is grounded; the capacitor Cftp and the resistor Rftp constitute a high-pass filter input to the DXP end, and the capacitor Cftn and the resistor Rftn constitute a high-pass filter input to the DXN end; the low-frequency common-mode noise coupled to the DXP and DXN ends by the driver chip through the high-voltage capacitor will be filtered out by the two differential high-pass filters, thereby reducing the influence of common-mode interference and improving the common-mode transient immunity.

6. The high power density electric vehicle onboard charger circuit according to claim 5 is characterized in that: The layout of the OOK modulation transmission circuit includes: an OOK modulation logic gate, a buffer Buff_p, a buffer Buff_n, a Cftp capacitor array, a Cftn capacitor array, an Rftp resistor array, an Rftn resistor array, and DXP and DXN signal line wiring areas; The overall layout of the OOK modulation transmission circuit is symmetrical on the left and right. The uppermost side is the Rftp resistor array and Rftn resistor array layout area arranged horizontally, the lower center is the OOK modulation logic gate layout area, the left and right sides of the OOK modulation logic gate layout area are the buffer Buff_p layout area and the buffer Buff_n layout area respectively, the left side of the buffer Buff_p layout area is the Cftp capacitor array layout area, and the right side of the buffer Buff_n layout area is the Cftn capacitor array layout area; DXP and DXN routing are transmitted from bottom to top in a completely symmetrical manner; the output signals of buffers Buff_p and Buff_n and DXP and DXN signals are differential pulse signals with frequencies greater than GHz. Signal routing uses 45-degree line turns, and sharp corners should be avoided at the turns of signal lines. At the same time, wide metal lines are used to reduce parasitic inductance and resistance effects; In addition, ground shielding rings are used on the outside of all layout areas.

7. The high power density electric vehicle onboard charger circuit according to claim 2 is characterized in that: The charger working state control circuit includes: 12 data registers, 12 data subtractors, a charger voltage and current state comprehensive judgment processing circuit, a power switch waveform generation circuit and a memory for storing charger voltage and current signals and waveform reference data; the quantization code DV in 、DV dc 、DV out 、DV sw1 、DV sw2 、DV sw3 、DV sw4 、DV sw5 、DV sw6 ,DI Lr1 ,DI out and DI L The 12 data registers are connected to 12 data subtractors, and the 12 reference data D output by the memory are connected to 12 data subtractors. r1 ~D r12 Subtract and get 12 state margin data D re1 ~D re12 , connected to the charger voltage and current state comprehensive judgment processing circuit; the charger voltage and current state comprehensive judgment processing circuit will be based on 12 state margin data D re1 ~D re12 The mode control signal Dcon is generated by performing a comprehensive operation with the margin reference data Dref output by the memory, and the mode control signal Dcon is connected to the power switch waveform generating circuit; finally, the power switch waveform generating circuit generates control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, and DS10 according to the mode control signal Dcon and the reference waveform data Dwave output by the memory.

8. The high power density electric vehicle onboard charger circuit according to claim 7 is characterized in that: The mode control signal Dcon output by the charger voltage and current state comprehensive judgment processing circuit needs to include a control word reflecting characteristic parameters including output power, switching frequency, EMI, and reliability.

9. The high power density electric vehicle onboard charger circuit according to claim 8 is characterized in that: At the moment when the voltages of the output nodes Vsw1 of the first half bridge arm, Vsw2 of the second half bridge arm, Vsw3 of the third half bridge arm, Vsw4 of the fourth half bridge arm, Vsw5 of the fifth half bridge arm, and Vsw6 of the sixth half bridge arm change rapidly, it is comprehensively judged whether the EMI interference of the charger exceeds the set value, and the control signals S1, S2, Q1, Q2, S3, S4, S5, S6, S7, S8, S9, and S10 are adjusted by the charger working state control circuit to control the gates of the power switch devices M1, M2, MQ1, MQ2, M3, M4, M5, M6, M7, M8, M9, and M10, thereby realizing modulation control of the states of the front-stage PFC converter (2) and the rear-stage LLC converter (3); If the EMI interference intensity exceeds the set threshold, the charger voltage and current state comprehensive judgment processing circuit will modify the EMI control word in the mode control signal Dcon, adjust the delay between the switch step edges of nodes Vsw1~Vsw6, reduce the time overlap of EMI interference sources, and thus reduce the EMI peak.

10. The high power density electric vehicle onboard charger circuit according to claim 7, characterized in that: The overall working process is as follows: after the power supply is turned on, the charger is started and reset; then, the charger working state control circuit outputs the initial mode control signal Dcon and the initial control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10, and the charger starts power conversion and has power output; then, the signal sampling and control circuit (4) starts to detect the current and voltage signals in the front-stage PFC converter (2) and the rear-stage LLC converter (3), and digitally quantizes the detected current and voltage signals, and the state margin data obtained by subtracting the quantization code from the reference signal is the state error; the charger working state control circuit calculates the adjustment mode control signal Dcon according to the state error, and then adjusts the control signals DS1, DS2, DQ1, DQ2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10; and the charger starts to enter the normal working state.

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