Method for automatically optimizing fractional spur and integer boundary spur of a frequency source

Abstract

The application discloses a method for automatically optimizing decimal spur and integer boundary spur of a frequency source, belongs to the technical field of radar communication, and is used for solving the problem of multiple spurs of the existing frequency source output, which influences signal quality. The method sets a phase-locked loop phase detection frequency variation range, phase detection frequency variation steps, associates integer boundary spur frequencies and decimal spur frequencies with out-of-band suppression points of a phase-locked loop filter through software configuration, automatically optimizes the phase detection frequency to integer boundary spur suppression and decimal spur suppression to meet indexes, and effectively realizes automatic optimization of decimal spur and integer boundary spur.

Description

Technical Field

[0001] This invention belongs to the field of radar communication technology, specifically, it relates to a method for automatically optimizing fractional spurious emissions and integer boundary spurious emissions of a frequency source. Background Technology

[0002] Frequency sources are the fundamental signal source of electronic systems. In modern electronics, they have become core components, widely used in radar, communication, measurement and control, countermeasures, and navigation. With the development of modern electronics, the performance and functionality of electronic devices are constantly improving, placing higher demands on the performance of frequency sources. Key performance indicators for frequency sources include miniaturization, small step size, high stability, ultra-wideband, low phase noise, low spurious emissions, low power consumption, frequency agility, and fast startup. However, these indicators are interdependent, making it difficult to achieve a perfect balance. Furthermore, the emphasis on various performance indicators differs across application areas. Therefore, frequency source design often requires trade-offs and compromises based on the specific application scenario.

[0003] There are various existing methods for implementing frequency sources, including phase-locked loop (PLL) frequency sources, direct digital frequency synthesis (DDS) frequency sources, DDS-driven PLL frequency sources, and PLL-driven PLL frequency sources. PLLs cannot achieve fine-step frequency hopping; while DDS can achieve fine-step frequency hopping, its operating principle limits its output to higher frequency, wider bandwidth signals. Furthermore, the nonlinear characteristics of the internal DAC (digital-to-analog converter) in DDS result in significant output spurious noise, affecting signal quality. Directly driving a PLL with a DDS results in substantial degradation of spurious and phase noise at the DDS output, impacting the final output signal quality. PLL-driven PLL frequency sources have a simple circuit structure, but achieving fine-step frequency hopping requires optimization of integer boundary spurious and fractional spurious noise. Summary of the Invention

[0004] The purpose of this invention is to provide a method for automatically optimizing fractional spurious and integer boundary spurious frequencies of a frequency source. This method associates the integer boundary spurious frequency and the fractional spurious frequency with the out-of-band suppression point of the phase-locked loop filter, thereby achieving automatic optimization of fractional spurious and integer boundary spurious frequencies.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for automatically optimizing fractional spurious emissions and integer boundary spurious emissions in a frequency source includes the following steps:

[0007] S1, set the loop filter bandwidth of the phase-locked loop to f BW The output frequency is set to f OUT The phase detection frequency is set to f.REF The lap-time division ratio of the phase-locked loop is configured as Nx = f OUT / f REF ;

[0008] S2, set the phase detection frequency variation range to f REF1 ~f REF2 The phase detection frequency change step is set to X;

[0009] S3, calculate the integer boundary spurious and fractional spurious of the phase-locked loop;

[0010] S4. Determine whether the integer boundary spurious and fractional spurious of the phase-locked loop (PLL) both fall within the suppression band of the PLL's loop filter. If they do, proceed to step S5. Otherwise, adjust the phase detection frequency according to the phase detection frequency change step, and repeat steps S3 and S4 until the integer boundary spurious and fractional spurious of the PLL both fall within the suppression band of the PLL's loop filter, and then proceed to step S5.

[0011] S5 is the final loop divider ratio of the output phase-locked loop.

[0012] Furthermore, in this invention, the formula for calculating the integer boundary spurious F1 of the phase-locked loop is:

[0013] F1 = (Nx - INT(Nx)) * f REF ;

[0014] The formula for calculating the fractional spurious F2 of a phase-locked loop is:

[0015] F2 = (INT(Nx) + 1 - Nx) * f REF ;

[0016] The condition that both the integer boundary spurious F1 and the fractional spurious F2 of the phase-locked loop (PLL) fall within the suppression band of the PLL's loop filter is F1 ≥ n*f. BW And F2≥n*f BW Where n is the coefficient of the loop bandwidth multiplication; INT represents the floor function.

[0017] Furthermore, in step S4, the specific steps for adjusting the phase detection frequency according to the phase detection frequency change steps are as follows:

[0018] S41, determine f REF1 ≤f REF +X≤f REF2 Is it true? If it is true, proceed to step S42; otherwise, proceed to step S43.

[0019] S42, add a phase detection frequency change step X to the previously configured phase detection frequency, and repeat steps S3 to S5 until F1 ≥ n*f BWAnd F2≥n*f BW This is established, yielding the final loop division ratio;

[0020] S43, subtract the difference f between the phase detection frequency range and the previously configured phase detection frequency. REF2 -f REF1 Repeat steps S3 to S5 until F1 ≥ n*f BW And F2≥n*f BW Once established, the final loop frequency division ratio is obtained.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The frequency source in this invention sets the phase-locked loop (PLL) phase detection frequency variation range and the phase detection frequency variation step. Through software configuration, it associates the integer boundary spurious frequency and the fractional spurious frequency with the out-of-band suppression point of the PLL loop filter, automatically optimizing the phase detection frequency until the integer boundary spurious suppression and fractional spurious suppression meet the indicators. This effectively realizes the algorithm for automatically optimizing fractional spurious and integer boundary spurious frequencies. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the frequency source in an embodiment of the present invention.

[0024] Figure 2 This is a flowchart of the method of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0026] This invention discloses a method for automatically optimizing fractional spurious emissions and integer boundary spurious emissions in a frequency source, such as... Figure 1 As shown, the frequency source in this embodiment includes a variable reference clock, a phase-locked loop, and a control unit. Figure 2 As shown, this invention designs the phase-locked loop bandwidth to be f using hardware circuitry. BW The control unit sets the phase-locked loop output frequency to f. OUT The phase detection frequency variation range is set to f REF1 ~f REF2 The phase detection frequency change step is set to X, and the phase-locked loop phase detection frequency is set to f. REF The loop divider ratio is configured as N=f OUT / f REF If Nx = INT(Nx) * f, then the formula for calculating the integer boundary spurious F1 of the phase-locked loop is: F1 = (Nx - INT(Nx)) * f REF The formula for calculating the fractional spurious emissions F2 in a phase-locked loop is: F2 = (INT(Nx) + 1 - Nx) * fREF If F1 ≥ 100*f BW And F2≥100*f BW If both integer boundary spurious F1 and fractional spurious F2 of the phase-locked loop (PLL) fall within the loop filter suppression band, then the suppression of both integer boundary spurious F1 and fractional spurious F2 is good. Here, 100 is the coefficient of the loop bandwidth multiplier, which can be adjusted appropriately according to the actual situation. If F1 < 100 * f BW Or F2*f REF <100*f BW If the integer boundary spurious and fractional spurious signals of the phase-locked loop (PLL) do not fall within the suppression band of the PLL's loop filter, the suppression of integer boundary spurious signals and fractional spurious signals will be poor. Changing the phase detection frequency (f) will further improve the suppression of integer boundary spurious signals. REF +X at the phase detection frequency f REF1 ~f REF2 Within the range, then f REF鉴相 =f REF +X, if f REF鉴相 =f REF +X was not at the phase detection frequency f REF1 ~f REF2 Within the range, then f REF鉴相 =f REF -(f REF2 -f REF1 ).

[0027] The following are specific numerical examples:

[0028] The loop filter bandwidth of the phase-locked loop is designed to be 0.1MHz, the phase detection frequency range is set to 50MHz-80MHz, and the phase detection frequency change step is 10MHz.

[0029] The output frequency is 2005.8MHz, and the phase detection frequency is designed to be 50MHz. Nx = 2005.8 / 50 = 40.116; (40.116 - INT(40.116)) * 100 = (40.116 - 40) * 100 = 11.6MHz > 0.1MHz * 100; (INT(40.116) + 1 - 40.116) * 100 = (40 + 1 - 40.116) * 100 = 88.4MHz > 0.1MHz * 100. At this time, the phase detection frequency is 50MHz, and Nx = 2005.8 / 50 = 40.116.

[0030] The output frequency is 2000.1MHz, and the phase detection frequency is designed to be 50MHz. Nx = 2000.1 / 50 = 40.002; (40.002 - INT(40.002)) * 100 = (40.002 - 40) * 100 = 0.2MHz < 0.1MHz * 100; (INT(40.002) + 1 - 40.002) * 100 = (40 + 1 - 40.002) * 100 = 99.8MHz > 0.1MHz * 100 At this point, the phase detection frequency is 50MHz + 10MHz = 60MHz; Nx = 2000.1 / 60 = 33.335, (33.335 - INT(33.335)) * 100 = (33.335 - 33) * 100 = 33.5MHz > 0.1MHz * 100; (INT(33.335) + 1 - 33.335) * 100 = (33 + 1 - 33.335) * 100 = 66.5MHz > 0.1MHz * 100. Therefore, the phase detection frequency is 60MHz; Nx = 2000.1 / 60 = 33.335.

[0031] The output frequency is 2080.4MHz, and the phase detection frequency is designed to be 80MHz. Nx = 2080.4 / 80 = 26.005; (26.005 - INT(26.005)) * 100 = (26.005 - 26) * 100 = 0.5MHz < 0.1MHz * 100; (INT(26.005) + 1 - 26.005) * 100 = (26 + 1 - 26.005) * 100 = 99.5MHz > 0.1MHz * 100. At this point, the phase detection frequency is 80MHz - (80 - 50) = 50MHz; Nx = 2080.4 / 50 = 41.608, (41.608 - INT(41.608)) * 100 = (41.608 - 41) * 100 = 60.8MHz > 0.1MHz * 100; (INT(41.608) + 1 - 41.608) * 100 = (41 + 1 - 41.608) * 100 = 39.2MHz > 0.1MHz * 100. Therefore, the phase detection frequency is 50MHz; Nx = 2080.4 / 50 = 41.608.

[0032] The frequency source in this invention sets the phase-locked loop (PLL) phase detection frequency variation range and the phase detection frequency variation step. Through software configuration, it associates the integer boundary spurious frequency and the fractional spurious frequency with the out-of-band suppression point of the PLL loop filter, automatically optimizing the phase detection frequency until the integer boundary spurious suppression and fractional spurious suppression meet the indicators. This effectively realizes the algorithm for automatically optimizing fractional spurious and integer boundary spurious frequencies.

[0033] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A method for automatically optimizing fractional spurious emissions and integer boundary spurious emissions in a frequency source, characterized in that, Includes the following steps: S1, set the loop filter bandwidth of the phase-locked loop to f BW The output frequency is set to f OUT The phase detection frequency is set to f. REF The lap-time division ratio of the phase-locked loop is configured as Nx = f OUT / f REF ; S2, set the phase detection frequency variation range to f REF1 ~f REF2 The phase detection frequency change step is set to X; S3, calculate the integer boundary spurious and fractional spurious of the phase-locked loop; where the formula for calculating the integer boundary spurious of the phase-locked loop is: F1=(N.x- INT(N.x))*f REF ; The formula for calculating decimal spurious signals in a phase-locked loop is: F2=(INT(N.x)+1-N.x)*f REF ; The condition that both integer boundary spurious and fractional spurious emissions of a phase-locked loop (PLL) fall within the suppression band of the PLL's loop filter is F1 ≥ n*f. BW And F2≥n*f BW Where n is the coefficient of the loop bandwidth multiplication; INT represents the floor function. S4. Determine whether the integer boundary spurious and fractional spurious of the phase-locked loop (PLL) both fall within the suppression band of the PLL's loop filter. If they do, proceed to step S5. Otherwise, adjust the phase detection frequency according to the phase detection frequency change step, and repeat steps S3 and S4 until the integer boundary spurious and fractional spurious of the PLL both fall within the suppression band of the PLL's loop filter, and then proceed to step S5. S5 is the final loop divider ratio of the output phase-locked loop.

2. The method for automatically optimizing fractional spurious emissions and integer boundary spurious emissions of a frequency source according to claim 1, characterized in that, In step S4, the specific steps for adjusting the phase detection frequency according to the phase detection frequency change steps are as follows: S41, determine f REF1 ≤f REF +X≤f REF2 Is it true? If it is true, proceed to step S42. Otherwise proceed to step S43; S42, add a phase detection frequency change step X to the previously configured phase detection frequency, and repeat steps S3 to S5 until F1 ≥ n*f BW And F2≥n*f BW This is established, yielding the final loop division ratio; S43, subtract the difference f between the phase detection frequency range and the previously configured phase detection frequency. REF2 -f REF1 Repeat steps S3 to S5 until F1 ≥ n*f BW And F2≥n*f BW Once established, the final loop frequency division ratio is obtained.

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