Integrated circuit chip, manufacturing method and application
By setting a temporary protective layer in the device area of the integrated circuit chip to separate the dielectric layer, the problems of increasing parasitic capacitance and increasing noise coefficient caused by dielectric layer deposition are solved, and the effect of reducing parasitic capacitance and improving device noise characteristics is achieved.
Patent Information
- Application Number
- CN202311109502.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-31
- Publication Date
- 2025-03-04
AI Technical Summary
When the prior art deposits a thin film of dielectric layer in an integrated circuit chip multiple times, a thicker dielectric layer is formed near the gate, increasing parasitic capacitance, reducing the dielectric frequency of the current gain, and increasing the noise factor of the amplifier. The etching thinning method cannot guarantee the etching depth, affecting the device reliability.
By providing a temporary protective layer in the device area of the integrated circuit chip, separating the front and rear dielectric layers, and removing the second dielectric layer on the temporary protective layer, the thickness of the dielectric layer in the gate and nearby areas is avoided, thereby reducing parasitic capacitance and improving the noise characteristics of the device.
It effectively reduces the thickness of the dielectric layer in the gate and nearby areas of the integrated circuit chip device area, reduces the parasitic capacitance, and improves the noise characteristics and reliability of the device.
Smart Images
Figure CN119562588A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to an integrated circuit chip and a manufacturing method and application thereof. Background Art
[0002] High electron mobility transistors (HEMT) and pseudomorphic high electron mobility transistors (pHEMT) have important applications in RF circuits and RF integrated circuits. For example, as the main component of 5G RF chips, the gallium arsenide pseudomorphic high electron mobility transistor (pHEMT) low noise amplifier (LNA) has low noise characteristics. The gate control capability plays an important role in this, so the dielectric layer film deposited on the surface of the pHEMT is an important part of ensuring the reliability of the device, which plays a role in reducing the damage of environmental factors such as water vapor and oxygen to the performance of pHEMT and other components on the integrated circuit. Commonly used materials such as silicon nitride have a high dielectric constant.
[0003] Usually, dielectric films are deposited multiple times in the subsequent processes of multiple metal connections and capacitor metals of integrated circuit chips. Since the deposition process of dielectric films is full-surface deposition, a thicker dielectric layer will eventually be formed near the gate. A parasitic capacitor of a metal-dielectric-metal structure will be formed between the gate and the source and drain metals. With the deposition of a dielectric layer with a higher dielectric constant, the parasitic capacitance increases, resulting in a decrease in the dielectric frequency (Ft) of the current gain, and ultimately an increase in the noise coefficient of the amplifier. In addition, for multi-layer dielectric layers, the etching thinning method cannot guarantee the etching depth, which may threaten the reliability of the device. Summary of the invention
[0004] The present invention aims at the deficiencies in the prior art and provides an integrated circuit chip and a manufacturing method and application thereof.
[0005] In order to achieve the above purpose, the technical solution of the present invention is:
[0006] An integrated circuit chip includes an epitaxial structure, the epitaxial structure has a first device area, the first device area is provided with a source metal, a drain metal and a gate metal, and the gate metal is located between the source metal and the drain metal; a first metal connection layer, a second metal connection layer and a dielectric layer are arranged on the epitaxial structure, the dielectric layer includes a first dielectric layer and a second dielectric layer in sequence, the first dielectric layer covers the surface of the epitaxial structure, the source metal, the drain metal and the gate metal, and the first metal connection layer is formed on the first dielectric layer; the second dielectric layer covers the first metal connection layer and the surface of the first dielectric layer, and forms an opening in the first device area; the opening exposes the gate metal, the area between the gate metal and the source metal and the drain metal, and the first dielectric layer on at least part of the source metal and the drain metal; the second metal connection layer is formed on the second dielectric layer.
[0007] An integrated circuit chip refers to a chip that integrates multiple component structures and their connecting circuits.
[0008] Optionally, the distance between the edge of the opening and the edge of the source metal and the drain metal close to the gate metal is greater than 0.1 μm.
[0009] Optionally, the thickness of the first dielectric layer is 50-100 nm.
[0010] Optionally, the thickness of the second dielectric layer is 100-200 nm.
[0011] Optionally, at least one of the first metal connection layer and the second metal connection layer extends above the source metal and the drain metal and penetrates the dielectric layer to be connected to the source metal and the drain metal.
[0012] Optionally, the first metal connection layer extends to above the source metal and the drain metal and penetrates the first dielectric layer to be connected to the source metal and the drain metal, and the second metal connection layer extends to above the source metal and the drain metal and penetrates the second dielectric layer to be connected to the first metal connection layer.
[0013] Optionally, the edge of the opening is located on the outer side of the source metal and the drain metal away from the gate metal, the first metal connection layer extends to the top of the source metal and the drain metal and penetrates the first dielectric layer to be connected to the source metal and the drain metal, and the second metal connection layer extends and is stacked on the surface of the first metal connection layer above the source metal and the drain metal.
[0014] Optionally, a third dielectric layer is further included, and the third dielectric layer is located on the surface layer of the integrated circuit chip, and the thickness of the third dielectric layer is 50-600 nm.
[0015] Optionally, the material of the dielectric layer is at least one of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide.
[0016] Optionally, the first device region forms a pHEMT device or a HEMT device.
[0017] Optionally, it also includes a capacitor structure, which is located on the first dielectric layer outside the first device area and includes a lower plate, an upper plate and a capacitor dielectric layer, and the capacitor dielectric layer is sandwiched between the upper plate and the lower plate.
[0018] Optionally, the lower electrode plate and the upper electrode plate are respectively arranged on the same layer as the first metal connection layer and the second metal connection layer, and the capacitor dielectric layer is formed by the second dielectric layer.
[0019] A method for manufacturing an integrated circuit chip comprises the following steps:
[0020] 1) providing an epitaxial structure, the epitaxial structure having a first device region, wherein a source metal, a drain metal and a gate metal are provided on the first device region, and the gate metal is located between the source metal and the drain metal;
[0021] 2) forming a first dielectric layer, wherein the first dielectric layer covers the surfaces of the epitaxial structure, the source metal, the drain metal and the gate metal;
[0022] 3) depositing metal to form a first metal connection layer, wherein the first metal connection layer is formed on the first dielectric layer;
[0023] 4) forming a second dielectric layer, the second dielectric layer covers the first metal connection layer and the surface of the first dielectric layer, and forming an opening in the first device region; the opening exposes the gate metal, the region between the gate metal and the source metal and the drain metal, and the first dielectric layer on at least part of the source metal and the drain metal;
[0024] 5) Depositing metal to form a second metal connection layer, wherein the second metal connection layer is formed on the second dielectric layer.
[0025] The dielectric layer is deposited on the entire surface by chemical vapor deposition or atomic layer deposition.
[0026] Optionally, step 4) includes:
[0027] 4.1) forming a temporary protection layer on the first device region; the temporary protection layer covers the gate metal, the region between the gate metal and the source metal and the drain metal, and at least a portion of the source metal and the drain metal;
[0028] 4.2) depositing a whole layer of the second dielectric layer on the surface of the integrated circuit chip;
[0029] 4.3) removing the second dielectric layer on the temporary protective layer;
[0030] 4.4) Remove the temporary protective layer.
[0031] Optionally, the material of the temporary protective layer is PBO, PI, BCB, photoresist, alloy material or metal oxide; the temporary protective layer and the dielectric layer have different etching removal selectivity and are removed in different ways. The temporary protective layer and the dielectric layer have large chemical property differences so as to be removed in layers.
[0032] Optionally, the temporary protective layer is a photosensitive polymer material, which is formed on the first device area by coating and formed by curing, and the coating thickness is such that a flat upper surface can be formed after curing; in step 4.4), the temporary protective layer is removed by a development reaction.
[0033] Optionally, a capacitor region is further provided on the first dielectric layer outside the first device region; in step 3), metal is simultaneously deposited on the capacitor region to form a lower electrode; in step 4), the second dielectric layer simultaneously covers the lower electrode, and the portion located on the upper surface of the lower electrode forms a capacitor dielectric layer; in step 5), metal is simultaneously deposited on the capacitor region to form an upper electrode.
[0034] A radio frequency module, characterized by comprising the above-mentioned integrated circuit chip.
[0035] Optionally, the first device region is a HEMT device, and the HEMT device is used for a low noise amplifier in a radio frequency module.
[0036] The radio frequency module is applied to base stations, radars, communications or remote sensing, etc.
[0037] The beneficial effects of the present invention are:
[0038] 1) The thickness of the dielectric layer in the gate and nearby areas of the device area of the integrated circuit chip is less than the thickness of the dielectric layer in the area far away from the gate, which reduces the parasitic capacitance between the gate and the source and drain electrodes and improves the noise characteristics and other performance of the device;
[0039] 2) During the multi-step dielectric layer deposition process on the integrated circuit chip, the dielectric layers before and after are separated by a temporary protective layer in the active area of the device, and then the dielectric layer on the temporary protective layer and the temporary protective layer are removed to prevent the thickness of the dielectric layer in and around the device gate from being thickened due to other processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 is a process flow chart of the method for manufacturing an integrated circuit chip of Example 1, showing the structure obtained in each step;
[0041] Figure 2 This is a schematic diagram of the structure of the integrated circuit chip obtained in Example 1;
[0042] Figure 3 for Figure 2 Schematic diagram of the local structure in;
[0043] Figures 4 to 12 The schematic diagram of the structure obtained by each step of the method for manufacturing the integrated circuit chip of Example 2, wherein:
[0044] Figure 4 is a schematic diagram of forming a first dielectric layer;
[0045] Figure 5 is a schematic diagram of forming a first metal structure layer;
[0046] Figure 6 A schematic diagram of forming a temporary protective layer;
[0047] Figure 7 is a schematic diagram of forming a second dielectric layer;
[0048] Figure 8 is a schematic diagram of etching the second dielectric layer;
[0049] Fig. 9 Schematic diagram for removing the temporary protective layer;
[0050] Fig.10 A top view showing the positional relationship between etching positions of the first metal structure layer and the second dielectric layer;
[0051] Fig.11 is a schematic diagram of forming a second metal structure layer;
[0052] Fig.12 A schematic diagram of the structure of an integrated circuit chip after the third dielectric layer is formed;
[0053] Fig.13 for Fig.12 A partial schematic diagram of the capacitor part;
[0054] Fig.14 for Fig.12 A partial schematic diagram of the first device region;
[0055] Fig.15 is a schematic structural diagram of an integrated circuit chip of Example 3;
[0056] Fig.16 This is a schematic diagram of the structure of the integrated circuit chip of Example 4. DETAILED DESCRIPTION
[0057] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions can be adjusted according to design requirements. The upper and lower relationships of the relative elements and the definitions of the front / back in the figures described in the text should be understood by those skilled in the art to refer to the relative positions of the components, so they can all be flipped to present the same components, which should all fall within the scope disclosed in this specification.
[0058] Example 1
[0059] The following references Figure 1 The method for manufacturing the integrated circuit chip of Example 1 is described.
[0060] The integrated circuit chip of Embodiment 1 that has completed a part of the device manufacturing process comprises an epitaxial structure 1, Figure 1 1 shows a first device region formed by device isolation of the epitaxial structure 1, which is used as an active region and is provided with a source metal S, a drain metal D and a gate metal G, wherein the gate metal G is located between the source metal S and the drain metal D. The source electrode S and the drain electrode D may respectively include Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. The source electrode S and the epitaxial structure 1 may form an ohmic contact therebetween, and the drain electrode D and the epitaxial structure 1 may form an ohmic contact therebetween.
[0061] The epitaxial structure of this embodiment may include a plurality of semiconductor layers disposed on a substrate. In a specific embodiment, the integrated circuit chip includes a high electron mobility transistor structure, and the semiconductor layer may include a buffer layer, a channel layer, a barrier layer, a barrier layer (e.g., a Schottky barrier layer), an isolation layer, a cap layer, any suitable layer or a combination of the foregoing, but is not limited thereto. A two-dimensional electron gas (two-dimensional electron gas, referred to as 2DEG) may be present approximately at the interface between the channel layer and the isolation layer. The material of the semiconductor layer may include one or more III-V semiconductors (e.g., GaAs, GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, AlGaAsP, InAlGaAs, InGaP, InGaPAs, AlInGaP, or a combination of the foregoing or a combination of the foregoing). The semiconductor layer can be formed by a deposition process including molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), similar processes or combinations thereof. In a specific embodiment, the epitaxial structure is a gallium arsenide-based pHEMT epitaxial structure, and its basic structure can be, for example, n+AlGaAs / i-InGaAs / i-GaAs type, with a double heterojunction, which not only improves the temperature stability of the device threshold voltage, but also improves the output volt-ampere characteristics of the device, so that the device has a larger output resistance, a higher transconductance, a larger current handling capacity, and a higher operating frequency.
[0062] refer to Figure 1 (a), a first dielectric layer 2 with a thickness of 50 to 100 nm is entirely covered on the surface of the integrated circuit chip by a plasma enhanced chemical vapor deposition (PECVD) process. The first dielectric layer 2 is etched to form a first opening 21 on the source metal S and the drain metal D. The material of the first dielectric layer 2 can be silicon nitride, silicon oxide, silicon oxynitride or aluminum oxide. In other embodiments, the first dielectric layer can also be entirely deposited by atomic layer deposition.
[0063] refer to Figure 1(b) A patterned first metal connection layer 3 is formed on the first dielectric layer 2 through a metal process, and the first metal connection layer 3 is in contact with the source metal S and the drain metal D through the first opening 21. The first metal connection layer 3 can be made of a metal material such as Co, W, Ru, Al, Mo, Ti, Cu, Au, Pt, a metal alloy, other suitable conductive materials, or a combination thereof.
[0064] refer to Figure 1 (c) Coating PBO (poly(p-phenylene benzobisoxazole)) material on the first dielectric layer 2 as a temporary protective layer 4, the coverage area of which includes the gate metal G and the area between the gate metal G and the source metal S and the drain metal D, and the edge covers the partial area above the source metal S and the drain metal D, but does not cover the first metal connection layer 3 above the source metal S and the drain metal D; the distance between the edge and the edge of the source metal S and the drain metal D close to the gate metal G is greater than 0.1 μm; the thickness is sufficient to form a smooth upper surface (i.e., a certain height higher than the highest structural surface of the coverage area), for example, 2 to 5 microns. After coating, baking and curing are performed once, the temperature is 300°C, and the time is 30 minutes, so as to reduce the deformation of the PBO material caused by high temperature in the subsequent process and prevent the silicon nitride material that is sensitive to stress changes from delamination or cracking.
[0065] refer to Figure 1 (d) Plasma enhanced chemical vapor deposition (PECVD) is used to deposit the second dielectric layer 5 on the entire surface, with a deposition temperature of 290° C. and a deposition thickness of 100-200 nm, so that the second dielectric layer 5 covers the surface of the temporary protective layer 4 in the active area. Specifically, the second dielectric layer 5 can be a silicon nitride film.
[0066] refer to Figure 1 (e) The second dielectric layer 5 on the surface of the temporary protective layer 4 is etched away to completely expose the temporary protective layer 4. Since the PBO material is a photosensitive material, the temporary protective layer 4 is directly exposed using a photolithography machine. The light waves in the i-line band will cause the exposure area to produce photoacid, so that the PBO material in this area can be dissolved in the aqueous developer, and this part of the PBO material is removed. As a result, the second dielectric layer 5 in the area covered by the temporary protective layer 4 is separated from the first dielectric layer 2 and removed, forming a second opening 51, which does not affect the quality of the first dielectric layer 2.
[0067] refer to Figure 1(f), the second dielectric layer 5 on the first metal connection layer 3 above the source metal S and the drain metal D is etched to form a third opening 52, and a patterned second metal connection layer 6 is formed on the second dielectric layer 5 through a metal process. The second metal connection layer 6 contacts the first metal connection layer 3 on the source metal S and the drain metal D through the third opening 52, thereby forming a thickened metal of the source metal S and the drain metal D to improve the flow capacity. In other areas, the first metal connection layer 3 and the second metal connection layer 6 are insulated and separated by the second dielectric layer 5 to meet the wiring requirements. A layer of silicon nitride film is deposited on the entire surface by a plasma enhanced chemical vapor deposition (PECVD) process as the third dielectric layer 7, with a thickness of 50 to 600 nm, which is used to protect the structure in the aforementioned process from erosion by water vapor and temperature changes in the external environment.
[0068] refer to Figure 2 and Figure 3 The obtained integrated circuit chip includes an epitaxial structure 1, a first dielectric layer 2, a first metal connection layer 3, a second dielectric layer 5, a second metal connection layer 6 and a third dielectric layer 7. The epitaxial structure 1 has a first device region through device isolation, and the periphery of the first device region is an isolation region 1a. The first device region is provided with a source metal S, a drain metal D and a gate metal G, and the gate metal G is located between the source metal S and the drain metal D. The first dielectric layer 2 covers the surface of the epitaxial structure 1, the source metal S, the drain metal D and the gate metal G, and has a first opening 21 on the source metal S and the drain metal D. The first metal connection layer 3 is formed on the first dielectric layer 2, and contacts the source metal S and the drain metal D respectively through the first opening 21. The second dielectric layer 5 covers the first metal connection layer 3 and the surface of the first dielectric layer 2, and forms a second opening 51 in the first device region, the second opening 51 exposes the gate metal G, the region between the gate metal G and the source metal S, the drain metal D, and the first dielectric layer 2 on part of the source metal S and the drain metal D; the second dielectric layer 5 has a third opening 52 on the first metal connection layer 3 on the source metal S and the drain metal D, respectively, the second metal connection layer 6 is formed on the second dielectric layer 5, and contacts the first metal connection layer 3 through the third opening 52. The third dielectric layer 7 covers the surface of the above structure.
[0069] In this embodiment, there is a dielectric layer for insulating and spacing adjacent metal wiring layers outside the active area of the pHEMT device, and the dielectric layer does not exist in the active area of the pHEMT device, which reduces the thickness of the dielectric layer deposited in the active area of the pHEMT device during multiple dielectric layer depositions of the integrated circuit (equivalent to reducing the thickness of the second dielectric layer in this embodiment). The noise characteristics of the gallium arsenide pHEMT are sensitive to the thickness of the silicon nitride film, and the noise characteristics of the pHEMT device are further reduced by reducing the number of silicon nitride deposition layers.
[0070] Example 2
[0071] refer to Figures 4 to 12 , Example 2 is described by taking a method for manufacturing an integrated circuit including a capacitor and a HEMT device as an example.
[0072] refer to Figure 4 The integrated circuit chip that has completed some device processes includes a gallium arsenide-based HEMT epitaxial structure 1'. The epitaxial structure 1' forms a first device area A through device isolation. As an active area, it is provided with a source metal S, a drain metal D and a gate metal G, that is, a pHEMT device is formed. A capacitor area B is planned outside the first device area A. A layer of silicon nitride film is entirely covered on the surface of the integrated circuit chip by plasma enhanced chemical vapor deposition (PECVD) process as a first dielectric layer 2 with a thickness of 50 to 100 nm. The first dielectric layer 2 is etched to form a first opening 21 on the source metal S and the drain metal D.
[0073] refer to Figure 5 , a patterned first metal structure layer is formed on the first dielectric layer 2 through a metal process, and the first metal structure layer includes a first metal connection layer 81 and a capacitor lower electrode plate 82; the first metal connection layer 81 is arranged on the chip surface according to the wiring requirements, and extends to the source metal S and the drain metal D of the active area, and is connected to the source metal S and the drain metal D through the first opening 21, and the part located above the source metal S and the drain metal D constitutes the source metal plate and the drain metal plate together with the source metal S and the drain metal D, and the capacitor lower electrode plate 82 is located on the capacitor area B. The first metal structure layer 8 is made by the same metal process, for example, the patterning can be achieved by evaporating the entire layer of metal and then etching.
[0074] refer to Figure 6 , a PBO (poly(p-phenylene benzobisoxazole)) material is coated on the first dielectric layer 2 as a temporary protective layer 9, the covering area of which includes the entire first device area A, that is, covering the gate metal G, the source metal S, the drain metal D and the area between them, that is, covering the first metal connection layer 81 in the first device area A; the thickness is sufficient to form a smooth upper surface (that is, a certain height higher than the highest structural surface of the covering area), for example, 2 to 5 microns. After coating, baking and curing are performed as in Example 1.
[0075] refer to Figure 7 A layer of silicon nitride film is deposited on the entire surface as the second dielectric layer 10 by plasma enhanced chemical vapor deposition (PECVD) process, the deposition temperature is 290°C, and the deposition thickness is 100-200nm. The second dielectric layer 5 covers the surface of the temporary protection layer 9 in the first device area A and covers the surface of the lower plate 82 of the capacitor in the capacitor area B.
[0076] refer to Figure 8, the second dielectric layer 10 on the surface of the temporary protection layer 9 is etched away, so that the temporary protection layer 9 is completely exposed.
[0077] refer to Fig. 9 , the temporary protective layer 9 is removed by exposure and development reaction process. Thus, the second dielectric layer 10 in the area covered by the temporary protective layer 9 is separated from the first dielectric layer 2 and removed, without affecting the quality of the first dielectric layer 2. That is, the second dielectric layer 10 forms a second opening 10a in the first device area A, and the edge of the opening 10a is located outside the source metal S and the drain metal D. The top view thereof is shown in FIG. Fig.10 .
[0078] refer to Fig.11 , a patterned second metal structure layer is formed on the second dielectric layer 10 through a metal process, and the second metal structure layer includes a second metal connection layer 111 and a capacitor upper plate 112; the second metal connection layer 111 is also arranged on the chip surface according to the wiring requirements, and it extends to the source metal S and the drain metal D in the active area and is directly deposited on the first metal connection layer 81 above the source metal S and the drain metal D. It serves as a thickened metal of the source and drain to improve the current capacity; the capacitor upper plate 112 is located on the second dielectric layer 10 in the capacitor area B, so that the second dielectric layer 10 in the capacitor area B sandwiched between the capacitor lower plate 82 and the capacitor upper plate 112 is used as a capacitor dielectric layer to form a MIM capacitor. The second metal structure layer 11 is made by the same metal process, for example, it can be patterned by evaporating a whole layer of metal and then etching.
[0079] refer to Fig.12 A layer of silicon nitride film is deposited on the entire surface by plasma enhanced chemical vapor deposition (PECVD) process as the third dielectric layer 12 with a thickness of 50 to 300 nm. Its function is to protect the structure in the aforementioned process from being corroded by water vapor and temperature changes in the external environment.
[0080] Combination Figure 12 to Figure 14The obtained integrated circuit chip includes a first device area A isolated by an isolation area 1a and a capacitor B located outside the first device area A, the first device area is provided with a source metal S, a drain metal D and a gate metal G, and the gate metal G is located between the source metal S and the drain metal D; it also includes a first metal connection layer 81, a second metal connection layer 111, a first dielectric layer 2, a second dielectric layer 10 and a third dielectric layer 12; the capacitor includes a capacitor lower plate 82, a capacitor dielectric layer and a capacitor upper plate 112; the first dielectric layer 2 covers the surface of the epitaxial structure 1 of the chip as well as the source metal S, the drain metal D and the gate metal G, and has a first opening 21 above the source metal S and the drain metal D respectively; the capacitor The capacitor lower plate 82 and the first metal connection layer 81 are arranged in the same layer, and are arranged on the first dielectric layer 2, and the first metal connection layer 81 extends to a partial area on the source metal S and the drain metal D and is connected to the source metal S and the drain metal D through the first opening 21; the second dielectric layer 10 covers the first dielectric layer 2, the capacitor lower plate 82 and the first metal connection layer 81, and has a second opening 10a in the first device area A; the capacitor upper plate 112 and the second metal connection layer 111 are arranged in the same layer, and are arranged on the second dielectric layer, and the second metal connection layer 111 extends to the part above the source metal S and the drain metal D and is directly connected to the first metal connection layer 81, and the third dielectric layer 12 is formed in the outermost layer.
[0081] The second dielectric layer 10 is sandwiched between the capacitor lower plate 82 and the capacitor upper plate 112 to form a capacitor dielectric layer, and does not cover the first device area A, that is, the surface of the gate metal G in the first device area A, the surface of the area between the gate metal G and the source metal S and the drain metal D, and the surface of the source metal S and the drain metal D close to the gate metal G. The third dielectric layer 12 is directly deposited on the first dielectric layer 2, avoiding the influence of the capacitor dielectric layer on the first device area A during the manufacture of the integrated circuit, reducing the silicon nitride thickness of the first device area A, and reducing noise.
[0082] The obtained integrated circuit chip can be used in a radio frequency module, wherein the HEMT device is applied to a low noise amplifier (LNA) in the radio frequency module. By controlling the thickness of the silicon nitride film in the active area of the HEMT device in the integrated circuit process, the noise coefficient of the amplifier is reduced to obtain better performance. The above-mentioned radio frequency module is applied to base stations, radars, communications or remote sensing and other fields.
[0083] In addition, other materials that can separate the first dielectric layer and the second dielectric layer and can be removed without damaging the dielectric layer and the metal layer can be used to make the temporary protective layer, such as polymer materials such as PBO, PI, BCB, photoresist, alloy materials, or metal oxides, etc. As long as the temporary protective layer material and the dielectric layer material have sufficiently large chemical property differences, such as etching selectivity differences.
[0084] Example 3
[0085] refer to Fig.15 The integrated circuit chip of embodiment 3 comprises an epitaxial structure 1, a first dielectric layer 2, a first metal connection layer 3, a second dielectric layer 5, a second metal connection layer 6 and a third dielectric layer 7. The epitaxial structure 1 has a first device region through device isolation, and the periphery of the first device region is an isolation region 1a. The first device region is provided with a source metal S, a drain metal D and a gate metal G, and the gate metal G is located between the source metal S and the drain metal D. The first dielectric layer 2 covers the surface of the epitaxial structure 1, the source metal S, the drain metal D and the gate metal G, and the first metal connection layer 3 is formed on the first dielectric layer 2 outside the isolation region 1a. The second dielectric layer 5 covers the surface of the first metal connection layer 3 and the first dielectric layer 2 and has an opening 5a, and the opening 5a exposes the gate metal G, the area between the gate metal G and the source metal S and the drain metal D, and the first dielectric layer 2 on the source metal S and the drain metal D; the second dielectric layer 5 has an opening 5b on the first metal connection layer 3, and the second metal connection layer 6 is formed on the second dielectric layer 5 and contacts the first metal connection layer 3 through the opening 5b. The third dielectric layer 7 covers the surface of the above structure.
[0086] The process of this embodiment is carried out with reference to the process of Embodiment 1, and the range of the opening of the second dielectric layer located in the first device region can be adjusted by simply adjusting the coverage of the temporary protection layer.
[0087] In this embodiment, the first metal connection layer 3 and the second metal connection layer 6 are not connected to the source metal S and the drain metal D, and are suitable for other device connection requirements of the integrated circuit chip.
[0088] Example 4
[0089] refer to Fig.16The integrated circuit chip of embodiment 4 comprises an epitaxial structure 1, a first dielectric layer 2, a first metal connection layer 3, a second dielectric layer 5, a second metal connection layer 6, a third dielectric layer 7 and a fourth dielectric layer 13. The epitaxial structure 1 has a first device region through device isolation, and the periphery of the first device region is an isolation region 1a. The first device region is provided with a source metal S, a drain metal D and a gate metal G, and the gate metal G is located between the source metal S and the drain metal D. The first dielectric layer 2 covers the surface of the epitaxial structure 1, the source metal S, the drain metal D and the gate metal G, and has a first opening 21 on the source metal S and the drain metal D. The first metal connection layer 3 is formed on the first dielectric layer 2, and contacts the source metal S and the drain metal D respectively through the first opening 21. The second dielectric layer 5 and the fourth dielectric layer 13 cover the surface of the first metal connection layer 3 and the first dielectric layer 2, and form a second opening 51 and a fourth opening 131 in the first device region, respectively. The second opening 51 and the fourth opening 131 expose the gate metal G, the area between the gate metal G and the source metal S and the drain metal D, and the first dielectric layer 2 on part of the source metal S and the drain metal D; the second metal connection layer 6 is formed on the fourth dielectric layer 13. The third dielectric layer 7 covers the surface of the above structure.
[0090] In this embodiment, openings are provided in the first device region for the plurality of dielectric layers, which further reduces the thickness of the dielectric layer in the gate metal and the surrounding area and is applicable to different connection and process requirements.
[0091] The above embodiments are only used to further illustrate a method for manufacturing and applying an integrated circuit chip of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. An integrated circuit chip, characterized in that: The invention comprises an epitaxial structure, wherein the epitaxial structure has a first device region, wherein the first device region is provided with a source metal, a drain metal and a gate metal, and the gate metal is located between the source metal and the drain metal; a first metal connection layer, a second metal connection layer and a dielectric layer are provided on the epitaxial structure, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer in sequence, wherein the first dielectric layer covers the surfaces of the epitaxial structure, the source metal, the drain metal and the gate metal, and the first metal connection layer is formed on the first dielectric layer; The second dielectric layer covers the first metal connection layer and the surface of the first dielectric layer, and forms an opening in the first device region; the opening exposes the gate metal, the region between the gate metal and the source metal and the drain metal, and the first dielectric layer on at least part of the source metal and the drain metal; The second metal connection layer is formed on the second dielectric layer.
2. The integrated circuit chip according to claim 1, characterized in that: The distance between the edge of the opening and the edge of the source metal and the drain metal close to the gate metal is greater than 0.1 μm.
3. The integrated circuit chip according to claim 1, characterized in that: The thickness of the first dielectric layer is 50-100 nm.
4. The integrated circuit chip according to claim 1, characterized in that: The thickness of the second dielectric layer is 100-200 nm.
5. The integrated circuit chip according to claim 1, characterized in that: At least one of the first metal connection layer and the second metal connection layer extends above the source metal and the drain metal and penetrates through the dielectric layer to connect with the source metal and the drain metal.
6. The integrated circuit chip according to claim 5, characterized in that: The first metal connection layer extends above the source metal and the drain metal and penetrates the first dielectric layer to be connected to the source metal and the drain metal. The second metal connection layer extends above the source metal and the drain metal and penetrates the second dielectric layer to be connected to the first metal connection layer.
7. The integrated circuit chip according to claim 5, characterized in that: The edge of the opening is located on the outer side of the source metal and the drain metal away from the gate metal, the first metal connection layer extends to the top of the source metal and the drain metal and penetrates the first dielectric layer to be connected to the source metal and the drain metal, and the second metal connection layer extends and is stacked on the surface of the first metal connection layer above the source metal and the drain metal.
8. The integrated circuit chip according to claim 1, characterized in that: It also includes a third dielectric layer, which is located on the surface of the integrated circuit chip and has a thickness of 50-600 nm.
9. The integrated circuit chip according to claim 1, characterized in that: The material of the dielectric layer is at least one of silicon nitride, silicon oxide, silicon oxynitride and aluminum oxide.
10. The integrated circuit chip according to claim 1, characterized in that: The first device region forms a pHEMT device or a HEMT device.
11. The integrated circuit chip according to claim 1, characterized in that: It also includes a capacitor structure, which is located on the first dielectric layer outside the first device area and includes a lower plate, an upper plate and a capacitor dielectric layer, and the capacitor dielectric layer is sandwiched between the upper plate and the lower plate.
12. The integrated circuit chip according to claim 11, characterized in that: The lower electrode plate and the upper electrode plate are respectively arranged on the same layer as the first metal connection layer and the second metal connection layer, and the capacitor dielectric layer is formed by the second dielectric layer.
13. A method for manufacturing an integrated circuit chip, characterized in that: The following steps are involved: 1) providing an epitaxial structure, the epitaxial structure having a first device region, wherein a source metal, a drain metal and a gate metal are provided on the first device region, and the gate metal is located between the source metal and the drain metal; 2) forming a first dielectric layer, wherein the first dielectric layer covers the surfaces of the epitaxial structure, the source metal, the drain metal and the gate metal; 3) depositing metal to form a first metal connection layer, wherein the first metal connection layer is formed on the first dielectric layer; 4) forming a second dielectric layer, the second dielectric layer covers the first metal connection layer and the surface of the first dielectric layer, and forming an opening in the first device region; the opening exposes the gate metal, the region between the gate metal and the source metal and the drain metal, and the first dielectric layer on at least part of the source metal and the drain metal; 5) Depositing metal to form a second metal connection layer, wherein the second metal connection layer is formed on the second dielectric layer.
14. The method according to claim 13, characterized in that: Step 4) includes: 4.1) forming a temporary protection layer on the first device region; the temporary protection layer covers the gate metal, the region between the gate metal and the source metal and the drain metal, and at least a portion of the source metal and the drain metal; 4.2) depositing a whole layer of the second dielectric layer on the surface of the integrated circuit chip; 4.3) removing the second dielectric layer on the temporary protective layer; 4.4) Remove the temporary protective layer.
15. The manufacturing method according to claim 14, characterized in that: The material of the temporary protection layer is PBO, PI, BCB, photoresist, alloy material or metal oxide; the temporary protection layer and the dielectric layer have different etching removal selectivity ratios and are removed in different ways.
16. The manufacturing method according to claim 15, characterized in that: The temporary protective layer is a photosensitive polymer material, which is formed on the first device area by coating and formed by curing. The coating thickness is such that a flat upper surface can be formed after curing. In step 4.4), the temporary protective layer is removed by a development reaction.
17. The manufacturing method according to claim 13, characterized in that: A capacitor region is also provided on the first dielectric layer outside the first device region; in step 3), metal is simultaneously deposited on the capacitor region to form a lower electrode; in step 4), the second dielectric layer simultaneously covers the lower electrode, and the portion located on the upper surface of the lower electrode forms a capacitor dielectric layer; in step 5), metal is simultaneously deposited on the capacitor region to form an upper electrode.
18. A radio frequency module, characterized in that: An integrated circuit chip comprising any one of claims 1 to 12.
19. The radio frequency module according to claim 18, characterized in that: The first device area is a HEMT device, and the HEMT device is used for a low noise amplifier in a radio frequency module.
20. The radio frequency module according to claim 19 is applied to base stations, radars, communications or remote sensing.