Display substrate, manufacturing method thereof and display mother board

Abstract

The invention provides a display substrate, a manufacturing method of the display substrate and a display mother board, the display substrate comprises a middle area and an edge area located on the periphery of the middle area, and the middle area comprises a plurality of panel units distributed in an array mode; the display substrate comprises a substrate body, a first electrode and a second electrode, the panel circuit is located on the substrate base plate, and the panel circuit comprises at least one of a touch control circuit and a display circuit; the panel circuit is electrically connected to the test circuit, and the orthographic projection of the panel circuit and the orthographic projection of the test circuit on the substrate are both located in the middle area, so that gaps are reserved between the panel circuit and the edge of the substrate as well as between the test circuit and the edge of the substrate. According to the display substrate, the manufacturing method of the display substrate and the display mother board, electrostatic damage can be reduced, and the electrostatic protection effect can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display motherboard. Background Art

[0002] When display screens are produced on the production line, static electricity burns the internal circuits, resulting in a large number of NG (unqualified) products being detected, causing great losses. Summary of the invention

[0003] The embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, and a display motherboard, which can reduce electrostatic damage and improve electrostatic protection effects.

[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0005] According to a first aspect of the present disclosure, the present disclosure provides a display substrate, the display substrate comprising a middle area and an edge area located at the periphery of the middle area, the middle area comprising a plurality of panel units distributed in an array; the display substrate comprises:

[0006] substrate substrate;

[0007] A panel circuit, the panel circuit is located on the base substrate, and the panel circuit includes at least one of a touch circuit and a display circuit; and

[0008] The panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the substrate are both located in the middle area, so that a distance is maintained between the panel circuit and the test circuit and the edge of the substrate.

[0009] Exemplarily, the test circuit includes multiple first test lines and multiple second test lines, the multiple first test lines and the multiple second test lines are cross-connected to each other to form a mesh circuit structure, and the first test lines are electrically connected to the panel lines for applying electrical test signals to the panel lines.

[0010] Exemplarily, a test line; multiple second test lines include a third edge test line and a fourth edge test line which are arranged closest to the edge area; wherein each of the first test lines has two opposite ends along its own extension direction respectively connected to the third edge test line and the fourth edge test line, and each of the second test lines has two opposite ends along its own extension direction respectively connected to the first edge test line and the second edge test line.

[0011] Exemplarily, the first test line and the second test line cross each other to define a plurality of sub-areas, and each sub-area includes at least two panel units.

[0012] Exemplarily, the display substrate further includes:

[0013] The peripheral circuit is arranged in the edge area around the middle area, and any one of the panel circuit and the test circuit is separated from the peripheral circuit to be disconnected from each other, and the routing of the peripheral circuit is led out to the edge of the substrate.

[0014] Exemplarily, the peripheral circuit includes:

[0015] a closed loop, the closed loop being disposed around the middle area; and

[0016] At least one lead is connected to the closed loop and extends from the closed loop to the edge of the substrate.

[0017] Exemplarily, the peripheral circuit also includes: multiple electrostatic release points, a gap is maintained between the electrostatic release point and the closed loop, the gap is configured to be broken down by static electricity, the multiple electrostatic release points are distributed in sequence along the routing direction of the closed loop, and the orthographic projection on the substrate is located between the orthographic projection of the closed loop on the substrate and the middle area.

[0018] Exemplarily, the display substrate further includes an alignment mark pattern distributed in the edge region; the orthographic projection of the electrostatic discharge point on the base substrate and the orthographic projection of the alignment mark pattern on the base substrate are separated from each other to be disconnected from each other.

[0019] Exemplarily, there are a plurality of leads, and the plurality of leads are sequentially spaced apart and distributed along the routing direction of the closed loop, and the orthographic projections of the plurality of leads on the substrate are located at the periphery of the closed loop.

[0020] Exemplarily, the test circuit includes multiple first test lines and multiple second test lines, and the multiple first test lines and the multiple second test lines are cross-connected to each other; the multiple leads include multiple first leads and / or multiple second leads; wherein, the first leads are parallel to and staggered in the extension direction of the first test lines, and the second leads are parallel to and staggered in the extension direction of the second test lines.

[0021] Exemplarily, at least one of the test circuit and the panel circuit includes a metal routing pattern, and the metal routing pattern is provided in the same layer and with the same material as the peripheral circuit.

[0022] According to the second aspect of the present disclosure, an embodiment of the present disclosure provides a display motherboard, including multiple substrate units, with a cutting line area between adjacent substrate units, and the substrate units are constructed to form the display substrate described above after being cut along the cutting line area.

[0023] According to a second aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a display substrate, wherein the display substrate comprises a middle region and an edge region located outside the middle region, wherein the middle region comprises a plurality of panel units distributed in an array; the method comprises the following steps:

[0024] Providing a substrate;

[0025] forming a pattern of the test circuit on the base substrate;

[0026] A pattern of the panel circuit is formed on the base substrate, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the base substrate are both located in the middle area, so that a spacing is maintained between the panel circuit and the test circuit and the edge of the base substrate.

[0027] Exemplarily, the method further includes:

[0028] A pattern of peripheral circuits is formed on the base substrate, wherein the peripheral circuits are arranged in the edge area around the middle area, and any one of the panel circuits and the test circuits is separated from the peripheral circuits to be disconnected from each other.

[0029] Exemplarily, at least one of the test circuit and the panel circuit includes a metal wiring pattern, and the pattern of the peripheral circuit and the metal wiring pattern are formed by a same patterning process.

[0030] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0031] The display substrate and its manufacturing method, and the display motherboard provided by the embodiments of the present disclosure, the panel circuit and the test circuit in the display substrate are both located in the middle area of ​​the base substrate, and a distance is maintained between the panel circuit and the test circuit and the edge of the base substrate. In this way, static electricity can be prevented from being introduced from the edge of the base substrate to the panel circuit and the test circuit, thereby reducing the damage to the panel circuit and the test circuit caused by static electricity and improving the static electricity protection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram showing the structure of a display substrate provided by an embodiment of the present disclosure;

[0033] Figure 2A schematic diagram showing the structure of a display motherboard provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] Before describing in detail the display substrate and the manufacturing method thereof and the display motherboard provided by the embodiments of the present disclosure, it is necessary to describe the related technologies as follows:

[0037] In the related art, in the manufacturing process of the display panel, in the array production process, the product is a large glass substrate with touch circuits and / or display circuits, i.e., Q-Panel. Each Q-Panel contains several small single cells (panel units). In order to prevent defective panel units in the Q-Panel from flowing into the next process, each Q-Panel needs to be inspected. Therefore, a test circuit for applying an electrical test signal to the panel circuit is also arranged on the Q-Panel.

[0038] When display panels such as touch screens (TSP) are produced on the production line, many NG (unqualified) products are detected, resulting in large losses. The inventors of the present disclosure have found through microscopic inspection of the internal circuits of the display screen that the internal circuits of the display screen, such as bonding pins (bridge pins for binding) and the bridge points of the Tx (transmission) touch lines and the Rx (reception) touch lines in the touch circuits, are burned by static electricity (ESD) at relatively vulnerable locations.

[0039] Q-Panel is cut from a large motherboard, and each Q-Panel includes multiple panel units. Each Q-Panel can be electrically tested before being cut to form a single panel unit. The inventor of the present disclosure has found through research that the cause of the above-mentioned electrostatic burn phenomenon is that when the motherboard is cut, the test circuit will be cut and disconnected at the cutting position between two adjacent Q-Panels. Therefore, the test circuit on the Q-Panel formed after cutting is led out to the edge of the substrate, that is, the internal panel circuit of the panel unit is led out to the edge of the substrate. In the subsequent production process, static electricity is introduced into the internal panel circuit of the panel unit through the edge of the substrate, so that the most vulnerable area of ​​the panel circuit inside the panel unit is burned.

[0040] In order to solve the above problems, the embodiments of the present disclosure provide a display substrate (Q-Panel) and a manufacturing method thereof, and a display motherboard, which can improve the electrostatic protection effect of the product and reduce the circuit burn phenomenon caused by static electricity.

[0041] The embodiment of the present disclosure provides a display substrate, which can be formed by cutting a large display motherboard, and the display substrate can be cut to form a plurality of single cells.

[0042] like Figure 1 As shown, the display substrate 10 provided in the embodiment of the present disclosure includes a middle area S1 and an edge area S2 located outside the middle area S1, wherein the middle area S1 includes a plurality of panel units A distributed in an array; the display substrate 10 includes:

[0043] Base substrate 11;

[0044] A panel circuit (not shown in the figure), the panel circuit is located on the base substrate 11, and the panel circuit includes at least one of a touch circuit for realizing a touch function and a display circuit for realizing a display function; and

[0045] The test circuit 12, the panel circuit is electrically connected to the test circuit 12, and the orthographic projections of the panel circuit and the test circuit 12 on the base substrate 11 are both located in the middle area S1, so that the panel circuit and the test circuit 12 are both spaced from the edge of the base substrate 11 and are no longer led out to the edge of the base substrate 11.

[0046] In the above scheme, the display substrate 10 provided in the embodiment of the present disclosure is a Q-Panel, and its panel circuit refers to various panel internal wirings used to realize the panel function. For example, the panel circuit may include at least one of a touch circuit and a display circuit, the touch circuit is used to realize the touch function of the display panel, and the display circuit is used to realize the display function of the display panel. It should be understood that the figure only illustrates the distribution position of the panel circuit, etc., and does not represent the actual wiring of the panel circuit. The test circuit 12 can be used to apply electrical test signals to the panel circuit. Any of the panel circuit and the test circuit 12 is constructed to be located in the middle area S1 of the base substrate 11, and to retain a spacing between the edge of the base substrate 11, and no longer lead to the edge of the base substrate 11. In this way, static electricity introduced from the edge of the base substrate 11 can be avoided from being introduced into the panel circuit and the test circuit 12, thereby reducing the damage of static electricity to the panel circuit and the test circuit 12, and improving the static electricity protection effect.

[0047] It should be noted that according to the working principle of the touch screen and the medium for transmitting information, the touch screen can be divided into four categories, namely resistive, capacitive, infrared and surface acoustic wave touch screens. The most widely used are resistive and capacitive. Among them, projected capacitive is the most widely used because it can realize multi-touch applications. Their main disadvantages are high cost and heavy weight. Low cost and thinness have become the new trend in the current touch field. In order to achieve thinness and lightness of touch panels, research on integrating touch panels and liquid crystal display panels is becoming increasingly popular. Among them, the in-cell touch solution that embeds the touch panel into the liquid crystal display panel has attracted widespread attention.

[0048] There are three types of In-Cell touch technologies: resistive, capacitive, and optical. Among them, the capacitive solution includes self-capacitive touch and mutual capacitance touch. The self-capacitive touch method is to divide the transparent conductive layer used as the common electrode (Vcom) on the array substrate into several blocks as touch electrodes, and use the touch signal line (Tx touch wiring) to connect to the touch electrode through a via at one end, and connect the other end to the driver integrated circuit. When the finger touches the array substrate, it will cause the capacitance value of the touch electrode at the corresponding position to fluctuate. The driver integrated circuit can determine the position of the touch point by detecting the fluctuation of the capacitance value, thereby realizing the touch function.

[0049] The FIC (Full In Cell Touch) touch screen integrates the touch electrodes and touch signal lines inside the array substrate, so that when the array substrate is used to make a liquid crystal display panel, the liquid crystal display panel can integrate the touch electrodes and touch signal lines used to realize the touch function inside the liquid crystal display panel to realize a liquid crystal touch display panel with an embedded touch structure. The liquid crystal touch display panel with a Full In Cell Touch structure integrates the touch function and the display function together, which can not only realize one-stop seamless production, but also has the advantages of integration, lightness, low cost, low power consumption, high image quality, and the ability to realize multiple types of touch (i.e. Multi-Touch).

[0050] The display substrate 10 provided in some embodiments of the present disclosure includes a plurality of panel units A, and its touch circuit may include a plurality of touch units A' arranged one-to-one in correspondence with the plurality of panel units A, and each touch unit A' is used to implement the touch function of the corresponding display panel. The touch circuit may include but is not limited to a circuit that uses self-capacitive touch or mutual-capacitive touch to implement the touch function.

[0051] In some exemplary embodiments of the present disclosure, as shown in the figure, the test circuit 12 includes a plurality of first test lines 121 and a plurality of second test lines 122, and the plurality of first test lines 121 and the plurality of second test lines 122 are cross-connected to each other to form a mesh line structure, wherein the first test lines 121 are electrically connected to the panel lines for applying electrical test signals to the panel lines. As shown in the figure, the orthographic projections of the first test lines 121 and the second test lines 122 on the substrate 11 may be located between adjacent panel units A.

[0052] Taking the panel circuit including a touch circuit as an example, the touch lines of the touch circuit (for example, the Tx touch line and the Rx touch line) can all be connected to the first test line 121 to apply an electrical test signal to the touch circuit through the first test line 121, and the second test line 122 is used to connect multiple first test lines 121.

[0053] by Figure 1As shown in the figure as an example, the sides of the display substrate 10 can be divided into a first side 10A, a third side 10B, a second side 10C and a fourth side 10D surrounding the middle area S1, the first side 10A is opposite to the second side 10C, and the third side 10B is opposite to the fourth side 10D. In some exemplary embodiments, as shown in the figure, the routing direction of the first test trace 121 is consistent with the extension direction of the first side 10A, and the routing direction of the second test trace 122 is consistent with the extension direction of the third side 10B. Among the two test traces closest to the edge area S2 among the multiple first test traces 121, one trace is closest to the first side 10A, recorded as the first edge test trace 121A, and the other trace is closest to the second side 10C, recorded as the second edge test trace 121B. Among the two test lines closest to the edge area S2 among the multiple second test lines 122, one line is closest to the third side 10B, recorded as the third edge test line 122A, and the other line is closest to the fourth side 10D, recorded as the fourth edge test line 122B.

[0054] See also Figure 1 As shown, the two opposite ends of each first test line 121 along its own extension direction are respectively connected to the third edge test line 122A and the fourth edge test line 122B, and the two opposite ends of each second test line 122 along its own extension direction are respectively connected to the first edge test line 121A and the second edge test line 121B. In other words, the end of each first test line 121 is connected to the second test line 122, and the end is not led out of the second test line 122; similarly, the end of each second test line 122 is connected to the first test line 121, and the end is not led out of the first test line 121.

[0055] In this way, the four test lines located closest to the edge area S2, namely the first edge test line 121A, the second edge test line 121B, the third edge test line 122A and the fourth edge test line 122B are connected to form a closed loop, and the entire grid-shaped circuit is a closed-loop grid circuit, which can further prevent static electricity from being introduced into the panel circuit.

[0056] In some exemplary embodiments of the present disclosure, Figure 1As shown, the first test trace 121 and the second test trace 122 cross each other to define a plurality of sub-areas, each of which includes at least two panel units A. In this way, each display substrate 10 is divided into a plurality of panel unit groups (Group), each panel unit group corresponds to a sub-area, and the touch circuits of each panel unit A in each panel unit group can be connected to the same test trace. Taking the figure as an example, a display substrate 10 includes 44 panel unit groups, and each panel unit group consists of 8 panel units A. Of course, it can be understood that the above is only an example. In actual applications, the number of panel unit groups and the number of panel units A in each panel unit group are not limited to this.

[0057] In some exemplary embodiments of the present disclosure, Figure 1 As shown, the display substrate 10 also includes: a peripheral circuit 13, which is arranged in the edge area S2 around the middle area S1, and any one of the panel circuit and the test circuit 12 is separated from the peripheral circuit 13 to be disconnected from each other, and the routing of the peripheral circuit 13 is led out to the edge of the base substrate 11.

[0058] By adopting the above scheme, the peripheral circuit 13 is set in the edge area S2 of the display substrate 10, that is, the peripheral circuit 13 is set around the panel circuit and the test circuit 12, and the routing of the peripheral circuit 13 can be led to the edge of the base substrate 11. In this way, the static electricity introduced into the display substrate 10 can be guided to the peripheral circuit 13 and suppressed or guided away by the peripheral circuit 13 to protect the panel circuit in the panel unit A.

[0059] In some exemplary embodiments of the present disclosure, Figure 1 As shown, the peripheral circuit 13 includes a closed loop 131 and at least one lead 132 . The closed loop 131 is arranged around the middle area S1 . The lead 132 is connected to the closed loop 131 and extends from the closed loop 131 to the edge of the base substrate 11 .

[0060] By adopting the above scheme, a closed loop 131 is set around the middle area S1 in the entire edge area S2, and the closed loop 131 can be led out to the edge of the base substrate 11 through the lead 132. In this way, the closed loop 131 can effectively suppress the static electricity introduced into the display substrate 10 from entering the various circuits in the middle area S1.

[0061] In some exemplary embodiments of the present disclosure, Figure 1As shown, the peripheral circuit 13 further includes: a plurality of electrostatic release points 133, a gap is maintained between the electrostatic release point 133 and the closed loop 131, the gap is configured to be broken down by static electricity, and the plurality of electrostatic release points 133 are sequentially spaced along the routing direction of the closed loop 131, and the orthographic projection on the base substrate 11 is located between the orthographic projection of the closed loop 131 on the base substrate 11 and the middle area S1. With the above solution, by setting the electrostatic release point 133, the electrostatic release point 133 can further effectively release static electricity.

[0062] In some exemplary embodiments, Figure 1 As shown, the display substrate 10 further includes an alignment mark pattern 14 distributed in the edge region S2; the orthographic projection of the electrostatic discharge point 133 on the base substrate 11 and the orthographic projection of the alignment mark pattern 14 on the base substrate 11 are separated from each other to be disconnected from each other.

[0063] In the above scheme, since the base substrate 11 needs to be aligned in the process of the display substrate 10, an alignment mark pattern 14 is set in the edge area S2 of the base substrate 11, and the arrangement position of the electrostatic discharge point 133 can avoid the alignment mark pattern 14. As shown in the figure, the electrostatic discharge point 133 is constructed with a line width greater than the line width of the closed loop 131 to facilitate electrostatic discharge. For example, the electrostatic discharge point 133 can be constructed as a conductive strip or conductive block structure.

[0064] In some exemplary embodiments, Figure 1 As shown, there are multiple leads 132, and the multiple leads 132 are sequentially spaced along the routing direction of the closed loop 131, and the orthographic projections of the multiple leads 132 on the base substrate 11 are located outside the closed loop 131. With the above solution, multiple leads 132 are sequentially spaced along the routing direction of the closed loop 131, which can effectively protect the excess static electricity entering the interior from the four sides of the display substrate 10. It can be understood that the specific distribution position and distribution number of the multiple leads 132 can be unlimited.

[0065] In addition, in some exemplary embodiments of the present disclosure, Figure 1 As shown, the plurality of leads 132 include a plurality of first leads 132A and a plurality of second leads 132B; wherein the first leads 132A are parallel to and staggered with the extension direction of the first test trace 121 , and the second leads 132B are parallel to and staggered with the extension direction of the second test trace 122 .

[0066] That is, as shown in the figure, the first lead 132A is parallel to the first test line 121, and the first lead 132A is not on the extension line of the first test line 121, and the second lead 132B is parallel to the second test line 122, and the second lead 132B is not on the extension line of the second test line 122. In this way, compared with the scheme of setting the first lead 132A on the extension line of the first test line 121, the spacing between the first lead 132A and the first test line 121, and between the second lead 132B and the second test line 122 can be enlarged as much as possible to further prevent the static electricity on the lead 132 from breaking through to the test line. Exemplarily, the spacing between the first lead 132A and the first test line 121 is about 15 to 20 mm; the spacing between the second lead 132B and the second test line 122 is about 15 to 20 mm. In this way, a better electrostatic protection effect can be achieved.

[0067] In addition, in some exemplary embodiments of the present disclosure, in order to facilitate electrostatic discharge, the peripheral circuit 13 can be made of metal material. Exemplarily, at least one of the test circuit 12 and the panel circuit includes a metal wiring pattern, and the metal wiring pattern is in the same layer and material as the peripheral circuit 13. With the above solution, the test circuit 12 and the metal wiring pattern can be formed simultaneously with the same patterning process to simplify the process steps.

[0068] Specifically, for example, the wiring in the test circuit 12 is made of metal material, and the test wiring is a metal wiring pattern, and the peripheral circuit 13 is made of the same material and arranged in the same layer as the test circuit 12. Of course, it can be understood that when other patterns in the panel circuit arranged in the middle area S1 are made of metal material, the peripheral circuit 13 can also be made of the same material and arranged in the same layer as the film layer.

[0069] In addition, it should be noted that Figure 1 and Figure 2 As shown, the display substrate 10 provided in the embodiment of the present disclosure is cut from a display motherboard 1, wherein the display motherboard 1 may include a plurality of substrate units 10', and a cutting line area is formed between adjacent substrate units 10'. By cutting the entire motherboard along the cutting line area, a plurality of substrate units 10' can be obtained, and one substrate unit 10' is a display substrate 10 provided in the embodiment of the present disclosure. In other words, each of the substrate units 10' is constructed to have the same circuit structure as that on the display substrate 10.

[0070] In addition, if Figure 2As shown, the embodiment of the present disclosure also provides a display motherboard 1, which includes a plurality of substrate units 10', and a cutting line area is formed between adjacent substrate units 10', and the substrate units 10' are configured to form the display substrate 10 provided in the embodiment of the present disclosure after being cut along the cutting line area. Obviously, the display motherboard 1 provided in the embodiment of the present disclosure can also bring about the beneficial effects brought by the display substrate 10 provided in the embodiment of the present disclosure, which will not be described in detail.

[0071] Furthermore, in some exemplary embodiments, Figure 2 As shown, the leads 132 between two adjacent substrate units 10' can be connected as one, and the leads 132 can be arranged in the cutting line area. When the display motherboard 1 is cut, the leads 132 between two adjacent substrate units 10' can be cut and separated.

[0072] In addition, the embodiment of the present disclosure further provides a method for manufacturing a display substrate 10, which is used to manufacture the display substrate 10 provided by the embodiment of the present disclosure, wherein the display substrate 10 includes a middle area S1 and an edge area S2 located outside the middle area S1, wherein the middle area S1 includes a plurality of panel units A distributed in an array; the method includes the following steps:

[0073] Step S01, providing a base substrate 11;

[0074] Step S02, forming a pattern of the test circuit 12 on the base substrate 11;

[0075] Step S03, forming a pattern of the panel circuit on the base substrate 11, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit 12, and the orthographic projections of the panel circuit and the test circuit 12 on the base substrate 11 are both located in the middle area S1, so that a distance is maintained between the panel circuit and the test circuit 12 and the edge of the base substrate 11.

[0076] In the above scheme, the display substrate 10 provided in the embodiment of the present disclosure is a Q-Panel, and its panel circuit refers to various panel internal wirings used to realize the panel functions. For example, the panel circuit may include at least one of a touch circuit and a display circuit. The touch circuit is used to realize the touch function of the display panel, and the display circuit is used to realize the display and other functions of the display panel. The test circuit 12 can be used to apply electrical test signals to the panel circuit. Any of the panel circuit and the test circuit 12 is constructed to be located in the middle area S1 of the base substrate 11, and to keep a spacing between the edge of the base substrate 11, and no longer lead out to the edge of the base substrate 11. In this way, static electricity introduced from the edge of the base substrate 11 can be avoided from being introduced into the panel circuit and the test circuit 12, thereby reducing the damage of static electricity to the panel circuit and the test circuit 12, and improving the static electricity protection effect.

[0077] Wherein, when the panel circuit includes a touch circuit, the touch circuit may include but is not limited to a self-capacitive touch circuit or a mutual-capacitive touch circuit.

[0078] In some exemplary embodiments, the method further comprises:

[0079] Step S04, forming a pattern of a peripheral circuit 13 on the base substrate 11, wherein the peripheral circuit 13 is arranged in the edge area S2 around the middle area S1, and any one of the panel circuit and the test circuit 12 is separated from the peripheral circuit 13 to be disconnected from each other.

[0080] By adopting the above scheme, the peripheral circuit 13 is set in the edge area S2 of the display substrate 10, that is, the peripheral circuit 13 is set on the periphery of the closed grid-like circuit structure, and the routing of the peripheral circuit 13 can be led to the edge of the base substrate 11. In this way, the static electricity introduced into the display substrate 10 can be guided to the peripheral circuit 13 and suppressed or guided away by the peripheral circuit 13 to protect the panel circuit in the panel unit A.

[0081] In some exemplary embodiments, in the method, at least one of the test circuit 12 and the panel circuit includes a metal wiring pattern, and the pattern of the peripheral circuit 13 and the metal wiring pattern are formed by the same patterning process, thereby simplifying the process steps.

[0082] In addition, it should be noted that in the above step S01, the base substrate 11 may be the base substrate of the display motherboard 1, and in the above steps S02 and S03, after forming the test circuit 12 and the panel circuit on the base substrate 11, a display motherboard is obtained. The method may further include:

[0083] Step S04 , cutting the display motherboard 1 to obtain the display substrate 10 .

[0084] There are a few points to note:

[0085] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0086] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0087] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0088] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, comprising a middle area and an edge area located outside the middle area, wherein the middle area comprises a plurality of panel units distributed in an array; characterized in that: The display substrate comprises: substrate substrate; A panel circuit, the panel circuit is located on the base substrate, and the panel circuit includes at least one of a touch circuit and a display circuit; and The panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the substrate are both located in the middle area, so that a distance is maintained between the panel circuit and the test circuit and the edge of the substrate.

2. The display substrate according to claim 1, characterized in that: The test circuit includes multiple first test lines and multiple second test lines, which are cross-connected to each other to form a mesh circuit structure. The first test lines are electrically connected to the panel circuit for applying electrical test signals to the panel circuit.

3. The display substrate according to claim 2, characterized in that: The multiple first test lines include a first edge test line and a second edge test line that are arranged closest to the edge area; the multiple second test lines include a third edge test line and a fourth edge test line that are arranged closest to the edge area; wherein, each of the first test lines has its two opposite ends along its own extension direction respectively connected to the third edge test line and the fourth edge test line, and each of the second test lines has its two opposite ends along its own extension direction respectively connected to the first edge test line and the second edge test line.

4. The display substrate according to claim 2, characterized in that: The first test line and the second test line cross each other to define a plurality of sub-areas, and each sub-area includes at least two of the panel units.

5. The display substrate according to claim 1, characterized in that: The display substrate further comprises: The peripheral circuit is arranged in the edge area around the middle area, and any one of the panel circuit and the test circuit is separated from the peripheral circuit to be disconnected from each other, and the routing of the peripheral circuit is led out to the edge of the substrate.

6. The display substrate according to claim 5, characterized in that: The peripheral circuit includes: a closed loop, the closed loop being disposed around the middle area; and At least one lead is connected to the closed loop and extends from the closed loop to the edge of the substrate.

7. The display substrate according to claim 6, characterized in that: The peripheral circuit also includes: multiple electrostatic release points, a gap is maintained between the electrostatic release points and the closed loop, the gap is configured to be broken down by static electricity, the multiple electrostatic release points are distributed in sequence along the routing direction of the closed loop, and the orthographic projection on the substrate is located between the orthographic projection of the closed loop on the substrate and the middle area.

8. The display substrate according to claim 7, characterized in that: The display substrate further includes an alignment mark pattern distributed in the edge region; the orthographic projection of the electrostatic discharge point on the base substrate and the orthographic projection of the alignment mark pattern on the base substrate are separated from each other to be disconnected from each other.

9. The display substrate according to claim 6, characterized in that: There are a plurality of leads, and the plurality of leads are sequentially spaced and distributed along the routing direction of the closed loop, and the orthographic projections of the plurality of leads on the base substrate are located at the periphery of the closed loop.

10. The display substrate according to claim 9, characterized in that: The test circuit includes multiple first test lines and multiple second test lines, and the multiple first test lines and the multiple second test lines are cross-connected to each other; the multiple leads include multiple first leads and / or multiple second leads; wherein, the first leads are parallel to and staggered in the extension direction of the first test lines, and the second leads are parallel to and staggered in the extension direction of the second test lines.

11. The display substrate according to claim 5, characterized in that: At least one of the test circuit and the panel circuit includes a metal routing pattern, and the metal routing pattern is provided in the same layer and with the same material as the peripheral circuit.

12. A display motherboard, characterized in that: The display device comprises a plurality of substrate units, wherein a cutting line area is formed between adjacent substrate units, and the substrate units are configured to form a display substrate as claimed in any one of claims 1 to 11 after being cut along the cutting line area.

13. A method for manufacturing a display substrate, wherein the display substrate comprises a middle area and an edge area located outside the middle area, wherein the middle area comprises a plurality of panel units distributed in an array; characterized in that: The method comprises the following steps: Providing a substrate; forming a pattern of a test circuit on the substrate; A pattern of a panel circuit is formed on the base substrate, wherein the panel circuit includes at least one of a touch circuit and a display circuit, the panel circuit is electrically connected to the test circuit, and the orthographic projections of the panel circuit and the test circuit on the base substrate are both located in the middle area, so that a spacing is maintained between the panel circuit and the test circuit and the edge of the base substrate.

14. The method according to claim 13, characterized in that The method further comprises: A pattern of peripheral circuits is formed on the base substrate, wherein the peripheral circuits are arranged in the edge area around the middle area, and any one of the panel circuits and the test circuits is separated from the peripheral circuits to be disconnected from each other.

15. The method according to claim 14, characterized in that At least one of the test circuit and the panel circuit includes a metal wiring pattern, and the pattern of the peripheral circuit and the metal wiring pattern are formed by a same patterning process.

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