Fault detection system and vehicle

Abstract

The present application provides a fault detection system and a vehicle. The fault detection system includes a detection circuit, a logic gate circuit, and a first control circuit. The detection circuit includes multiple detection branches, each of which outputs a corresponding first detection signal based on the connection status of a low-voltage detection connector. The logic gate circuit receives the first detection signals from the multiple detection branches and generates a second detection signal based on the multiple first detection signals. The first control circuit determines the on / off state of a high-voltage interlock circuit based on the second detection signal. When the first control circuit determines that the on / off state of the high-voltage interlock circuit is disconnected based on the second detection signal, the first control circuit further determines the connection state of multiple low-voltage detection connectors based on the multiple first detection signals. The system can determine the on / off state of the high-voltage interlock circuit based on the second detection signal and can also accurately determine the fault location based on the first detection signal, thereby improving detection and troubleshooting efficiency and achieving high detection reliability.

Description

Technical Field

[0001] The present application relates to the technical field of high-voltage interlock detection, and more particularly, to a fault detection system and a vehicle. Background Art

[0002] With the development of new energy vehicles, electrification has gradually become a trend. Electric vehicles are usually equipped with high-voltage electrical systems. The high-voltage electrical system is used to power high-power electrical equipment (such as motors) in the vehicle. In order to detect the working status of the high-voltage electrical system in real time, a high-voltage interlock (HVIL) system is usually provided in the vehicle. The high-voltage interlock system is provided with multiple high-voltage connectors and corresponding low-voltage detection connectors. Each high-voltage connector usually has an interlocking contact, and these contacts are connected to form a complete high-voltage interlocking circuit through wires. The high-voltage interlock system can cut off the high-voltage power supply in time when the high-voltage electrical system is abnormal, thereby preventing electric shock accidents and fire risks.

[0003] High-voltage interlock systems in related technologies are typically equipped with a high-voltage interlock detection circuit and a control system. Once the high-voltage interlock detection circuit detects a disconnection in the high-voltage interlock circuit, it immediately sends a signal to the control system, causing the control system to cut off the high-voltage output of all loads to ensure safety. However, the high-voltage interlock detection circuit in related technologies can only detect the on / off status of the high-voltage interlock circuit and cannot accurately detect the specific location of the disconnection in the high-voltage interlock circuit, resulting in low efficiency in troubleshooting the high-voltage interlock system. Summary of the Invention

[0004] The present application provides a fault detection system and vehicle, which aim to solve the problem that the high-voltage interlock detection circuit cannot accurately detect the specific location where the high-voltage interlock circuit is disconnected, resulting in low efficiency in troubleshooting high-voltage interlock system faults.

[0005] In a first aspect, a fault detection system is provided, which is applied to a high-voltage interlocking circuit having multiple low-voltage detection connectors, the fault detection system including a detection circuit, a logic gate circuit and a first control circuit; the detection circuit includes multiple detection branches, the multiple detection branches are respectively connected to the multiple low-voltage detection connectors in a one-to-one correspondence, and the detection branches are used to output corresponding first detection signals based on the connection status of the low-voltage detection connectors; the logic gate circuit is connected to the multiple detection branches, the logic gate circuit receives the first detection signals from the multiple detection branches, and generates a second detection signal based on the multiple first detection signals; the first control circuit is connected to the logic gate circuit and the multiple detection branches, the first control circuit is used to receive the second detection signal and the multiple first detection signals, and the first control circuit is used to determine the on-off state of the high-voltage interlocking circuit based on the second detection signal; when the first control circuit determines that the on-off state of the high-voltage interlocking circuit is disconnected based on the second detection signal, the first control circuit is also used to determine the connection state of the multiple low-voltage detection connectors based on the multiple first detection signals.

[0006] In the above technical solution, the detection branch provided by the present application can convert the connection state of the low-voltage detection connector into a high-low level detection signal that can be identified by the logic gate circuit and the first control circuit, that is, the detection branch can convert the connection state of the low-voltage detection connector in real time, and send the converted first detection signal to the logic gate circuit and the first control circuit, and the logic gate circuit can generate a second detection signal based on these first detection signals, so that the first control circuit can accurately know the on-off state of the high-voltage interlock circuit based on the second detection signal. When the first control circuit determines that the high-voltage interlock circuit is disconnected based on the second detection signal, the specific fault location (i.e., the low-voltage detection connector with abnormal connection) is determined based on multiple first detection signals to achieve accurate detection of the connection state of the low-voltage detection connector and the on-off state of the high-voltage interlock circuit, so that the staff can determine the fault of the low-voltage detection connector and quickly repair or replace the low-voltage detection connector, thereby improving the detection and troubleshooting efficiency, effectively solving the problem of low efficiency in troubleshooting the high-voltage interlock system, and improving a certain degree of safety. Secondly, when the first control circuit determines that the high-voltage interlock circuit is connected based on the second detection signal, the first control circuit can determine that the low-voltage detection connectors are all properly connected. There is no need to determine the connection status of each low-voltage detection connector based on multiple first detection signals. This simplifies the calculation and processing steps of the first control circuit and saves resources of the first control circuit.

[0007] In combination with the first aspect, in some possible implementations, each detection branch includes a first resistor, one end of the first resistor is connected to the first end of the low-voltage detection connector, the logic gate circuit, and the first control circuit, and the other end of the first resistor is connected to the second end of the low-voltage detection connector and the ground end.

[0008] In the above technical solution, the logic gate circuit and the first control circuit can easily determine the connection status of the low-voltage detection connector connected thereto by detecting the voltage difference across the first resistor and the voltage of the corresponding node. The first resistor can also autonomously convert the connection status of the low-voltage detection connector. That is, the connection status of the low-voltage detection connector can be converted into high and low level signals recognizable by the logic gate circuit and the first control circuit through the first resistor, so that the fault detection system can realize autonomous detection based on the first resistor without relying on the control of the first control circuit or the control of other systems, and has high detection flexibility.

[0009] In combination with the first aspect and the above implementation, in some possible implementations, the logic gate circuit includes an OR gate; the input end of the OR gate is respectively connected to one end of multiple first resistors, and the output end of the OR gate is connected to the first control circuit.

[0010] In the above technical solution, the OR gate can simplify multiple first detection signals into one second detection signal. The first control circuit can determine the on-off state of the high-voltage interlocking circuit based on the second detection signal, without setting up an additional multiplexer or other logical combination, which simplifies the system. The OR gate can quickly change the output state (i.e., the second detection signal) when the input signal (i.e., multiple first detection signals) changes, and the response speed is fast, so that the first control circuit can accurately know the on-off state of the current high-voltage interlocking circuit based on the second detection signal. Secondly, the static power consumption of the OR gate is low, and it only consumes a small amount of energy when the input first detection signal changes, which helps to reduce the power consumption of the entire fault detection system.

[0011] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the fault detection system also includes a comparison circuit; the comparison circuit is connected to one end of the first resistor, the logic gate circuit and the first control circuit, and the comparison circuit is further used to access multiple comparison thresholds. The comparison circuit is used to generate multiple electrical signals based on the first detection signal and the multiple comparison thresholds, and output the multiple electrical signals to the logic gate circuit; wherein the logic gate circuit is further used to generate a third detection signal based on the multiple electrical signals and output the third detection signal to the first control circuit; wherein the first control circuit is further used to determine the connection status of the low-voltage detection connector based on the third detection signal, and when the first control circuit determines that the connection status of the low-voltage detection connector is abnormal based on the third detection signal, the first control circuit is further used to determine the fault status of the low-voltage detection connector based on the multiple electrical signals.

[0012] In the above technical solution, after the first control circuit determines the on / off state of the high-voltage interlock circuit based on the second detection signal, the first control circuit can simultaneously determine the low-voltage detection connector whose connection state at this time is abnormal connection based on the first detection signal and the third detection signal, and then determine the fault state of the faulty low-voltage detection connector at this time based on multiple electrical signals output by the comparison circuit, so that the staff can determine the specific fault state of the low-voltage detection connector and quickly repair or replace the low-voltage detection connector based on the fault state, further improving the detection and troubleshooting efficiency of the fault detection system, effectively solving the problem of low efficiency in troubleshooting high-voltage interlock system faults, and improving a certain degree of safety.

[0013] In combination with the first aspect and the above-mentioned implementation manner, in some possible implementation manners, the multiple comparison thresholds include a first comparison threshold, a second comparison threshold, and a third comparison threshold, the multiple electrical signals include a first electrical signal, a second electrical signal, and a third electrical signal; the comparison circuit includes a first comparator, a second comparator, and a third comparator; the non-inverting input terminal of the first comparator is connected to the first comparison threshold, the inverting input terminal of the first comparator is connected to one end of the first resistor, the output terminal of the first comparator is connected to the first control circuit and the logic gate circuit, the first comparator is used to generate a first electrical signal based on the first comparison threshold and the first detection signal and output it to the logic gate circuit; the non-inverting input terminal of the second comparator is connected to the first comparison threshold, the inverting input terminal of the first comparator is connected to the first resistor, the output terminal of the first comparator is connected to the first control circuit and the logic gate circuit, and the first comparator is used to generate a first electrical signal based on the first comparison threshold and the first detection signal and output it to the logic gate circuit; the non-inverting input terminal of the second comparator is connected to the first comparison threshold. The second comparison threshold, the inverting input terminal of the second comparator is connected to one end of the first resistor, the output terminal of the second comparator is connected to the first control circuit and the logic gate circuit, and the second comparator is used to generate a second electrical signal based on the second comparison threshold and the first detection signal and output it to the logic gate circuit; the non-inverting input terminal of the third comparator is connected to the third comparison threshold, the inverting input terminal of the third comparator is connected to one end of the first resistor, the output terminal of the third comparator is connected to the first control circuit and the logic gate circuit, and the third comparator is used to generate a third electrical signal based on the third comparison threshold and the first detection signal and output it to the logic gate circuit; wherein, the second comparison threshold is greater than the first comparison threshold and less than the third comparison threshold.

[0014] In the above technical solution, by using the first comparator, the second comparator, and the third comparator, combined with multiple different comparison thresholds, it is possible not only to determine whether a fault has occurred in the low-voltage detection connector itself, but also to determine whether the low-voltage detection connector is short-circuited to the power supply terminal or short-circuited to ground, thereby enabling the fault detection system to accurately detect the fault state of the low-voltage detection connector.

[0015] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the fault detection system also includes a threshold generation circuit; the threshold generation circuit is connected to the non-inverting input terminal of the first comparator, the non-inverting input terminal of the second comparator, and the non-inverting input terminal of the third comparator, and the threshold generation circuit is used to generate a first comparison threshold, a second comparison threshold, and a third comparison threshold based on the power supply voltage.

[0016] In the above technical solution, different first comparison thresholds, second comparison thresholds, and third comparison thresholds can be set by the threshold generation circuit to achieve accurate detection of different fault states of the low-voltage detection connector.

[0017] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the threshold generation circuit includes a first voltage divider module, a second voltage divider module and a third voltage divider module; the first end of the first voltage divider module is connected to the power supply voltage, the second end of the first voltage divider module is connected to the non-inverting input terminal of the first comparator, and the third end of the first voltage divider module is connected to the ground terminal. The first voltage divider module is used to generate a first comparison threshold based on the power supply voltage and output it to the first comparator; the first end of the second voltage divider module is connected to the power supply voltage, the second end of the second voltage divider module is connected to the non-inverting input terminal of the second comparator, and the third end of the second voltage divider module is connected to the ground terminal. The second voltage divider module is used to generate a second comparison threshold based on the power supply voltage and output it to the second comparator; the first end of the third voltage divider module is connected to the power supply voltage, the second end of the third voltage divider module is connected to the non-inverting input terminal of the third comparator, and the third end of the third voltage divider module is connected to the ground terminal. The third voltage divider module is used to generate a third comparison threshold based on the power supply voltage and output it to the third comparator.

[0018] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the logic gate circuit includes an inverter and an AND gate; the input end of the inverter is connected to the output end of the first comparator; the input end of the AND gate is respectively connected to the output end of the inverter, the output end of the second comparator, and the output end of the third comparator, and the output end of the AND gate is connected to the first control circuit.

[0019] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the fault detection system also includes a second control circuit and multiple first switch circuits; the second control circuit is connected to the first control circuit; the controlled ends of the multiple first switch circuits are connected to the second control circuit, the first ends of the multiple first switch circuits are connected to the power supply voltage, and the second ends of the multiple first switch circuits are respectively connected one-to-one with the first ends of multiple detection branches and multiple low-voltage detection connectors; wherein the second control circuit is used to control the on and off of the first switch circuit to correspond to the working state of the control detection branch.

[0020] In the above technical solution, each low-voltage detection connector and its corresponding detection branch are controlled by an independent first switch circuit, which has high control accuracy. At the same time, the first switch circuit corresponding to any low-voltage detection connector can be turned on according to actual troubleshooting needs, so that the corresponding detection branch is in working mode, thereby realizing the conversion of the connection state of the low-voltage detection connector and independent troubleshooting, and the detection flexibility is high. In addition, the multiple first switch circuits corresponding to the multiple low-voltage detection connectors and the multiple detection branches are independent of each other, that is, the detection branches corresponding to the various detection branches do not affect each other, thereby ensuring the detection reliability of each detection branch performing independent detection. Secondly, the second control circuit can also achieve precise control of the overall working state of the fault detection system by simultaneously controlling the on-off state of the multiple first switch circuits. For example, the second control circuit can simultaneously control the multiple first switch circuits to be turned off to reduce the overall energy consumption of the fault detection system, thereby saving a certain amount of energy.

[0021] In a second aspect, an embodiment of the present application provides a vehicle comprising a high-voltage interlocking circuit and a fault detection system as described in any optional manner of the first aspect, wherein the high-voltage interlocking circuit is provided with a plurality of low-voltage detection connectors, and the fault detection system is connected to the plurality of low-voltage detection connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of a module structure of a vehicle provided in an embodiment of the present application;

[0023] Figure 2 This is a schematic diagram of the module structure of a fault detection system provided in an embodiment of the present application;

[0024] Figure 3 This is a schematic diagram of the circuit structure of a fault detection system provided in an embodiment of the present application;

[0025] Figure 4 This is a schematic diagram of the circuit structure of another fault detection system provided in an embodiment of the present application;

[0026] Figure 5 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0027] Figure 6 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0028] Figure 7 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0029] Figure 8 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0030] Figure 9 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0031] Figure 10 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0032] Figure 11 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0033] Figure 12 This is a circuit diagram of another fault detection system provided in an embodiment of the present application;

[0034] Figure 13 This is a circuit structure diagram of another fault detection system provided in an embodiment of the present application.

[0035] Among them, the reference numerals in the figures are:

[0036] 1. Fault detection system; 11. Detection circuit; 111. Detection branch; 12. Logic gate circuit; 13. First control circuit; 14. Second control circuit; 15. First switch circuit; 16. Second switch circuit; 17. Comparison circuit; 18. Threshold generation circuit; 181. First voltage divider module; 182. Second voltage divider module; 183. Third voltage divider module; 2. Low-voltage detection connector;

[0037] DET1, first detection signal; DET2, second detection signal; DET3, third detection signal; OUT1, first electrical signal; OUT2, second electrical signal; OUT3, third electrical signal; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; a, first node; b, second node; c, third node; d, fourth node; e, fifth node; f, sixth node; OR, OR gate; VCC, power supply voltage; Q1, first switch tube; Q1, second switch tube; COMP1, first comparator; COMP2, second comparator; COMP3, third comparator; Vth1, first comparison threshold; Vth2, second comparison threshold; Vth3, third comparison threshold; GND, ground terminal; INV, inverter; AND, AND gate. DETAILED DESCRIPTION

[0038] The following will clearly and thoroughly describe the technical solutions in this application in conjunction with the accompanying drawings. In the description of the embodiments of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more than two.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0040] Currently, new energy vehicles are widely used in various scenarios, replacing internal combustion engine vehicles. Compared with internal combustion engine vehicles, new energy vehicles produce less noise during driving and do not directly emit exhaust gas, making them more environmentally friendly. At the same time, new energy vehicles are intelligent, have higher energy efficiency conversion rates, and have lower maintenance costs. Therefore, more and more people are starting to use new energy vehicles as a means of transportation. New energy vehicles are usually equipped with a power battery to provide a power source for the vehicle and drive motor. For example, the power battery outputs direct current to the motor. The motor controller (MCU) converts the DC power provided by the power battery into three-phase alternating current to drive the motor according to the target torque and speed sent by the vehicle control unit (VCU). This controls the motor to complete functions such as starting, acceleration and deceleration, braking, and energy recovery, thereby ensuring the normal operation of the vehicle.

[0041] New energy vehicles are usually equipped with two electrical systems, high voltage and low voltage. Among them, the high voltage electrical system is equipped with a high voltage battery (such as a power battery). The high voltage battery is used to power high-power electrical equipment (such as a motor) in the vehicle to drive the vehicle to maintain normal driving. At the same time, the power battery will also charge the low voltage battery in the vehicle under the control of the vehicle controller. The charging voltage is usually about several hundred volts. In order to ensure the safety of the driver, passengers and vehicles, a high voltage interlocking system is usually provided in the vehicle. The high voltage interlocking system includes a high voltage connector and a control system. The high voltage connector is used to connect various components in the high voltage electrical system (such as high voltage components such as high voltage batteries, motors, inverters, etc.) to ensure the safe transmission of high voltage current. Each high voltage connector usually has an interlocking contact. These contacts are connected in series through wires to form a complete high voltage interlocking circuit. The high voltage interlocking circuit and the control system can cut off the high voltage power supply in time when the high voltage electrical system is abnormal, thereby preventing electric shock accidents and fire risks.

[0042] High-voltage connectors may become loose or fall off, causing an abnormality in the high-voltage interlock circuit. To monitor the connection status of the high-voltage interlock circuit in real time, high-voltage interlock systems in related technologies typically include a high-voltage interlock detection circuit. This circuit consists of a low-voltage detection connector and a low-voltage detection port. The low-voltage detection connector connects the low-voltage detection port to the high-voltage interlock circuit to ensure reliable signal transmission and is typically located between various nodes in the high-voltage interlock circuit. The low-voltage detection port is used to send and receive low-voltage signals to detect the status of the high-voltage interlock circuit. The detection principle is generally as follows: before the vehicle is started, the control system sends a low-voltage excitation signal through the low-voltage detection port. This excitation signal is transmitted through the low-voltage detection connector along the interlock contacts of all high-voltage connectors in the high-voltage interlock circuit. If all high-voltage connectors are properly connected, the excitation signal is successfully transmitted and returned to the low-voltage detection port through the low-voltage detection connector. If the low-voltage detection port receives a feedback signal that matches the transmitted excitation signal, indicating that all high-voltage connectors are properly connected and the high-voltage interlock circuit is functioning properly, the control system activates the high-voltage power supply and the high-voltage electrical system begins operation. If a high-voltage interlock circuit fault is detected, the control system will take the same action, cutting off the high-voltage output to all loads.

[0043] However, the high-voltage interlock detection circuit in the related art can only know the on-off status of the high-voltage interlock circuit, and cannot accurately detect the specific location where the high-voltage interlock circuit is disconnected, resulting in low efficiency in troubleshooting the high-voltage interlock system.

[0044] To this end, an embodiment of the present application provides a fault detection system and a vehicle, in which the first control circuit can determine the on / off state of the high-voltage interlocking circuit based on the second detection signal, and can also accurately determine the fault location based on the first detection signal, thereby improving the detection and troubleshooting efficiency and providing high detection reliability.

[0045] The following is an exemplary introduction to the fault detection system and vehicle provided in the embodiments of the present application with reference to the accompanying drawings.

[0046] The embodiment of the present application provides a vehicle, and the vehicle provided by the present application includes a high-voltage electrical system and a low-voltage electrical system, wherein a high-voltage battery (such as a power battery) is provided in the high-voltage electrical system, and the high-voltage battery is used to power high-power electrical equipment in the vehicle (such as motors, inverters and other high-voltage components) to drive the vehicle to maintain normal driving. At the same time, the power battery will also charge the low-voltage battery in the low-voltage electrical system under the control of the vehicle controller. The low-voltage electrical system is provided with a low-voltage battery (such as a 12V battery) and a direct current to direct current converter (DCDC). The DC converter can convert the high voltage electricity of the high-voltage battery into low voltage electricity to meet the transmission / control of signals in the vehicle, which will not be described in detail.

[0047] Among them, the voltage in the high-voltage electrical system is usually above hundreds of volts. When repairing or inspecting the vehicle, personnel may accidentally touch the high-voltage components that are not completely disconnected, resulting in electric shock accidents. Secondly, a short circuit or poor connection of the high-voltage electrical system may cause sparks or overheating, which in turn may cause a fire, posing a great safety hazard. To this end, the vehicle provided by the present application is provided with a high-voltage interlock system, which includes a high-voltage connector. The high-voltage connector is used to connect various components in the high-voltage electrical system to ensure the safe transmission of high-voltage current. Each high-voltage connector usually has an interlocking contact. These contacts are connected in series through wires to form a complete high-voltage interlock circuit. The high-voltage interlock circuit can ensure that the high-voltage power supply will not be activated when the high-voltage connector is not fully connected or disconnected, thereby preventing personnel from touching the live high-voltage components. At the same time, when the high-voltage electrical system is short-circuited or poorly connected, the high-voltage interlock circuit can quickly cut off the high-voltage power supply to prevent fires caused by electrical faults.

[0048] In order to realize the fault detection of the high voltage interlock circuit, in one example, Figure 1 As shown, the vehicle provided by the present application also includes a fault detection system 1 and a plurality of low-voltage detection connectors 2. The low-voltage detection connector 2 is arranged in a high-voltage interlocking circuit (not shown in the figure) and corresponds to a high-voltage connector (not shown in the figure). The fault detection system 1 in the present application can realize the fault detection of the high-voltage interlocking circuit and the precise positioning of the fault by detecting the connection status of the low-voltage detection connector. It is worth noting that the number of low-voltage detection connectors can be equal to or less than the number of high-voltage connectors. When the number of low-voltage detection connectors is equal to the number of high-voltage connectors, the high-voltage connectors and the low-voltage detection connectors are one-to-one corresponding to ensure that the state of each high-voltage connector can be independently detected, thereby improving the safety of the system; when the number of low-voltage detection connectors is less than the number of high-voltage connectors, multiple high-voltage connectors can be connected to the same low-voltage detection connector to save production costs. The specific setting can be made according to actual needs. In this regard, the present application does not make specific restrictions.

[0049] In order to enable the fault detection system 1 to accurately detect the connection status of multiple low-voltage detection connectors 2, in one example, Figure 2 As shown, the fault detection system 1 includes a detection circuit 11, a logic gate circuit 12, and a first control circuit 13. The detection circuit 11 includes multiple detection branches 111, each of which is connected to a plurality of low-voltage detection connectors 2 in a one-to-one correspondence. The logic gate circuit 12 is connected to the multiple detection branches 111, and the first control circuit 13 is connected to the logic gate circuit 12 and the multiple detection branches 111. It is worth noting that the figure only takes three low-voltage detection connectors 2 and three detection branches 111 as an example. The specific number of low-voltage detection connectors 2 and detection branches 111 can be set according to actual needs, and this application does not impose any specific limitation on this.

[0050] In this example, each detection branch 111 can output a corresponding first detection signal DET1 based on the connection status of the connected low-voltage detection connector 2, and output the first detection signal DET1 to the logic gate circuit 12. The logic gate circuit 12 receives the first detection signals DET1 from the multiple detection branches 111, and generates a second detection signal DET2 based on the multiple first detection signals DET1, and outputs the second detection signal DET2 to the first control circuit 13. The first control circuit 13 receives the second detection signal DET2 and the multiple first detection signals DET1, and can determine the on-off state of the high-voltage interlock circuit based on the second detection signal DET2. The on-off state of the high-voltage interlock circuit includes the high-voltage interlock circuit being disconnected and the high-voltage interlock circuit being connected. When the high-voltage interlock circuit is disconnected, the high-voltage interlock circuit is abnormal, that is, the low-voltage detection connector 2 in the high-voltage interlock circuit may be faulty; when the high-voltage interlock circuit is connected, the high-voltage interlock circuit is normal, that is, the low-voltage detection connector 2 in the high-voltage interlock circuit is normal.

[0051] To this end, when the first control circuit 13 determines that the high-voltage interlock circuit is disconnected based on the second detection signal DET2, the first control circuit 13 is further configured to determine the connection status of the plurality of low-voltage detection connectors 2 based on the plurality of first detection signals DET1. The connection status includes normal connection and abnormal connection. When the plurality of low-voltage detection connectors 2 are all normally connected, the high-voltage interlock circuit is connected, i.e., the high-voltage interlock circuit is normal. An abnormal connection refers to a problem such as a loosening or detachment of the low-voltage detection connector 2, in which case the low-voltage detection connector 2 is abnormally connected. It is understood that if any one of the plurality of low-voltage detection connectors 2 is abnormally connected, the high-voltage interlock circuit is disconnected, i.e., the high-voltage interlock circuit is abnormal.

[0052] Exemplarily, when the connection status of all low-voltage detection connectors 2 is normally connected, each detection branch 111 can convert the normal connection status into a corresponding first detection signal DET1. At this time, the first detection signal DET1 can be a low-level detection signal indicating that the connection status of the low-voltage detection connector 2 is normally connected. Multiple detection branches 111 output the corresponding low-level detection signals to the logic gate circuit 12. The logic gate circuit 12 can generate a corresponding second detection signal DET2 based on multiple low-level detection signals. At this time, the first detection signals DET1 connected to the logic gate circuit 12 are all low-level detection signals, and the corresponding output second detection signal DET2 is a low-level detection signal. The logic gate circuit 12 then sends the low-level detection signal to the first control circuit 13. When the second detection signal DET2 received by the first control circuit 13 is a low-level detection signal, the first control circuit 13 can determine that the high-voltage interlocking circuit is connected at this time, that is, the high-voltage interlocking circuit is normal at this time. It can be understood that the high-voltage interlock circuit can only be connected when all the low-voltage detection connectors 2 in the high-voltage interlock circuit are normally connected. That is, when the second detection signal DET2 received by the first control circuit 13 is a low-level detection signal, the first control circuit 13 can determine that the high-voltage interlock circuit is normal at this time and the low-voltage detection connectors 2 in the high-voltage interlock circuit are also normally connected. The first control circuit 13 no longer needs to determine the connection status of each low-voltage detection connector 2 based on multiple first detection signals DET1, thereby simplifying the calculation and processing steps of the first control circuit 13.

[0053] For example, when one or more of the multiple low-voltage detection connectors 2 have an abnormal connection state, while the remaining low-voltage detection connectors 2 have a normal connection state, the detection branch 111 corresponding to the one or more abnormal low-voltage detection connectors 2 can convert the abnormal connection state into a corresponding first detection signal DET1. In this case, the first detection signal DET1 can be a high-level detection signal indicating that the low-voltage detection connector 2 has an abnormal connection state. The detection branch 111 outputs the corresponding high-level detection signal to the logic gate circuit 12. The detection branches 111 corresponding to the remaining low-voltage detection connectors 2 can convert the normal connection state into a corresponding first detection signal DET1. In this case, the first detection signal DET1 can be a low-level detection signal indicating that the low-voltage detection connector 2 has a normal connection state. The remaining detection branches 111 output the corresponding low-level detection signal to the logic gate circuit 12. At this time, the multiple first detection signals DET1 connected to the logic gate circuit 12 include a low-level detection signal and a high-level detection signal. The logic gate circuit 12 will output a second detection signal DET2 based on the low-level detection signal and the high-level detection signal. At this time, the second detection signal DET2 is a high-level detection signal, and the logic gate circuit 12 then sends the high-level detection signal to the first control circuit 13. When the second detection signal DET2 received by the first control circuit 13 is a high-level detection signal, the first control circuit 13 can determine that the high-voltage interlocking circuit is disconnected at this time, that is, the high-voltage interlocking circuit is abnormal at this time.

[0054] When the first control circuit 13 determines that the high-voltage interlock circuit is abnormal based on the second detection signal DET2, the first control circuit 13 needs to determine the specific location of the fault in the high-voltage interlock circuit. The first control circuit 13 will determine the connection status of each low-voltage detection connector 2 based on the multiple first detection signals DET1 received. It can be understood that when the first detection signal DET1 received by the first control circuit 13 is a low-level detection signal, the low-voltage detection connector 2 corresponding to the low-level detection signal is normally connected; when the first detection signal DET1 received by the first control circuit 13 is a high-level detection signal, the low-voltage detection connector 2 corresponding to the high-level detection signal is abnormally connected. At this time, the first control circuit 13 can determine the specific fault location in the high-voltage interlock circuit based on the high-level detection signal. After detecting that a fault has occurred in the high-voltage interlock circuit and determining the fault location (i.e., the low-voltage detection connector 2 with an abnormal connection), the staff can repair or replace the low-voltage detection connector 2 based on the fault location to effectively troubleshoot the high-voltage interlock system fault.

[0055] In this way, the detection branch 111 provided in the present application can convert the connection status of the low-voltage detection connector 2 into high and low-level detection signals that can be recognized by the logic gate circuit 12 and the first control circuit 13, that is, the detection branch 111 can convert the connection status of the low-voltage detection connector 2 in real time, and send the converted first detection signal DET1 to the logic gate circuit 12 and the first control circuit 13. The logic gate circuit 12 can generate the second detection signal DET2 based on these first detection signals DET1, so that the first control circuit 13 can accurately know the on-off state of the high-voltage interlocking circuit based on the second detection signal DET2. When the first control circuit 13 determines that the high-voltage interlock circuit is disconnected based on the second detection signal DET2, it then determines the specific fault location (i.e., the abnormally connected low-voltage detection connector 2) based on multiple first detection signals DET1 to achieve accurate detection of the connection status of the low-voltage detection connector 2 and the on-off status of the high-voltage interlock circuit, so that the staff can determine that the low-voltage detection connector 2 is faulty and quickly repair or replace the low-voltage detection connector 2, thereby improving the detection and troubleshooting efficiency, effectively solving the problem of low efficiency in troubleshooting high-voltage interlock system faults, and improving a certain degree of safety. Secondly, when the first control circuit 13 determines that the high-voltage interlock circuit is connected based on the second detection signal DET2, the first control circuit 13 can know that the low-voltage detection connectors 2 are all normally connected at this time, and there is no need to determine the connection status of each low-voltage detection connector 2 based on multiple first detection signals DET1, which simplifies the calculation and processing steps of the first control circuit 13 and saves resources of the first control circuit 13.

[0056] In order to enable the detection branch 111 to output the corresponding first detection signal DET1 based on the connection state of the low voltage detection connector 2, in one example, Figure 3 As shown, each detection branch 111 includes a first resistor R1, one end of the first resistor R1 is connected to the first end of the low voltage detection connector 2 and the logic gate circuit 12, and the other end of the first resistor R1 is connected to the second end of the low voltage detection connector 2 and the ground terminal GND.

[0057] In this example, when the connection state of the low-voltage detection connector 2 is normally connected, the voltage difference across the first resistor R1 is 0V (volts), and the first detection signal DET1 output by the first resistor R1 is a low-level detection signal. When the connection state of the low-voltage detection connector 2 is abnormal, there is a voltage difference across the first resistor R1, and the voltage difference is greater than 0V, and the detection signal DET1 output by the first resistor R1 is a high-level detection signal.

[0058] For example, Figure 3As shown, a fault detection system 1 includes three detection branches 111, namely, three first resistors R1. One end of each of the three first resistors R1 is connected to the first end of the corresponding low-voltage detection connector 2 at a first node a, a second node b, and a third node c, respectively. When all low-voltage detection connectors 2 are in a normal connection state, the voltages at the first node a, the second node b, and the third node c are all zero. In this case, the first detection signals DET1 output by the three first resistors R1 to the logic gate circuit 12 and the first control circuit 13 are low-level detection signals. When the connection state of the first low-voltage detection connector 2 is abnormal and the connection states of the other two low-voltage detection connectors 2 are normal, the voltage at the first node a is non-zero. In this case, the first detection signal DET1 output by the corresponding first resistor R1 to the logic gate circuit 12 and the first control circuit 13 is a high-level detection signal. The voltages at the second node b and the third node c are both zero. In this case, the first detection signal DET1 output by the corresponding first resistor R1 to the logic gate circuit 12 and the first control circuit 13 is a low-level detection signal.

[0059] In this way, the logic gate circuit 12 and the first control circuit 13 can easily determine the connection status of the low-voltage detection connector 2 connected thereto by detecting the voltage difference across the first resistor R1 and the voltage of the corresponding node, and the first resistor R1 can autonomously convert the connection status of the low-voltage detection connector 2. That is, the connection status of the low-voltage detection connector 2 can be converted into high and low level signals that can be recognized by the logic gate circuit 12 and the first control circuit 13 through the first resistor R1, so that the fault detection system 1 can realize autonomous detection based on the first resistor R1 without relying on the control of the first control circuit or the control of other systems, and has high detection flexibility.

[0060] Optionally, the first resistor R1 provided in the present application may be connected to the low voltage detection connector 2 via the low voltage detection port.

[0061] In order to enable the logic gate circuit 12 to generate the corresponding second detection signal DET2 based on different first detection signals DET1, in one example, as shown in FIG. Figure 4 As shown, the logic gate circuit 12 includes an OR gate OR, the input end of the OR gate OR is respectively connected to one end of the plurality of first resistors R1 , and the output end of the OR gate OR is connected to the first control circuit 13 .

[0062] The logic of the OR gate OR is "0" if all are "0" and "1" if there is a "1". It can be understood that when the multiple first detection signals DET1 connected to the OR gate OR are all low-level detection signals, the second detection signal DET2 output by the OR gate OR will be a low-level detection signal. At this time, the first control circuit 13 can determine that the high-voltage interlock circuit is connected based on the low-level detection signal, and at the same time, know that the low-voltage detection connectors 2 are all properly connected. When any one of the multiple first detection signals DET1 connected to the OR gate OR is a high-level detection signal, the second detection signal DET2 output by the OR gate OR is a high-level detection signal. The first control circuit 13 can determine that the high-voltage interlock circuit is disconnected based on the high-level detection signal. Then, the multiple first detection signals DET1 connected are processed to determine the connection status of the multiple low-voltage detection connectors 2, thereby realizing the fault location in the high-voltage interlock circuit.

[0063] In this example, the OR gate OR can simplify multiple first detection signals DET1 into one second detection signal DET2. The first control circuit 13 can determine the on-off state of the high-voltage interlocking circuit based on the second detection signal DET2, without setting up an additional multiplexer or other logical combination, thereby simplifying the system. The OR gate OR can quickly change the output state (i.e., the second detection signal DET2) when the input signal (i.e., multiple first detection signals DET1) changes, and the response speed is fast, so that the first control circuit 13 can accurately know the on-off state of the current high-voltage interlocking circuit based on the second detection signal DET2. Secondly, the static power consumption of the OR gate OR is low, and only a small amount of energy is consumed when the input first detection signal DET1 changes, which helps to reduce the power consumption of the entire fault detection system 1.

[0064] The specific implementation scheme of the high-voltage interlock circuit can be classified into voltage source type and current source type according to the circuit excitation source. For example, please refer to Figures 2 to 4 , the high voltage interlock circuit adopts a voltage source type, the detection branch 111 and the low voltage detection connector 2 are connected to the power supply voltage VCC, in order to further reduce the energy consumption of the fault detection system 1, in an example, as Figure 4 As shown, the fault detection system 1 further includes a second control circuit 14 and multiple first switch circuits 15. The second control circuit 14 is connected to the first control circuit 13. The controlled ends of the multiple first switch circuits 15 are connected to the second control circuit 14. The first ends of the multiple first switch circuits 15 are connected to the power supply voltage VCC, and the second ends of the multiple first switch circuits 15 are connected to the multiple detection branches 111 and the first ends of the multiple low-voltage detection connectors 2 in a one-to-one correspondence. The second control circuit 14 can control the operating state of the corresponding detection branch 111 by controlling the on and off of the first switch circuits 15.

[0065] In this example, when the fault detection system 1 needs to be detected as a whole, the second control circuit 14 can simultaneously control multiple first switch circuits 14 to be turned on, so that the power supply voltage VCC is loaded into the loop where the detection branch 111 is located, so that the multiple detection branches 111 can operate normally, that is, the fault detection system 1 can operate normally as a whole. When several detection branches 111 are required to work, that is, only the connection status of several low-voltage detection connectors 2 needs to be checked, since each low-voltage detection connector 2 and the detection branch 111 (i.e., Figure 5 Each of the first resistors R1 shown is provided with a corresponding first switch circuit 15. The second control circuit 14 can control the first switch circuit 15 corresponding to the low-voltage detection connector 2 that needs to be checked to be turned on, while the first switch circuits 15 corresponding to the remaining low-voltage detection connectors 2 remain turned off, thereby enabling detection of the connection status of the corresponding low-voltage detection connector 2. Each low-voltage detection connector 2 and the corresponding detection branch 111 are controlled by an independent first switch circuit 15, resulting in high detection accuracy and flexibility. When the fault detection system 1 is not required to perform detection as a whole, the second control circuit 14 controls multiple first switch circuits 15 to be turned off, so that the power supply voltage VCC is not loaded into the loop where the detection branch 111 is located. At this time, the detection branch 111 and other modules are not operating, thereby saving energy.

[0066] In this way, each low-voltage detection connector 2 and its corresponding detection branch 111 are controlled by an independent first switch circuit 15, resulting in high control accuracy. Furthermore, the first switch circuit 15 corresponding to any low-voltage detection connector 2 can be turned on according to actual troubleshooting needs, placing the corresponding detection branch 111 in working mode. This allows for switching the connection state of the low-voltage detection connector 2 and enabling independent troubleshooting, resulting in high detection flexibility. Furthermore, the multiple first switch circuits 15 corresponding to the multiple low-voltage detection connectors 2 and the multiple detection branches 111 are independent of each other, meaning that the detection branches corresponding to the various detection branches 111 do not affect each other, thereby ensuring the reliability of independent detection of each detection branch 111. Furthermore, by simultaneously controlling the on / off states of the multiple first switch circuits 15, the second control circuit 14 can also achieve precise control of the overall operating state of the fault detection system 1. For example, the second control circuit 14 can simultaneously control the off states of the multiple first switch circuits 15 to reduce the overall energy consumption of the fault detection system 1, thereby saving a certain amount of energy.

[0067] The high-voltage components in this application are arranged at different positions of the vehicle, and the positions of the high-voltage connector and the low-voltage detection connector 2 are also correspondingly arranged at different positions of the vehicle. In order to further shorten the length of the connecting harness, optionally, multiple detection branches 111 are connected to the adjacent first control circuit 13 to shorten the length of the connecting harness between the first control circuit 13 and the detection branch 111, further shorten the length of the connecting harness, simplify the system circuit, and thus further reduce the resistance, capacitance and inductance encountered by the first detection signal DET1 during transmission, further improve the transmission reliability and detection reliability of the first detection signal DET1, and secondly, multiple detection branches 111 are connected to the adjacent first control circuit 13, so that the various connecting harnesses are separated from each other, avoiding interference between the harnesses, and the problem of certain safety hazards, thereby improving a certain degree of safety.

[0068] The first control circuit 13 in this application can reuse the electronic control unit (ECU) corresponding to each high-voltage component in the vehicle. The first control circuit 13 can also reuse the ECU in other modules. This application does not impose specific restrictions on this. Optionally, the second control circuit 14 can be a microcontroller (MCU), and the first control circuit 13 and the second control circuit 14 can communicate using a controller area network (CAN) bus.

[0069] It is worth noting that in this example, the first control circuit 13 can also output the detection results to the second control circuit 14, so that the second control circuit 14 can determine the current on / off status of the high-voltage interlock circuit and the connection status of the low-voltage detection connector 2 based on the detection results. Under normal circumstances, the first control circuit 13 only needs to output the second detection signal DET2 indicating that the high-voltage interlock circuit is connected to the second control circuit 14, and there is no need to output the multiple first detection signals DET1 to the second control circuit 14. Only under abnormal circumstances will the first control circuit 13 report the output status of each detection branch 111 (i.e., the multiple first detection signals DET1) to the second control circuit 14, so that the second control circuit 14 can determine the connection status of the low-voltage detection connector 2 based on the multiple first detection signals DET1, thereby saving resources of the second control circuit 14.

[0070] In one example, if Figure 6As shown, each first switch circuit 15 includes a first switch tube Q1 and a second resistor R2. The first end of the first switch tube Q1 serves as the first end of the first switch circuit 15 and is connected to the power supply voltage VCC. The controlled end of the first switch tube Q1 serves as the controlled end of the first switch circuit 15 and is connected to the second control circuit 14. One end of the second resistor R2 is connected to the second end of the first switch tube Q1. The other end of the second resistor R2 serves as the second end of the first switch circuit 15 and is connected to one end of the first resistor R1 and the first end of the low-voltage detection connector 2.

[0071] In this example, when the fault detection system 1 needs to perform detection, the second control circuit 14 controls the multiple first switch tubes Q1 to be turned on, so that the power supply voltage VCC is loaded into the loop where the detection branch 111 is located through the second resistor R2, so that the fault detection system 1 can operate normally. If a low-voltage detection connector 2 is abnormally connected at this time, the first detection signal DET1 output by the detection branch 111 connected to it to the logic gate circuit 12 is a high-level detection signal divided by the second resistor R2.

[0072] When several detection branches 111 need to be operated, that is, when only the connection status of several low-voltage detection connectors 2 needs to be checked, the second control circuit 14 can control the first switch tubes Q1 corresponding to the low-voltage detection connectors 2 that need to be checked to be turned on, while the first switch tubes Q1 corresponding to the remaining low-voltage detection connectors 2 remain turned off, thereby realizing the detection of the connection status of the corresponding low-voltage detection connectors 2.

[0073] When the fault detection system 1 is not required to perform detection, the second control circuit 14 controls the multiple first switching tubes Q1 to be turned off, so that the power supply voltage VCC is not loaded into the loop where the detection branch 111 is located. At this time, the detection branch 111 and other modules are not operating. In this way, the second control circuit 14 can accurately control the operating state of the fault detection system 1 by controlling the on and off states of the multiple first switching tubes Q1. When the second control circuit 14 controls the multiple first switching tubes Q1 to be turned on, the second resistor R2 acts as a voltage divider resistor to ensure the reliability of the voltage input to the loop where the detection branch 111 is located. When the second control circuit 14 controls the multiple first switching tubes Q1 to be turned off, the energy consumption of the fault detection system 1 can be reduced, saving a certain amount of energy.

[0074] Optionally, the first switch tube Q1 can be a hardware switch, an N-type metal oxide semiconductor (NMOS) field effect transistor, a P-type metal oxide semiconductor (PMOS) field effect transistor, an IGBT, a transistor, a relay circuit or other devices or circuits that can achieve on-off functions. This application does not impose any specific restrictions on this.

[0075] For example, Figure 6 As shown, the first switch tube Q1 can be a PMOS tube, the gates of the multiple PMOS tubes are connected to the second control circuit 14, the sources of the multiple PMOS tubes are connected to the power supply voltage VCC, and the drains of the multiple PMOS tubes are respectively connected one-to-one with one end of the multiple second resistors R2. When the fault detection system 1 needs to perform detection, the second control circuit 14 will control the gate and source of the PMOS tube to be connected, thereby connecting the source and drain of the PMOS, so that the power supply voltage VCC can be loaded into the loop where the detection branch 111 is located through the second resistor R2.

[0076] In one example, if Figure 6 As shown, the fault detection system 1 further includes a third resistor R3, one end of which is connected to the controlled terminals of the plurality of first switching transistors Q1, and the other end of which is connected to the first terminals of the plurality of first switching transistors Q1. In this example, when the first switching transistor Q1 is a PMOS transistor, providing the third resistor R3 between the gate and source of the PMOS transistor can limit the gate current of the PMOS transistor, improve the anti-interference capability of the PMOS transistor, improve the switching characteristics, and match the circuit impedance, thereby improving the overall operational stability and reliability of the fault detection system 1.

[0077] Suppose you want to reduce the wiring harness to simplify the system wiring. In an example, Figure 7 As shown, the fault detection system 1 also includes a fourth resistor R4 and a second switch circuit 16, one end of the fourth resistor R4 is connected to the second control circuit 14, the first end of the second switch circuit 16 is connected to the other end of the fourth resistor R4, the second end of the second switch circuit 16 is connected to the controlled ends of the multiple first switch circuits 15, and the third end and the fourth end of the second switch circuit 16 are connected to the ground end GND.

[0078] In this example, when the fault detection system 1 is required to perform detection, the second control circuit 14 can control the second switch circuit 16 to be turned on. When the second switch circuit 16 is turned on, the multiple first switch circuits 15 connected to the second switch circuit 16 will also be turned on accordingly, so that the power supply voltage VCC can be loaded into the loop where the detection branch 111 is located through the second resistor R2, so that the fault detection system 1 can operate normally. When the fault detection system 1 is not required to perform detection, the second control circuit 14 will control the second switch circuit 16 to be turned off. After the second switch circuit 16 is turned off, the multiple first switch circuits 15 connected to the second switch circuit 16 will also be turned off accordingly, so that the power supply voltage VCC will not be loaded into the loop where the detection branch 111 is located. At this time, the detection branch 111 and other circuits do not work.

[0079] In this way, the second control circuit 14 can precisely control the on / off states of multiple first switch circuits 15 by controlling the on / off states of the second switch circuit 16, thereby precisely controlling the operating state of the fault detection system 1. When the second control circuit 14 turns on the second switch circuit 16, the multiple first switch circuits 15 connected to the second switch circuit 16 are simultaneously turned on, resulting in high control synchronization. Furthermore, there is no need to connect each first switch circuit 15 to the second control circuit 14, which reduces the layout of the wiring harness and simplifies the system's wiring.

[0080] It is worth noting that the connection between the plurality of first switch circuits 15 and the second control circuit 14 can be set according to actual needs, for example, Figure 5 As shown, multiple first switch circuits 15 can be connected to the second control circuit 14 through a wiring harness. When one of the wiring harnesses fails, the first switch circuits 15 connected to other wiring harnesses can still be turned on and off normally, thereby improving the reliability of the fault detection system 1. For another example, Figure 7 As shown, multiple first switch circuits 15 can be connected to the second switch circuit 16, and the second switch circuit 16 is connected to the first control circuit 13 to simplify the layout of the wiring harness. This application does not make any specific restrictions on this.

[0081] In order to further reduce the layout of the wiring harness, in one example, Figure 7 As shown, the controlled terminals of multiple first switch circuits 15 are interconnected to form a common node, and the second terminals of the second switch circuits 16 are connected to the common node. In this way, multiple first switch circuits 15 can be connected to the second switch circuits 16 through the same wiring harness, further shortening the length of the wiring harness and simplifying the system wiring.

[0082] Optionally, the second switch circuit 16 can be a switch, an NMOS field effect transistor, a PMOS field effect transistor, an IGBT, a transistor, a relay circuit or other devices or circuits that can achieve on-off functions, and this application does not impose specific restrictions on this.

[0083] For example, Figure 7As shown, the second switch circuit 16 can be a photocoupler; the anode of the light-emitting diode in the photocoupler serves as the first end of the second switch circuit 16 and is connected to the other end of the fourth resistor R4; the cathode of the light-emitting diode in the photocoupler serves as the third end of the second switch circuit 16 and is connected to the ground terminal GND; the collector of the transistor in the photocoupler serves as the second end of the second switch circuit 16 and is connected to the controlled ends of the plurality of first switch circuits 15; and the emitter of the transistor in the photocoupler serves as the fourth end of the second switch circuit 16 and is connected to the ground terminal GND. The second control circuit 14 can control the on-off of the transistor by changing the current of the light-emitting diode, that is, the on-off of the transistor is controlled by outputting different high and low levels of the current of the light-emitting diode to output corresponding high and low level detection signals. This has high flexibility and fast response speed. In addition, the light-emitting diode only needs a small current to drive the light emission, and the power consumption is low. Secondly, the light-emitting diode circuit and the transistor circuit in the photoelectric coupler composed of the light-emitting diode and the transistor are electrically isolated, that is, there is no direct electrical connection between the second control circuit 14 corresponding to the light-emitting diode and the load circuit corresponding to the transistor, which can effectively prevent high voltage or large current from damaging the circuit, realize electrical isolation, and improve the service life and reliability of the fault detection system 1.

[0084] In one example, if Figure 8 As shown, each detection branch 111 also includes a fifth resistor R5 and a filter capacitor C, one end of the fifth resistor R5 is connected to the input end of the OR gate OR, the other end of the fifth resistor R5 is connected to one end of the first resistor R1, the first plate of the filter capacitor C is connected to one end of the first resistor R1 and the other end of the fifth resistor R5, and the second plate of the filter capacitor C is connected to the ground end GND.

[0085] In this example, the RC filter formed by the fifth resistor R5 and the filter capacitor C can filter out high-frequency noise and reduce the interference component in the first detection signal DET1 output by the first resistor R1. By removing noise through the fifth resistor R5 and the filter capacitor C, the signal-to-noise ratio can be improved, electromagnetic interference can be reduced, and the detection signal can be more easily received by the OR gate OR. Secondly, the fifth resistor R5 and the filter capacitor C can also smooth the first detection signal DET1, reduce the fluctuation and jitter of the first detection signal DET1, and make the first detection signal DET1 connected to the OR gate OR more stable. In this way, by setting the fifth resistor R5 and the filter capacitor C between multiple first resistors R1 and the OR gate OR, the high-frequency noise in the first detection signal DET1 can be filtered out, the first detection signal DET1 can be stabilized, the signal-to-noise ratio can be improved, and electromagnetic interference can be reduced, thereby ensuring the reliability of the first detection signal DET1 received by the OR gate OR, and further ensuring the detection reliability of the fault detection system 1.

[0086] It is worth noting that a first resistor R1 and a filter capacitor C are disposed between each first resistor R1 and the OR gate OR, wherein the second plates of the plurality of filter capacitors C are connected to each other and to the ground terminal GND.

[0087] When the first control circuit 13 determines that the high-voltage interlock circuit is disconnected, it processes the multiple first detection signals DET1 received to determine the connection status of the multiple low-voltage detection connectors 2, thereby locating the fault location in the high-voltage interlock circuit. In addition to the low-voltage detection connector 2 itself failing, it may also be short-circuited to the power supply or short-circuited to ground. To further improve the detection reliability of the fault detection system 1 provided by the present application, the first control circuit 13 provided by the present application is also capable of determining the specific fault status of the faulty low-voltage detection connector 2, such as whether the low-voltage detection connector 2 is disconnected, short-circuited to the power supply, or short-circuited to ground.

[0088] In one example, if Figure 9 As shown, the fault detection system 1 further includes a comparison circuit 17, which is connected to one end of the first resistor R1, the logic gate circuit 12, and the first control circuit 13. The comparison circuit 17 is also configured to access multiple comparison thresholds. The comparison circuit 17 is configured to generate multiple electrical signals based on the first detection signal DET1 and the multiple comparison thresholds, and output the multiple electrical signals to the logic gate circuit 12. The logic gate circuit 12 is further configured to generate a third detection signal DET3 based on the multiple electrical signals and output the third detection signal DET3 to the first control circuit 13. In this example, the first control circuit 13 is further configured to determine the connection status of the low-voltage detection connector 2 based on the third detection signal DET3. When the first control circuit 13 determines that the connection status of the low-voltage detection connector 2 is abnormal based on the third detection signal DET3, the first control circuit 13 is further configured to determine a fault status of the low-voltage detection connector 2 based on the multiple electrical signals.

[0089] The first resistor R1 in each detection circuit 111 is provided with a comparison circuit 17. While outputting the first detection signal DET to the first control circuit 13 and the logic gate circuit 12, the first resistor R1 also synchronously outputs the first detection signal DET1 to the comparison circuit 17. The comparison circuit 17 and the logic gate circuit 12 are used in conjunction to generate a third detection signal DET3. It is worth noting that the first control circuit 13 provided in the present application can simultaneously receive the first detection signal DET1 and the third detection signal DET3, and determine the low-voltage detection connector 2 that specifically fails at this time and the corresponding fault state of the low-voltage detection connector 2 based on the first detection signal DET1 and the third detection signal DET3, so as to improve the detection reliability and accuracy of the fault detection system 1.

[0090] When the first control circuit 13 determines that the high-voltage interlock circuit is connected based on the second detection signal DET2, it is determined that all low-voltage detection connectors 2 are properly connected. There is no need to determine the connection status of each low-voltage detection connector 2 based on multiple first detection signals DET1. Similarly, when the first control circuit 13 determines that the connection status of the low-voltage detection connector 2 is normal based on the third detection signal DET3, it is determined that the low-voltage detection connector 2 is properly connected and no fault is present. There is no need to determine the fault status of the low-voltage detection connector 2 based on multiple electrical signals. This simplifies the calculation and processing steps of the first control circuit 13 and saves resources of the first control circuit 13. When the first control circuit 13 determines that the high-voltage interlock circuit is disconnected based on the second detection signal DET2, the first control circuit 13 can determine the specific fault location of the high-voltage interlock circuit based on multiple first detection signals DET1 and the third detection signal DET3, that is, the low-voltage detection connector 2 with the abnormal connection. The first control circuit 13 then determines the specific fault state of the low-voltage detection connector 2 based on multiple electrical signals corresponding to the low-voltage detection connector 2 with the abnormal connection, so as to further improve the detection reliability of the fault detection system 1 provided in this application.

[0091] In this example, after the first control circuit 13 determines the on / off state of the high-voltage interlock circuit based on the second detection signal DET2, the first control circuit 13 can simultaneously determine that the connection state of the low-voltage detection connector 2 at this time is abnormal based on the first detection signal DET1 and the third detection signal DET3, and then determine the fault state of the faulty low-voltage detection connector 2 at this time based on the multiple electrical signals output by the comparison circuit 17, so that the staff can determine the specific fault state of the low-voltage detection connector 2, and quickly repair or replace the low-voltage detection connector 2 based on the fault state, further improving the detection and troubleshooting efficiency of the fault detection system 1, effectively solving the problem of low efficiency in troubleshooting high-voltage interlock system faults, and improving a certain degree of safety.

[0092] In this way, the first control circuit 13 provided in the present application can know the connectivity status of the high-voltage interlocking circuit based on the second detection signal DET2, and then determine the connection status of the low-voltage detection connector 2 based on the first detection signal DET1 and the third detection signal DET3, that is, determine the specific fault location of the high-voltage interlocking circuit. When it is determined that the low-voltage detection connector 2 is abnormally connected, the first control circuit 13 can also determine the specific fault status of the low-voltage detection connector 2 based on multiple electrical signals. The detection is more comprehensive and the detection accuracy and reliability are higher.

[0093] In one example, the plurality of comparison thresholds include a first comparison threshold Vth1, a second comparison threshold Vth2, and a third comparison threshold Vth3, and the plurality of electrical signals include a first electrical signal OUT1, a second electrical signal OUT2, and a third electrical signal OUT3. Figure 10As shown, the comparison circuit 17 includes a first comparator COMP1, a second comparator COMP2, and a third comparator COMP3. The second comparison threshold Vth2 is greater than the first comparison threshold Vth1 and less than the third comparison threshold Vth3, that is, the relationship between the three comparison thresholds is: first comparison threshold Vth1 < second comparison threshold Vth2 < third comparison threshold Vth3.

[0094] The non-inverting input terminal of the first comparator COMP1 (such as Figure 10 The “+” shown in FIG1 is connected to the first comparison threshold Vth1, and the inverting input terminal of the first comparator COMP1 (as shown in FIG1 ) is connected to the first comparison threshold Vth1. Figure 10 The output end of the first comparator COMP1 is connected to the first control circuit 13 and the logic gate circuit 12. The first comparator COMP1 is used to generate a first electrical signal OUT1 based on the first comparison threshold Vth1 and the first detection signal DET1, and output the first electrical signal OUT1 to the logic gate circuit 12. The non-inverting input end of the second comparator COMP2 is connected to the second comparison threshold Vth2, the inverting input end of the second comparator COMP2 is connected to one end of the first resistor R1, and the output end of the second comparator COMP2 is connected to the first control circuit 13 and the logic gate circuit 12. The second comparator COMP2 is used to generate a second electrical signal OUT2 based on the second comparison threshold Vth2 and the first detection signal DET1, and output the second electrical signal OUT2 to the logic gate circuit 12. The non-inverting input of the third comparator COMP3 is connected to the third comparison threshold Vth3, the inverting input of the third comparator COMP3 is connected to one end of the first resistor R1, and the output of the third comparator COMP3 is connected to the first control circuit 13 and the logic gate circuit 12. The third comparator COMP3 is used to generate a third electrical signal OUT3 based on the third comparison threshold Vth3 and the first detection signal DET1 and output it to the logic gate circuit 12.

[0095] In this example, by using the first comparator COMP1, the second comparator COMP2, and the third comparator COMP3, in combination with multiple different comparison thresholds, the first control circuit 13 can not only determine whether the low-voltage detection connector 2 itself has failed, but also determine whether the low-voltage detection connector 2 is short-circuited to the power supply terminal and short-circuited to ground, thereby enabling the fault detection system 1 to accurately detect the fault state of the low-voltage detection connector 2.

[0096] Optionally, to reduce wiring harness, e.g. Figure 10 As shown, the non-inverting input terminal of the first comparator COMP1, the non-inverting input terminal of the second comparator COMP2 and the non-inverting input terminal of the third comparator COMP3 can be connected to a common node, and connected to one end of the first resistor R1 through the common node.

[0097] In one example, if Figure 11 As shown, the fault detection system 1 further includes a threshold generation circuit 18. The threshold generation circuit 18 is connected to the non-inverting input of the first comparator COMP1, the non-inverting input of the second comparator COMP2, and the non-inverting input of the third comparator COMP3. The threshold generation circuit 18 is configured to generate a first comparison threshold Vth1, a second comparison threshold Vth2, and a third comparison threshold Vth3 based on the power supply voltage VCC. In this example, the threshold generation circuit 18 can be used to set different first comparison thresholds Vth1, Vth2, and Vth3 to accurately detect different fault conditions of the low-voltage detection connector 2.

[0098] For example, Figure 11 As shown, the threshold generation circuit 18 includes a first voltage divider module 181, a second voltage divider module 182, and a third voltage divider module 183. The first voltage divider module 181 is connected to the power supply voltage VCC at its first terminal, the second terminal of the first voltage divider module 181 is connected to the non-inverting input terminal of the first comparator COMP1 at its third terminal, and the ground terminal GND at its third terminal. The first voltage divider module 181 is configured to generate a first comparison threshold value Vth1 based on the power supply voltage VCC and output it to the first comparator COMP1. The second voltage divider module 182 is connected to the power supply voltage VCC at its first terminal, the second terminal of the second voltage divider module 182 is connected to the non-inverting input terminal of the second comparator COMP2 at its third terminal, and the ground terminal GND at its third terminal. The second voltage divider module 182 is configured to generate a second comparison threshold value Vth2 based on the power supply voltage VCC and output it to the second comparator COMP2. The first end of the third voltage divider module 183 is connected to the power supply voltage VCC, the second end of the third voltage divider module 183 is connected to the non-inverting input end of the third comparator COMP3, and the third end of the third voltage divider module 183 is connected to the ground end GND. The third voltage divider module is used to generate a third comparison threshold Vth3 based on the power supply voltage VCC and output it to the third comparator COMP3.

[0099] Optional, such as Figure 11As shown, the first voltage divider module 181 includes a sixth resistor R6 and a seventh resistor R7, the second voltage divider module 182 includes an eighth resistor R8 and a ninth resistor R9, the third voltage divider module 183 includes a tenth resistor R10 and an eleventh resistor R11, and the fault detection system 1 further includes a twelfth resistor R12 and a thirteenth resistor R13. One end of the sixth resistor R6, one end of the eighth resistor R8, one end of the tenth resistor R10, and one end of the twelfth resistor R12 are connected to the power supply voltage VCC. The other end of the sixth resistor R6, one end of the seventh resistor R7, and the non-inverting input terminal of the first comparator COMP1 are connected to a fourth node d. The other end of the eighth resistor R8, one end of the ninth resistor R9, and the non-inverting input terminal of the second comparator COMP2 are connected to a fifth node e. The other end of the tenth resistor R10, one end of the eleventh resistor R11, and the non-inverting input terminal of the third comparator COMP3 are connected to a sixth node f. The other end of the twelfth resistor R12 is connected to one end of the first resistor R1, one end of the thirteenth resistor R13 is connected to the other end of the first resistor R1, and the other end of the seventh resistor R7, the other end of the ninth resistor R9, the other end of the eleventh resistor R11 and the other end of the thirteenth resistor R13 are connected to the ground terminal GND.

[0100] The resistance of the sixth resistor R6 is set to 3 times the resistance of the seventh resistor R7, so the first comparison threshold Vth1 corresponding to the fourth node d is 1 / 4 VCC. The resistance of the eighth resistor R8 is set to 2 / 3 times the resistance of the ninth resistor R9, so the second comparison threshold Vth2 corresponding to the fifth node e is 3 / 5 VCC. The resistance of the tenth resistor R10 is set to 1 / 5 times the resistance of the eleventh resistor R11, so the third comparison threshold Vth3 corresponding to the sixth node f is 5 / 6 VCC. The resistance values ​​of the first resistor R1, the twelfth resistor R12, and the thirteenth resistor R13 are set to be equal.

[0101] In this example, when the low-voltage detection connector 2 is connected normally, the voltage Va corresponding to the first node a is 1 / 2VCC, Vth1<Va<Vth2<Vth3, the first electrical signal OUT1 generated by the first comparator COMP1 based on the first comparison threshold Vth1 and the first detection signal DET1 is low, the second electrical signal OUT2 generated by the second comparator COMP2 based on the second comparison threshold Vth2 and the first detection signal DET1 is high, and the third electrical signal OUT3 generated by the third comparator COMP3 based on the third comparison threshold Vth3 and the first detection signal DET1 is high. At this time, the third detection signal DET3 generated by the logic gate circuit 12 based on the first electrical signal OUT1, the second electrical signal OUT2 and the third electrical signal OUT3 is a high-level detection signal. The first control circuit 13 knows that the low-voltage detection connector 2 is normally connected based on the high-level detection signal.

[0102] When the low-voltage detection connector 2 is abnormally connected, the voltage Va corresponding to the first node a is equal to 2 / 3 VCC. At this time, Vth1<Vth2<Va<Vth3. The first electrical signal OUT1 generated by the first comparator COMP1 based on the first comparison threshold Vth1 and the first detection signal DET1 is low. The second electrical signal OUT2 generated by the second comparator COMP2 based on the second comparison threshold Vth2 and the first detection signal DET1 is low. The third electrical signal OUT3 generated by the third comparator COMP3 based on the third comparison threshold Vth3 and the first detection signal DET1 is high. At this time, the third detection signal DET3 generated by the logic gate circuit 12 based on the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3 is a low-level detection signal. The first control circuit 13 detects that the low-voltage detection connector 2 is abnormally connected based on this low-level detection signal.

[0103] When the low-voltage detection connector 2 is short-circuited to the power supply, the voltage Va corresponding to the first node a is equal to VCC. At this time, Vth1<Vth2<Vth3<Va. The first electrical signal OUT1 generated by the first comparator COMP1 based on the first comparison threshold Vth1 and the first detection signal DET1 is at a low level. The second electrical signal OUT2 generated by the second comparator COMP2 based on the second comparison threshold Vth2 and the first detection signal DET1 is at a low level. The third electrical signal OUT3 generated by the third comparator COMP3 based on the third comparison threshold Vth3 and the first detection signal DET1 is at a low level. At this time, the third detection signal DET3 generated by the logic gate circuit 12 based on the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3 is a low-level detection signal. The first control circuit 13 detects that the low-voltage detection connector 2 is abnormally connected based on this low-level detection signal and determines that the low-voltage detection connector 2 is short-circuited to the power supply based on the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3.

[0104] When the low voltage detection connector 2 is short-circuited to the ground, that is, the first and second terminals of the low voltage detection connector 2 are short-circuited to the power supply and the ground terminal GND, the voltage Va corresponding to the first node a is equal to 0. At this time, Va<Vth1<Vth2<Vth3, the first electrical signal OUT1 generated by the first comparator COMP1 based on the first comparison threshold Vth1 and the first detection signal DET1 is at a high level, the second electrical signal OUT2 generated by the second comparator COMP2 based on the second comparison threshold Vth2 and the first detection signal DET1 is at a high level, and the third comparator COMP3 based on the third comparison threshold Vth2 and the first detection signal DET1 is at a high level. The third electrical signal OUT3 generated by the comparison threshold Vth3 and the first detection signal DET1 is at a high level. At this time, the third detection signal DET3 generated by the logic gate circuit 12 based on the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3 is a low-level detection signal. The first control circuit 13 detects that the low-voltage detection connector 2 is abnormally connected based on the low-level detection signal, and further determines that the first and second terminals of the low-voltage detection connector 2 are short-circuited to the power supply and the ground terminal GND based on the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3.

[0105] The corresponding relationship between the fault type of the low voltage detection connector 2 and the first electrical signal OUT1 , the second electrical signal OUT2 and the third electrical signal OUT3 is shown in Table 1.

[0106]

[0107]

[0108] Table 1

[0109] Optionally, the first voltage dividing module 181 , the second voltage dividing module 182 and the third voltage dividing module 183 may also use other devices or circuits that can achieve the above functions, and this application does not impose any specific restrictions on this.

[0110] In one example, if Figure 12 As shown, the logic gate circuit 14 may include an inverter INV and an AND gate AND, the input end of the inverter INV is connected to the output end of the first comparator COMP1, the input end of the AND gate AND is respectively connected to the output end of the inverter INV, the output end of the second comparator COMP2 and the output end of the third comparator COMP3, and the output end of the AND gate AND is connected to the first control circuit 13.

[0111] The logic of the AND gate ANDR is "1" when all "1s" are present, and "0" when any "0" is present. It is understood that only when the first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3, which are inverted by the inverter INVR and connected to the AND gate AND, are all high-level, will the third detection signal DET3 output by the AND gate AND be a high-level detection signal. In this case, the first control circuit 13 can determine that the low-voltage detection connector 2 is properly connected based on the high-level detection signal. When any one of the electrical signals 1 input by the AND gate AND is at a low level, the third detection signal DET3 output by the AND gate AND is a low-level detection signal. The first control circuit 13 can determine, based on the low-level detection signal, that the low-voltage detection connector 2 is abnormally connected at this time, and then process the input first electrical signal OUT1, the second electrical signal OUT2, and the third electrical signal OUT3 to determine the specific fault state of the low-voltage detection connector 2. This allows staff to determine the specific fault state of the low-voltage detection connector 2 and quickly repair or replace the low-voltage detection connector 2 based on the fault state, further improving the detection and troubleshooting efficiency of the fault detection system 1, effectively solving the problem of low efficiency in troubleshooting high-voltage interlocking system faults, and improving safety to a certain extent.

[0112] In this example, the AND gate ANDR can simplify multiple electrical signals into a third detection signal DET3. The first control circuit 13 can determine the fault status of the corresponding low-voltage detection connector 2 based on the third detection signal DET3 without setting up an additional multiplexer or other logical combination, which simplifies the system. In addition, the AND gate ANDR can quickly change the output state (i.e., the third detection signal DET3) when the input signal (i.e., multiple electrical signals) changes, and the response speed is fast, so that the first control circuit 13 can accurately know the current fault status of the low-voltage detection connector 2 based on the third detection signal DET3.

[0113] When the fault detection system 1 further includes a twelfth resistor R12 and a thirteenth resistor R13, in this example, Figure 13As shown, the first switch circuit 15 may include a second switch transistor Q2. The controlled terminal of the second switch transistor Q2 is connected to the second terminal of the second switch circuit 16. The first terminal of the second switch transistor Q2 is connected to the other terminal of the twelfth resistor R12 to receive the power supply voltage VCC. The second terminal of the second switch transistor Q2 is connected to one terminal of the first resistor R1 and the first terminal of the corresponding low-voltage detection connector 2. It is worth noting that the figure only uses one first resistor R1 and one low-voltage detection connector 2 as an example, and therefore only one second switch transistor Q2 is connected to the second switch circuit 16. If multiple first resistors R1 and one low-voltage detection connector 2 are shown, the second terminal of the second switch circuit 16 is connected to the controlled terminals of multiple second switch transistors Q2. The control logic and effects achieved by the second switch transistor Q2 can refer to the control logic and effects of the first switch transistor Q1 described above, and will not be further described.

[0114] Optional, such as Figure 13 As shown, the second switch tube Q2 can be a PNP transistor, the emitter of the PNP transistor is connected to the other end of the twelfth resistor R1, the base of the PNP transistor is connected to the second end of the second switch circuit 16, and the collector of the PNP transistor is connected to one end of the first resistor R1 and the first end of the corresponding low-voltage detection connector 2. The second switch tube Q2 can also be a hardware switch, an NMOS field-effect transistor, a PMOS field-effect transistor, an IGBT, an NPN transistor, a relay circuit, or other devices or circuits that can achieve on-off functions. This application does not impose specific restrictions on this.

[0115] In summary, the detection branch 111 provided in the present application can convert the connection status of the low-voltage detection connector 2 into high and low-level detection signals that can be recognized by the logic gate circuit 12 and the first control circuit 13, that is, the detection branch 111 can convert the connection status of the low-voltage detection connector 2 in real time, and send the converted first detection signal DET1 to the logic gate circuit 12 and the first control circuit 13. The logic gate circuit 12 can generate the second detection signal DET2 based on these first detection signals DET1, so that the first control circuit 13 can accurately know the on and off status of the high-voltage interlocking circuit based on the second detection signal DET2. When the first control circuit 13 determines that the high-voltage interlock circuit is disconnected based on the second detection signal DET2, it then determines the specific fault location (i.e., the abnormally connected low-voltage detection connector 2) based on multiple first detection signals DET1 to achieve accurate detection of the connection status of the low-voltage detection connector 2 and the on-off status of the high-voltage interlock circuit, so that the staff can determine that the low-voltage detection connector 2 is faulty and quickly repair or replace the low-voltage detection connector 2, thereby improving the detection and troubleshooting efficiency, effectively solving the problem of low efficiency in troubleshooting high-voltage interlock system faults, and improving a certain degree of safety. Secondly, when the first control circuit 13 determines that the high-voltage interlock circuit is connected based on the second detection signal DET2, the first control circuit 13 can know that the low-voltage detection connectors 2 are all normally connected at this time, and there is no need to determine the connection status of each low-voltage detection connector 2 based on multiple first detection signals DET1, which simplifies the calculation and processing steps of the first control circuit 13 and saves resources of the first control circuit 13.

[0116] The vehicle in the embodiments of the present application may be an electric vehicle, i.e., a vehicle that uses electricity as a power source and drives its wheels through an electric motor. Electric vehicles include, but are not limited to, battery electric vehicles (BEVs), plug-in hybrid electric vehicles (PHEVs), hybrid electric vehicles (HEVs), and extended-range electric vehicles (EREVs). This application does not impose specific restrictions on this.

[0117] The vehicle provided in the embodiment of the present application has all the beneficial effects of the above-mentioned fault detection system 1 because it has the fault detection system 1 of the above-mentioned embodiment, and therefore, details thereof will not be given here.

[0118] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0119] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0120] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A fault detection system, applied to a high voltage interlock circuit having multiple low voltage detection connectors, characterized in that: The fault detection system comprises: a detection circuit, the detection circuit comprising a plurality of detection branches, the plurality of detection branches being connected to the plurality of low-voltage detection connectors in a one-to-one correspondence, the detection branches being configured to output corresponding first detection signals based on the connection status of the low-voltage detection connectors; a logic gate circuit, the logic gate circuit being connected to the plurality of detection branches, the logic gate circuit receiving first detection signals from the plurality of detection branches and generating a second detection signal based on the plurality of first detection signals; and a first control circuit, the first control circuit being connected to the logic gate circuit and the plurality of detection branches, the first control circuit being configured to receive the second detection signal and a plurality of the first detection signals, the first control circuit being configured to determine an on / off state of the high-voltage interlock circuit based on the second detection signal; and when the first control circuit determines that the on / off state of the high-voltage interlock circuit is disconnected based on the second detection signal, the first control circuit being further configured to determine a connection state of a plurality of the low-voltage detection connectors based on the plurality of the first detection signals; Each of the detection branches includes: a first resistor, one end of the first resistor being connected to the first end of the low voltage detection connector, the logic gate circuit, and the first control circuit, and the other end of the first resistor being connected to the second end of the low voltage detection connector and a ground end; The fault detection system further comprises: a comparison circuit, the comparison circuit being connected to one end of the first resistor, the logic gate circuit, and the first control circuit, the comparison circuit being further configured to access a plurality of comparison thresholds, the comparison circuit being configured to generate a plurality of electrical signals based on the first detection signal and the plurality of comparison thresholds, and output the plurality of electrical signals to the logic gate circuit; The logic gate circuit is further configured to generate a third detection signal based on the plurality of electrical signals and output the signal to the first control circuit; the first control circuit is further configured to determine a connection state of the low-voltage detection connector based on the third detection signal; and when the first control circuit determines that the connection state of the low-voltage detection connector is abnormal based on the third detection signal, the first control circuit is further configured to determine a fault state of the low-voltage detection connector based on the plurality of electrical signals. The plurality of comparison thresholds include a first comparison threshold, a second comparison threshold, and a third comparison threshold; the plurality of electrical signals include a first electrical signal, a second electrical signal, and a third electrical signal; and the comparison circuit includes: a first comparator, wherein a non-inverting input terminal of the first comparator is connected to the first comparison threshold, an inverting input terminal of the first comparator is connected to one end of the first resistor, an output terminal of the first comparator is connected to the first control circuit and the logic gate circuit, and the first comparator is configured to generate the first electrical signal based on the first comparison threshold and the first detection signal and output the first electrical signal to the logic gate circuit; a second comparator, wherein a non-inverting input terminal of the second comparator is connected to the second comparison threshold, an inverting input terminal of the second comparator is connected to one end of the first resistor, an output terminal of the second comparator is connected to the first control circuit and the logic gate circuit, and the second comparator is configured to generate the second electrical signal based on the second comparison threshold and the first detection signal and output the second electrical signal to the logic gate circuit; and a third comparator, wherein a non-inverting input terminal of the third comparator is connected to the third comparison threshold, an inverting input terminal of the third comparator is connected to one end of the first resistor, an output terminal of the third comparator is connected to the first control circuit and the logic gate circuit, and the third comparator is used to generate the third electrical signal based on the third comparison threshold and the first detection signal and output the third electrical signal to the logic gate circuit; The second comparison threshold is greater than the first comparison threshold and less than the third comparison threshold.

2. The fault detection system according to claim 1, characterized in that: The logic gate circuit comprises: An OR gate, wherein the input end of the OR gate is respectively connected to one end of the plurality of first resistors, and the output end of the OR gate is connected to the first control circuit.

3. The fault detection system according to claim 1, characterized in that: The fault detection system further comprises: A threshold generation circuit is connected to the non-inverting input terminal of the first comparator, the non-inverting input terminal of the second comparator, and the non-inverting input terminal of the third comparator, and the threshold generation circuit is used to generate the first comparison threshold, the second comparison threshold, and the third comparison threshold based on the power supply voltage.

4. The fault detection system according to claim 3, characterized in that: The threshold generation circuit includes: a first voltage divider module, wherein a first end of the first voltage divider module is connected to the power supply voltage, a second end of the first voltage divider module is connected to the non-inverting input end of the first comparator, and a third end of the first voltage divider module is connected to the ground end, and the first voltage divider module is used to generate the first comparison threshold based on the power supply voltage and output the first comparison threshold to the first comparator; a second voltage divider module, wherein a first terminal of the second voltage divider module is connected to the power supply voltage, a second terminal of the second voltage divider module is connected to the non-inverting input terminal of the second comparator, and a third terminal of the second voltage divider module is connected to the ground terminal, and the second voltage divider module is configured to generate a second comparison threshold based on the power supply voltage and output the second comparison threshold to the second comparator; and A third voltage divider module, wherein the first end of the third voltage divider module is connected to the power supply voltage, the second end of the third voltage divider module is connected to the non-inverting input end of the third comparator, and the third end of the third voltage divider module is connected to the ground end. The third voltage divider module is used to generate the third comparison threshold based on the power supply voltage and output it to the third comparator.

5. The fault detection system according to claim 1, characterized in that: The logic gate circuit comprises: an inverter, an input terminal of the inverter being connected to an output terminal of the first comparator; and An AND gate, wherein the input end of the AND gate is respectively connected to the output end of the inverter, the output end of the second comparator, and the output end of the third comparator, and the output end of the AND gate is connected to the first control circuit.

6. The fault detection system according to any one of claims 1 to 5, characterized in that: The fault detection system further comprises: a second control circuit, the second control circuit being connected to the first control circuit; and a plurality of first switch circuits, wherein controlled ends of the plurality of first switch circuits are connected to the second control circuit, first ends of the plurality of first switch circuits are connected to a power supply voltage, and second ends of the plurality of first switch circuits are connected one-to-one with first ends of the plurality of detection branches and the plurality of low-voltage detection connectors; The second control circuit is used to control the on and off of the first switch circuit to correspondingly control the working state of the detection branch.

7. A vehicle, characterized in that: The vehicle comprises: A high-voltage interlock circuit, wherein the high-voltage interlock circuit is provided with a plurality of low-voltage detection connectors; The fault detection system according to any one of claims 1 to 6, wherein the fault detection system is connected to a plurality of the low voltage detection connectors.

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