Floating-point number format conversion apparatus and method, storage medium and program products

Abstract

This application discloses a floating-point number format conversion apparatus and method, storage medium, and program product, relating to the field of floating-point number format conversion technology. The apparatus includes a preprocessing unit and a conversion mapping unit. The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect rounding operations to generate corresponding index values, wherein the bit width of the index values ​​is smaller than the mantissa bit width of the input data. The conversion mapping unit is coupled to the preprocessing unit and stores multiple mapping relationships between index value ranges and numerical representations in a second floating-point format, used to look up the corresponding numerical representation in the second floating-point format as output data based on the index values. This application aims to reduce the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption, and operation latency.

Description

Technical Field

[0001] This application relates to the field of floating-point number format conversion technology, and in particular to a floating-point number format conversion device and method, storage medium and program product. Background Technology

[0002] In artificial intelligence, high-performance computing, and embedded systems, different precision floating-point representation formats are often used to strike a balance between computational precision and hardware resources. Common high-precision floating-point formats include single-precision floating-point numbers (Fp32), half-precision floating-point numbers (Fp16), brain-half-precision floating-point numbers (bf16), and tensor floating-point formats (tf32), while low-precision floating-point formats include 4-bit floating-point numbers (Fp4), 8-bit floating-point numbers (fp8 and bf8), etc. When converting high-precision floating-point numbers to low-precision floating-point numbers, rounding is usually required to retain as much valid information as possible. Common rounding rules include "rounding to the nearest even number".

[0003] Existing methods for converting high-precision to low-precision floating-point numbers are typically based on arithmetic logic units and complex rounding circuits. For example, when converting Fp32 to Fp4, traditional methods require multiple adders, comparators, and shifters of different bit widths, along with logic circuits for rounding to even numbers. While this implementation is functionally correct, it suffers from problems such as logical complexity, large hardware area, and high power consumption. In particular, as the conversion precision changes, the required bit width and number of logic circuits also increase accordingly, further exacerbating hardware resource consumption and reducing energy efficiency.

[0004] In traditional high-precision floating-point to low-precision floating-point format conversion schemes, such as the conversion from fp32 to fp4, the Round-to-Even algorithm is required. The Round-to-Even algorithm needs to process the complete 8-bit exponent and 23-bit mantissa, which is costly to implement in hardware. Moreover, the Round-to-Even algorithm has complex logic, requiring multiple levels of judgment and calculation, which increases additional hardware overhead and control complexity. When processing denormalized numbers, complex shift value calculation logic is also required, as well as cumbersome rounding logic in the denormalization and normalization conversion process, which increases a large number of redundant control circuits. Summary of the Invention

[0005] The purpose of this application is to at least solve one of the technical problems existing in the prior art, and to provide a floating-point number format conversion device and method, storage medium and program product, which aims to reduce the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption and operation latency.

[0006] In a first aspect, embodiments of this application provide a floating-point number format conversion device, including a preprocessing unit and a conversion mapping unit;

[0007] The preprocessing unit is used to receive input data in a first floating-point format and perform bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate a corresponding index value, wherein the bit width of the index value is smaller than the bit width of the mantissa of the input data.

[0008] The conversion mapping unit is coupled to the preprocessing unit. The conversion mapping unit stores multiple index value ranges and numerical representations in the second floating-point format, and is used to find the corresponding numerical representation in the second floating-point format as output data based on the index value.

[0009] The mantissa width of the second floating-point format is smaller than that of the first floating-point format.

[0010] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: the preprocessing unit performs bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate the corresponding index value. Since the bit width of the index value is smaller than the bit width of the mantissa of the input data, the mapping relationship in the conversion mapping unit can be relatively simple, and the method of using the mapping relationship to perform index lookup is relatively simple, further reducing the number of logic gates and circuit complexity. At the same time, there is no need to use round-to-even algorithms or other rounding algorithms, nor is there a need to specifically handle denormalized numbers and the conversion between denormalization and normalization, further reducing the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption and operation latency.

[0011] According to some embodiments of this application, the conversion mapping unit includes a lookup table memory, and the mapping relationship is stored in the lookup table memory in the form of a lookup table.

[0012] According to some embodiments of this application, the conversion mapping unit includes a decision circuit, which includes a plurality of comparators, each comparator having the same bit width as the index value, for comparing the index value with a preset threshold and outputting the corresponding numerical representation in the second floating-point format.

[0013] According to some embodiments of this application, the plurality of comparators are arranged in parallel or in series.

[0014] According to some embodiments of this application, when the plurality of comparators are arranged in series, the preceding comparator is used to pass the index value or a decision intermediate signal to the following comparator when the index value does not fall within its decision range.

[0015] According to some embodiments of this application, the preprocessing unit generates the index value by extracting the sign information, exponent adjustment information and partial mantissa information of the input data.

[0016] According to some embodiments of this application, the preprocessing unit generates the index value by compressing multiple sticky bits used for rounding judgment in the low-order bits of the mantissa of the input data.

[0017] According to some embodiments of this application, the preprocessing unit compresses the plurality of viscous bits into a single viscous judgment bit.

[0018] Secondly, embodiments of this application provide a floating-point number format conversion method, applied to a floating-point number format conversion device. The floating-point number format conversion device includes a preprocessing unit and a conversion mapping unit coupled to the preprocessing unit. The conversion mapping unit stores a mapping relationship between multiple index value ranges and numerical representations of a second floating-point format.

[0019] The method includes:

[0020] The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate corresponding index values.

[0021] The conversion mapping unit looks up the corresponding numerical representation in the second floating-point format based on the index value as the output data;

[0022] Wherein, the bit width of the index value is less than the bit width of the mantissa of the input data, and the bit width of the mantissa of the second floating-point format is less than the bit width of the mantissa of the first floating-point format.

[0023] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which are used to cause a computer to perform the floating-point number format conversion method as described in the second aspect above.

[0024] Fourthly, embodiments of this application provide a computer program product, including a computer program or computer instructions, the computer program or computer instructions being stored in a computer-readable storage medium, a processor of a computer device reading the computer program or computer instructions from the computer-readable storage medium, and the processor executing the computer program or computer instructions to cause the computer device to perform the floating-point number format conversion method as described in the second aspect above.

[0025] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0026] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0027] The present application will be further described below with reference to the accompanying drawings and embodiments;

[0028] Figure 1 This is a schematic block diagram of the structure of a floating-point number format conversion device provided in one embodiment of this application;

[0029] Figure 2 This is a schematic block diagram of the structure of a floating-point number format conversion device provided in another embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the structure of a floating-point number format conversion device provided in another embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the structure of a floating-point number format conversion device provided in another embodiment of this application;

[0032] Figure 5 This is a flowchart of a floating-point number format conversion method provided in one embodiment of this application. Detailed Implementation

[0033] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0034] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0035] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0036] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0037] The various embodiments of the floating-point number format conversion device of this application will be further described below with reference to the accompanying drawings.

[0038] like Figure 1 As shown, Figure 1 This is a schematic block diagram of a floating-point number format conversion device provided in an embodiment of this application. The device may include a preprocessing unit 110 and a conversion mapping unit 120.

[0039] The preprocessing unit 110 is used to receive input data in a first floating-point format and perform bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate a corresponding index value, wherein the bit width of the index value is smaller than the bit width of the mantissa of the input data.

[0040] The conversion mapping unit 120 is coupled to the preprocessing unit 110. The conversion mapping unit 120 stores multiple index value ranges and numerical representations in the second floating-point format, and is used to find the corresponding numerical representation in the second floating-point format as output data based on the index value.

[0041] The mantissa width of the second floating-point format is smaller than that of the first floating-point format.

[0042] Understandably, the preprocessing unit 110, as the front end of the floating-point format conversion, converts the high-bit-width original floating-point input into a low-bit-width compressed representation through configurable data compression and feature extraction techniques, thereby simplifying the circuit complexity of the subsequent conversion mapping unit 120, reducing power consumption, and improving processing speed.

[0043] The input to the preprocessing unit 110 is a complete floating-point number in the first floating-point format, such as 32-bit data of FP32. The output is an index value with a significantly reduced bit width, such that the bit width of the index value is smaller than the bit width of the mantissa of the input data. For example, the mantissa of the input 32-bit data of FP32 is 23 bits, and the bit width of the index value is less than 23 bits, which can be 11 bits, 8 bits or less. The compression process of the preprocessing unit 110 can be performed without losing key decision information to ensure that the accuracy of the final conversion result meets the system requirements.

[0044] For example, within the IEEE 754 floating-point arithmetic standard framework, the rounding operation of a complete floating-point number is affected by all low-order bits of information at and after the truncation boundary of its significant digits at a specific target precision. Specifically, when rounding a high-precision floating-point number to a lower-precision second floating-point format, the key database determining how to round includes three key bits: the Least Significant Bit of the retained part, which is the last significant digit to be retained at the target precision (e.g., if the second floating-point format has 3 mantissas, the third digit retained from the original mantissa is L); the Guard Bit, which is the first bit discarded immediately after the Least Significant Bit, representing the value of the highest bit in the truncated part. It is the core of determining which of the two target values ​​the original value is closer to. If the Guard Bit is 0, the discarded part is less than half a Least Significant Bit unit and is usually truncated; if the Guard Bit is 1, the discarded part is greater than or equal to half a Least Significant Bit unit; and the Sticky Bit, which is the logical OR result of all the remaining discarded bits after the Guard Bit.

[0045] The preprocessing unit 110 may include one or more parallel or serial processing paths. For example, direct truncation and rounding preprocessing can reduce the number of bits by directly discarding the low-order part of the floating-point mantissa. For example, the 23-bit mantissa of the FP32 can be truncated to 8 bits or less. Various rounding strategies can be combined, such as rounding to zero, rounding up, rounding down, or random rounding, to adapt to different error tolerance requirements. In this case, the preprocessing unit 110 can be designed with a configurable truncation window, select the range of bits to be retained through a multiplexer, and generate the compressed mantissa by combining rounding logic.

[0046] For example, the preprocessing unit 110 can map linear data with a large dynamic range to a nonlinear representation with a small dynamic range by means of dynamic range compression and nonlinear quantization, such as logarithmic transformation or A-law compression. For example, the logarithm of the absolute value of the input can be calculated first, and then quantized to an integer with a fixed bit width. This way, a wide range of index values ​​can be covered with fewer bits while preserving the relative relationship of the values. At this time, the preprocessing unit 110 can implement the nonlinear function by using a lookup table or use a piecewise linear approximation circuit to reduce complexity.

[0047] For example, the preprocessing unit 110 can extract statistical features as a compressed representation instead of directly retaining the numerical value itself through feature extraction and encoding based on statistical features. For example, it can calculate the exponent value, the high-order pattern of the mantissa, and the predefined interval number to which the numerical value belongs in the input data of the first floating-point format. For example, for the conversion from FP32 to FP4, the preprocessing unit 110 can extract only the exponent field and the first 3 bits of the mantissa, and then concatenate a sticky bit flag indicating whether the lower 20 bits of the mantissa are non-zero, forming a compressed code of about 10 bits.

[0048] For example, the preprocessing unit 110 can linearly map the input data to a fixed range through normalization and scaling preprocessing, and then quantize it with fixed points. Here, it is necessary to know or dynamically estimate the maximum and minimum values ​​of the input data, which can be achieved by using subtractors, multipliers and scaling shifters. If the range is statically known, the scaling factor can be fixed in the circuit.

[0049] For example, the preprocessing unit 110 may include a configuration register set for setting parameters such as the currently active compression mode, truncation position, and scaling factor; an input parsing unit for decomposing floating-point numbers into sign, exponent, and mantissa; multiple parallel compression engines, such as a truncation engine, a nonlinear transformation engine, and a feature extraction engine, each of which independently generates a candidate compressed representation; a compression quality evaluation unit for selecting the best one from the candidate representations based on a simple error metric or information entropy estimation; and an output formatting unit for packaging the selected compressed data into a fixed bit-width format, and possibly adding a small number of mode identifier bits for subsequent modules to interpret.

[0050] It is understandable that in complex digital systems, soft errors and hard errors are important factors affecting reliability. Soft errors are memory bit flips or combinational logic transient faults caused by high-energy particle impacts, while hard errors refer to permanent damage to the circuit. The simplified design of the preprocessing unit 110 directly reduces the number of potential fault points and improves the intrinsic reliability of the system. Specifically, fewer logic gates mean fewer transistors are likely to be affected by radiation effects and also reduce the possibility of timing violations. In terms of error detection and correction, the simplified data path is easier to implement an integrity check mechanism. For example, parity checks or cyclic redundancy check codes can be added to the data paths before and after dimensionality reduction. Due to the smaller data width, the overhead of the protection mechanism is relatively lower.

[0051] Based on this, the simplified preprocessing unit 110, due to its low resource occupancy and power consumption characteristics, enables more functional units to be integrated on the chip or other key modules to be enhanced. For example, in an AI accelerator, the saved area and power consumption can be used to add more computing cores or expand the on-chip cache, thereby directly improving the computing throughput; in data stream processing, the reduced latency brought by the simplified module can reduce pipeline bubbles and improve the overall execution efficiency; in power management, the low power consumption characteristics of the module make it easier to incorporate into the dynamic voltage and frequency adjustment strategy, and the power management unit can more finely control the power consumption status of each module to achieve better energy efficiency performance.

[0052] Exemplarily, the index value range and the numerical representation of the second floating-point format constitute the mapping mechanism for the conversion mapping unit 120 to implement floating-point format conversion. When the input index value falls within these intervals, it will trigger and output the pre-set numerical representation of the second floating-point format. The design of the index value range needs to consider multiple dimensions, including the continuity of the numerical values, the mutual exclusivity of the intervals, the accuracy of the boundaries, and the completeness of the mapping. First, the index value range itself can adopt various mathematical forms, and the most common is the closed interval condition. For example, to determine whether the input value x satisfies a ≤ x ≤ b. In actual hardware implementation, the closed interval comparison can be achieved by combining two comparison units. One checks x ≥ a, and the other checks x ≤ b, and then the two results are merged through a logical AND gate. It can also be a semi-open interval a ≤ x < b, which can avoid the same numerical value being repeatedly matched by multiple intervals. The open interval condition can have specific uses when dealing with special numerical values such as infinity or NaN.

[0053] More complex index value ranges may involve multiple discontinuous intervals. For example, in some floating-point conversions, it may be necessary to map small values ​​near 0 to a special denormalized representation, while mapping values ​​far from 0 to a normalized representation. This requires setting two separate interval conditions based on a deep analysis of the numerical characteristics of floating-point numbers. For instance, in the IEEE 754 standard, the index value range of floating-point numbers extends from tiny denormalized values ​​to enormous normalized values, including various special values ​​in between. Furthermore, the design of the numerical representation in the second floating-point format also needs to be considered and must conform to the encoding specifications of the target floating-point format. For the FP4 ultra-low precision format, the output value can be a 4-bit code. The 4-bit code needs to fully represent all possible states of the second floating-point format, including positive and negative normalized numbers, positive and negative denormalized numbers, positive and negative zero, and possible special values. Furthermore, the output value corresponding to each index value range may not be just a simple numerical code, but may also need to include additional control information. For example, in the conversion from FP32 to FP4, when the input value falls into a certain range, the output may not only be the FP4 bit mode, but may also include rounding control signals, exception flags or other metadata, or even a microinstruction or configuration parameter to control the subsequent processing pipeline.

[0054] For example, the specific settings for the index value range and the numerical representation of the second floating-point format can be based on detailed numerical analysis and optimization algorithms. Through statistical analysis of the numerical distribution of the source format, such as analyzing the numerical distribution characteristics of FP32 in a specific application scenario, by collecting a large amount of real workload data, it can be found that certain index value ranges appear with particularly high frequency. Hotspot areas should be more finely divided and more accurately mapped, while areas with very low frequency can be mapped more coarsely. Statistical analysis methods include histogram analysis, probability density function estimation, and cluster analysis.

[0055] After obtaining the numerical distribution characteristics, optimization algorithms can be applied to determine the optimal interval partitioning. For example, the Lloyd-Max quantizer algorithm can be used to find the optimal quantization boundary and reconstructed value through iterative optimization. For nonlinear problems involving floating-point conversion, it may be necessary to preprocess the values ​​by performing logarithmic transformations, or to use vector quantization or neural network optimization. Furthermore, the optimization of the interval boundaries also needs to consider the feasibility of hardware implementation. The boundary values ​​are best chosen as powers of 2 or values ​​with a simple binary pattern, so that the comparator can be implemented more simply. For example, choosing boundary values ​​such as 0x400 or 0x800 can simplify the comparison operation to checking whether a specific bit is set, without requiring a complete numerical comparison.

[0056] For example, in a practical FP4 conversion example, the setting of the index value range may need to consider handling underflow. When the index value is less than a certain minimum threshold, the FP4 output should be zero. The selection of the minimum threshold needs to be calculated based on the smallest positively normalized number that FP4 can represent, taking into account factors such as exponent bias and mantissa precision. For the index value range that just exceeds the underflow threshold, it may be necessary to map it to the denormalized number representation of FP4. These index value ranges are narrow because the dynamic range of denormalized numbers is limited. As the value increases, it enters the normalized number region. The index value range can be divided using a geometric progression because the exponential representation of floating-point numbers makes the values ​​uniformly distributed on a logarithmic scale. Each interval corresponds to a specific exponent value, and changes within the interval are handled through the mantissa. For the overflow case, when the value exceeds the maximum threshold, the maximum representable value of FP4 or infinity is output.

[0057] The specific encoding of numerical representations in the second floating-point format must conform to the FP4 format specification. Assuming the FP4 format is configured with 1 sign bit, 2 exponent bits, and 1 mantissa bit, there are a total of 16 possible encodings. These encodings need to be appropriately allocated to different numerical ranges. The sign bit can be handled separately based on the sign of the input value, or negative and positive numbers can be mapped to symmetrical interval divisions. The exponent bit is used to cover a large range of index values, and the mantissa bit is used to provide limited precision within each exponent interval. For example, an exponent value of 00 might represent a denormalized number or the smallest normalized number, with a narrow range of index values ​​but relatively high precision; an exponent value of 11 might represent the largest normalized number, covering a wide range of index values ​​but with lower precision. In extreme cases, an exponent of all 1s and a non-zero mantissa might represent NaN, and an exponent of all 1s and a zero mantissa might represent infinity.

[0058] The mapping relationship also needs to consider the impact of rounding strategies, because floating-point conversion inevitably introduces quantization errors. The design of the index value range needs to be optimized in conjunction with the rounding direction. Rounding strategies include rounding to even numbers, rounding to the nearest, rounding to zero, rounding up, or rounding down. In the comparator architecture, rounding is achieved by offsetting the interval boundaries. For example, to achieve rounding, the midpoint of each interval can be set as the boundary point. In this way, values ​​falling into the lower half of the interval are rounded down, and values ​​falling into the upper half are rounded up. To achieve rounding to zero, the interval boundaries need to be offset towards zero.

[0059] For handling special numerical values, including zero, infinity, NaN, and denormalized numbers, these values ​​have special semantics in floating-point arithmetic and need to be handled correctly during the conversion process. For zero, a specific index range needs to be set; when the input value is sufficiently close to 0, zero should be output regardless of the rounding mode. For infinity, exponent overflow needs to be detected, and a sufficiently large upper bound threshold needs to be set. For NaN, it's necessary to check whether the input itself is NaN or whether the conversion process generated invalid operations.

[0060] In another embodiment of the floating-point number format conversion device provided in this application, the conversion mapping unit 120 includes a lookup table memory, and the mapping relationship is stored in the lookup table memory in the form of a lookup table.

[0061] For example, the mapping relationship can be achieved by looking up a table, and direct table lookup can be used for various numerical models; it can also be combined with prediction techniques to use the temporal or spatial locality of numerical values ​​to predict the transformation results and reduce comparison operations.

[0062] For example, the conversion mapping unit 120 replaces the traditional iterative calculation logic with a predictive lookup table comparison method. By pre-calculating all cases and storing the results in a highly optimized lookup table, it simplifies complex arithmetic operations into a single, extremely fast address access and data read. Furthermore, it introduces a predictive preprocessing mechanism, using innovative precision compression technology to efficiently compress the 21-bit sticky bits that determine rounding to 1 bit. This significantly reduces the number of logic gates and circuit complexity in the conversion mapping unit 120, directly resulting in a triple advantage of reduced chip area, lower power consumption, and shorter comparison operation latency. In addition, based on these two technologies, the traditional shift value calculation unit is completely eliminated, and the dedicated Round-to-even logic circuit in Norm / Denorm conversion is removed. This not only achieves extreme simplification of the most complex data path in the format conversion hardware unit, significantly reducing chip area and power consumption, but also reduces potential design errors and improves the reliability of the core computing unit.

[0063] In another embodiment of the floating-point format conversion device provided in this application, the conversion mapping unit 120 includes a decision circuit, which includes a plurality of comparators. The bit width of each comparator is the same as the bit width of the index value, and is used to compare the index value with a preset threshold and output the corresponding numerical representation of the second floating-point format.

[0064] In another embodiment of the floating-point number format conversion device provided in this application, multiple comparators are arranged in parallel or in series.

[0065] For example, the index value refers to the floating-point representation with fewer bits obtained after dimensionality reduction processing by the preprocessing unit 110. For instance, an original FP32 floating-point number may contain 1 sign bit, 8 exponent bits, and 23 mantissa bits. After dimensionality reduction processing, it may be compressed into an 11-bit value. The same bit width means that each comparator in the module is designed to receive input data with this specific bit width. If the index value is 11 bits, then each comparator is an 11-bit comparator, and its data input port width is 11 bits.

[0066] Understandably, in digital integrated circuit design, it's desirable for functional modules to use uniform data bit widths and interface standards as much as possible. This simplifies interconnections between modules and reduces layout and routing complexity. If the comparator bit width differs from the index value bit width, additional bit extension or truncation circuitry is required, increasing area and power consumption. For example, if the index value is 11 bits and the comparator is 16 bits, then sign extension or zero extension is needed to fill the 11 bits of data into 16 bits. This extension process requires additional logic gates, increasing circuit complexity. Therefore, comparators with the same bit width as the index value achieve circuit regularity.

[0067] For example, each comparator needs to compare the input index value with a predefined threshold to determine whether the value falls within a specific index range. The threshold itself is also a binary number with the same bit width as the index value. Since the index value and the threshold have the same bit width, the comparator can use standard numerical comparison algorithms, such as ripple carry comparison or parallel prefix comparison. This achieves optimal performance and area efficiency when the bit width is consistent, ensuring the accuracy and integrity of the comparison operation. It is worth noting that although the index value is obtained by dimensionality reduction from the original floating-point number, the numerical order relationship is still maintained. That is, if the original floating-point number A is greater than B, then the corresponding index value A is also greater than B. This order preservation characteristic ensures that the comparison operation performed in the compressed domain can correctly reflect the size relationship of the original floating-point number.

[0068] For example, for an N-bit comparator, a tree structure consisting of N 1-bit comparators can be used. Each 1-bit comparator receives corresponding bits of the two input numbers and generates outputs greater than, equal to, and less than. These outputs are then combined through multi-level logic to produce the overall comparison result. When all comparators use the same bit width, the 1-bit comparator can be standardized, which is beneficial for automatic circuit generation and verification. Furthermore, the comparator array can be implemented using a parallel prefix structure, and an N-bit comparison can be completed in a short time through a preprocessing-propagation-generation network, achieving optimal performance-area ratio. Moreover, since all comparators share the same input bit width, the input interface of the conversion mapping unit 120 can be designed as a simple N-bit wide bus without complex multiplexing or bit width conversion logic. This makes the conversion mapping unit 120 easier to integrate into larger systems and facilitates timing analysis and constraints. During the physical design phase, comparators with the same bit width can be neatly arranged in the chip layout, forming a regular structure. This is beneficial for optimizing interconnect lengths, reducing parasitic parameters, and improving circuit performance. In addition, although the bit width and index value of each comparator are the same, it can support a variety of compression formats with different bit widths. For example, through parameterized design, the same set of RTL code can generate conversion mapping units 120 that support 4-bit, 8-bit, 11-bit or 16-bit index values ​​according to the configuration. The system configuration can be flexibly adjusted for different application scenarios without redesigning the entire module. When it is necessary to support a new floating-point format, it is only necessary to adjust the compression bit width parameters and resynthesize to generate the corresponding hardware circuit.

[0069] For example, the transformation mapping unit 120 can be a specialized classifier that maps input index values ​​to a finite number of numerical representations in a second floating-point format based on the partitioning and matching of index value ranges. The transformation mapping unit 120 can employ architectures such as parallel comparison trees, cascaded comparison chains, or hybrid architectures. Among these, the parallel comparison tree structure is the most direct implementation. All comparators simultaneously receive the input index values, each comparing them with pre-stored thresholds. Then, a priority encoder selects the highest-priority output from all true comparison results, completing the classification decision in a single clock cycle. For example, if the goal is to map index values ​​to eight different output categories, eight parallel comparators are needed, each containing complete numerical comparison logic. A cascaded comparison chain organizes comparators into a pipeline or sequence, where the index value sequentially passes through each comparison stage, comparing it with a threshold at each stage. The final output or progression to the next stage is determined based on the comparison result, resulting in good area efficiency. The hybrid architecture uses coarse-grained parallel comparisons at the top layer to quickly eliminate values ​​that are obviously out of range, and fine-grained cascaded comparisons at the bottom layer for accurate classification. It provides a good balance between speed and area and is suitable for handling unevenly distributed index value ranges.

[0070] Comparators in decision circuits can employ various circuit techniques. The simplest comparator is a numerical comparator, which determines whether the input is less than, equal to, or greater than a fixed threshold. However, in specific applications of floating-point conversion, comparators can support more complex range conditions. For example, a comparator might need to determine whether the input satisfies a composite condition of being greater than or equal to threshold A and less than threshold B. Such a range comparator can be constructed using two numerical comparators and an AND gate. In more complex cases, the comparison conditions may involve multiple discontinuous regions, requiring the use of multi-input comparators or lookup table structures. For certain special boundary conditions, such as the handling of denormalized numbers, the comparator may need to integrate special detection logic to identify all-zero patterns or specific bit sequences.

[0071] For example, the selection of the threshold of the conversion mapping unit 120 directly affects the accuracy and efficiency of the conversion. It can be determined based on statistical analysis of the distribution of input values. For example, in the conversion from FP32 to FP4, the threshold can be set in the region with higher numerical density to provide finer division, while a coarser division is used in the sparse region to save comparator resources. The threshold is fixed as a hardware constant during the design and stored in a register or lookup table. In a configurable system, the threshold may be designed to be programmable, allowing the software to dynamically adjust the conversion characteristics according to application requirements.

[0072] For example, the binary nature of numerical values ​​can be used to optimize the conversion mapping unit 120 to improve performance and efficiency. For instance, when the threshold is a power of 2, the comparison operation can be simplified to bitmasking and bit testing, which is much simpler than a full numerical comparison. When multiple comparators share the same threshold or part of the comparison logic, these circuits can be reused to reduce area. Alternatively, clock gating and operand isolation techniques can be used to activate the corresponding comparator circuits only when needed to reduce dynamic power consumption. The conversion mapping unit 120 needs to work closely with the preceding and following modules. Its input is connected to the compression module, receiving a fixed-width index value; its output generates a second floating-point format encoding. For example, if the goal is to map the input to 16 different FP4 modes, the output encoding is 4 bits wide. The control interface allows external logic to configure the module's operating mode, such as enabling / disabling specific comparators, adjusting power consumption states, etc. In addition, when the input value does not match any predefined range, the conversion mapping unit 120 can output a safe default value or trigger an abnormal signal; for high reliability applications, the comparator can adopt a triple module redundancy design and ensure the correctness of the result through a voting mechanism.

[0073] For example, the conversion mapping unit 120 includes multiple comparators with a bit width equal to the number of bits of the index value. Since the index value is smaller than the number of bits of the input data in the first floating-point format, the comparator bit width of the conversion mapping unit 120 can also be reduced to the same number of bits as the index value, thus eliminating the need for higher-width comparators and further reducing the number of logic gates and circuit complexity. In addition to the core advantages of significantly reducing the number of logic gates and circuit complexity, it also forms a multi-dimensional, multi-layered positive influence network, from the most basic transistor switching characteristics to the overall system-level performance.

[0074] In terms of performance, in digital circuit design, the delay of a comparator exhibits a superlinear relationship with its bit width. This is because most comparators employ parallel prefixes or tree structures. When the bit width is reduced from 32 bits to 11 bits, the theoretical delay reduction is not merely a simple linear proportional relationship, but a logarithmic optimization. Specifically, a 32-bit comparator typically requires 6 logic stages, while an 11-bit comparator only requires 4, reducing the logic depth by 33%. The delay improvement in actual circuit implementation may be even more significant because factors such as wiring delay and fan-out load are easier to optimize with narrower bit widths. Therefore, reducing the comparator bit width directly leads to a substantial reduction in critical path delay. The direct result of this reduced delay is an increase in the module's maximum operating frequency. In synchronous digital systems, the clock frequency is limited by the longest combinational logic path. As part of the critical path, the increased speed of the comparator allows the entire module to operate stably at higher frequencies. For example, a floating-point conversion module originally designed to operate at 1 GHz can achieve an operating frequency of 1.3-1.5 GHz after comparator optimization, resulting in a significant performance improvement.

[0075] Furthermore, in processor architecture, floating-point translation units are organized into multi-stage pipelines to achieve high throughput. The latency of each pipeline stage must be balanced to ensure maximum efficiency. Narrower comparators allow the comparison stage to be better balanced with other processing stages, reducing pipeline bubbles and improving instruction-level parallelism. In some designs, comparison operations that previously required multiple cycles can now be completed in a single cycle, allowing the processor to simplify related control logic, reduce branch prediction error costs, and improve instruction throughput. For superscalar processors, simpler and faster comparators mean that more floating-point translation instructions can be issued in a single cycle, making better use of execution units. In vector processors and GPU architectures, because SIMD / SIMT execution modes require multiple data channels to execute the same operation synchronously, narrow-bit comparators allow for more parallel channels to be implemented within the same area budget, or the same level of parallelism to be achieved in a smaller area. For example, in AI accelerators, halving the comparator bit width allows the number of computational cores to be doubled within the same chip area, or power consumption to be reduced while keeping the number of cores constant. Therefore, reducing the comparator bit width leads to a systemic improvement in the efficiency of the entire processing pipeline.

[0076] Secondly, reducing the comparator bit width requires fewer logic gates, resulting in smaller load capacitance because the gate capacitance and interconnect capacitance of each transistor are reduced accordingly. Furthermore, the simplified circuit has a lower switching activity factor because narrow bit-width data generates fewer glitches and redundant switching during comparison. Finally, reduced latency allows for a lower operating voltage while maintaining the same performance requirements. Since power consumption is proportional to the square of voltage, the impact of voltage reduction on power consumption is exponential. Some measurement data show that reducing a 32-bit comparator to 16 bits can reduce dynamic power consumption by 40%–60%. Combined with voltage and frequency adjustment optimization, the overall energy saving effect can reach over 70%. Furthermore, the combination of reduced power consumption and improved performance results in superior energy efficiency, namely a significant increase in the amount of computation that can be completed per joule of energy. The energy efficiency improvement achieved through comparator optimization has a multiplier effect: on the one hand, the circuit itself consumes less power; on the other hand, due to improved performance, the time required to complete tasks is shortened, allowing the system to enter a low-power state more quickly. In data center scenarios, improved energy efficiency directly translates into reduced operating costs and a smaller carbon footprint. For example, if the floating-point conversion unit accounts for 10% of the power consumption in an AI inference accelerator, and its energy efficiency is improved by 50% through comparator optimization, then the energy efficiency of the entire chip may be improved by 5%. For a hyperscale data center with tens of thousands of chips deployed, this is equivalent to saving millions of kilowatt-hours of electricity and reducing hundreds of tons of carbon dioxide emissions annually.

[0077] Furthermore, narrow bit-width comparator designs significantly improve system robustness because more complex circuits have more potential points of failure and are more sensitive to process variations, voltage fluctuations, and temperature changes. Specifically, reducing the comparator bit width decreases the number of transistors, directly reducing the probability of hard failures; the simplified circuit is less sensitive to soft errors because there are fewer critical state bits and greater timing margins on the critical path. Due to their shorter logic depth and simpler interconnect structure, narrow bit-width circuits are less sensitive to fluctuations in process parameters, exhibiting smaller performance variability and more stable power consumption characteristics, enabling the chip to continue operating normally under extreme conditions.

[0078] For example, in high-performance applications, it may be necessary to sacrifice some accuracy in exchange for simpler comparison logic. For instance, some adjacent intervals can be merged to cover a wider range with the same comparator, which will introduce quantization error but reduce the number of comparators. Alternatively, a hierarchical comparison strategy can be adopted, with the first level being a coarse division and the second level being a fine division, which controls hardware costs while maintaining accuracy.

[0079] For example, the conversion mapping unit 120 implements floating-point format conversion from FP32 to FP4 involving multi-level abstraction, precise numerical mapping, and efficient hardware execution. It is used to compress and map the high-precision floating-point space to an extremely low-precision representation space via a comparator network. The conversion process can be broken down into several key stages, each involving profound theoretical foundations and engineering implementation considerations. First, it is important to understand the significant precision difference between FP32 and FP4. FP32 provides approximately 7 decimal significant digits and a large dynamic range, while FP4 only has 1-2 significant digits and a very limited dynamic range. This huge precision gap inevitably leads to the loss of a large amount of information during the conversion process. Therefore, the conversion strategy must intelligently select which information to retain to minimize the impact on application performance.

[0080] The starting point of the conversion process is understanding the representation structures of the two formats. FP32 follows the IEEE 754 standard, containing 1 sign bit, 8 exponent bits, and 23 mantissa bits. FP4, however, does not have a unified standard. Common configurations may include 1 sign bit, 2 exponent bits, and 1 mantissa bit, or other variations such as 1 sign bit, 3 exponent bits, and 0 mantissa bits. Regardless of the specific configuration, the representable values ​​of FP4 are discrete and finite. The essence of the conversion mapping unit 120 is to select the most suitable FP4 representation for each FP32 input from this finite set of discrete values.

[0081] The first step in the specific implementation can be to preprocess the FP32 value into a form suitable for comparison. This includes extracting the sign bit for separate processing, taking the absolute value of the numerical part to simplify the comparison logic, performing possible numerical scaling or transformations, and generating an index value representation, retaining the key features of the original FP32 value but significantly reducing the number of bits. After obtaining the index values, the mapping process is implemented through a transformation mapping unit 120, which includes multiple comparators. Each comparator is configured with a specific range of index values ​​and a corresponding FP4 output value. The range conditions cover the entire convertible numerical space and can be designed to be mutually exclusive and complete, ensuring that each valid input matches one and only one comparator. The optimized number of comparators is slightly more than the number of values ​​that FP4 can represent because some index value ranges may require special processing.

[0082] For example, the transformation mapping unit 120 can also be verified to verify that all possible FP32 inputs can be correctly mapped to the expected FP4 output. However, since FP32 has a huge number of possible values, exhaustive testing is not practical. Therefore, an intelligent testing strategy is needed to select boundary test cases based on numerical analysis to cover all interval boundaries and special values.

[0083] In another embodiment of the floating-point number format conversion device provided in this application, each comparator has a preset output value threshold, and the decision range of the comparator is obtained by its own output value threshold and the output value thresholds of all preceding comparators.

[0084] Understandably, the output value threshold refers to one or more specific numerical limits preset within each comparator, serving as a reference point for the comparison operation. It is directly used to compare the size with the compressed representation of the input data in the first floating-point format, thereby generating a Boolean output signal indicating whether the input satisfies the specific relationship of interest to the comparator. The decision range, on the other hand, describes the complete set of input values ​​that a comparator is used to process, i.e., the continuous or discrete numerical interval in which the input value falls when the comparator is triggered and outputs the corresponding second floating-point format value. This interval can be defined by the current comparator's own output value threshold and the output value thresholds of all comparators before it. Therefore, the decision range depends on multiple thresholds in the entire comparator sequence.

[0085] For example, the output value threshold defines the dividing point in the input space, pre-calculated based on the representational capability of the second floating-point format and an optimization algorithm that minimizes quantization error, aiming to divide consecutive input values ​​into different categories. The decision range represents the specific region divided by the dividing point, with each region corresponding to a unique target output code, ensuring that the entire input space is completely and non-overlappingly covered, thereby avoiding mapping ambiguity and guaranteeing the determinism of the conversion function. The output value threshold can exist as a hardware constant, such as a reference voltage or digital value stored in a register, lookup table, or directly encoded in the comparator circuit, which does not change with the input and is statically configured. The decision range is rarely explicitly stored, but is implicitly implemented through the interconnection logic and priority rules between comparators. For example, in a cascaded comparator architecture, the threshold T1 of the first comparator defines that it is triggered when the input value is less than or equal to T1, while the second comparator is only triggered when the input value is greater than T1 and less than or equal to its own threshold T2. Therefore, its decision range is dynamically generated through hardware interconnects, enable signals, or logic gates.

[0086] Setting the output threshold primarily focuses on the accuracy and sensitivity of a single comparator, including the numerical accuracy of the threshold itself, robustness to process variations, and comparison speed. The design requires a trade-off between the number and location of thresholds. The decision range, on the other hand, prioritizes system-level integrity, ensuring that all possible input values ​​are covered by a certain range, with seamless transitions between ranges without gaps or overlaps. Therefore, global optimization of the threshold sequence is required, taking into account the statistical distribution of input values. Furthermore, errors in the output threshold can directly cause misjudgments at individual comparison points, potentially leading to incorrect classification of input values ​​into adjacent intervals. Deviations in the decision range affect the mapping accuracy of the entire interval, potentially causing increased systematic quantization errors or local distortions. Moreover, the output threshold affects the switching activity and delay of each comparator unit. For example, higher threshold accuracy may require more transistors or more complex comparator circuitry, increasing power consumption and comparison time. The decision range influences the topology and operation sequence of the entire comparator network. For instance, cascaded structures save area but introduce linear delays, parallel structures reduce delay but increase power consumption and area, while tree structures represent a trade-off between delay and hardware overhead.

[0087] For example, output value thresholds can be verified individually through scan tests or parameter tests; decision ranges, however, require integration tests and boundary value tests to verify the correctness of the boundaries of all ranges and whether there are conflicts or omissions between ranges, requiring more complex test vectors and functional simulations. Output value thresholds can be designed to be programmable, allowing software updates to the thresholds to adapt to different conversion modes or rounding strategies; decision ranges will automatically change with threshold adjustments, but may require re-verification of the correctness of the entire range division.

[0088] For example, the output value threshold can be represented as a threshold set T = {t1, t2, ..., tn}, where each threshold ti corresponds to a comparator; the decision range can be represented as an interval set I = {I1, I2, ..., Im}, where each interval Ii is a function of the threshold set T, for example, Ii = (t_{i-1}, t_i], and assuming t0 = -∞, t_m = +∞.

[0089] For example, the decision range of a comparator can be derived from its own output value threshold and the output value thresholds of all preceding comparators. This can be based on the linear order of the priority chain, where comparators are arranged in order of their output value thresholds. The input value passes through each comparator sequentially, first being compared with the threshold T1 of the first comparator. If the input is less than or equal to T1, the first comparator is triggered and outputs the corresponding value, and the process terminates. Otherwise, the input is passed to the second comparator and compared with the threshold T2, and so on. Thus, the decision range of the i-th comparator is actually the interval defined by the thresholds of the preceding i-1 comparators and its own threshold, specifically (T_{i-1}, T_i], where T_{i-1} is the threshold of the preceding comparator. This method is simple to implement in hardware, requiring only the concatenation of comparators and some control logic. However, the disadvantage is that the latency increases linearly with the number of comparators.

[0090] Another option is a tree-structured binary derivation, where comparators are organized into a binary tree, with each internal node corresponding to an output value threshold. The input is compared starting from the root node, and the left or right subtree is selected based on the comparison result until a leaf node is reached. Each leaf node corresponds to an output value, and its decision range is determined by all threshold conditions along the path from the root to the leaf. For example, if the path requires the input to be less than T1 and greater than or equal to T2, then the range is [T2, T1). The latency of this method increases logarithmically with the number of comparators, making it suitable for high-performance scenarios with a large number of comparators. However, the hardware structure is more complex, requiring a balanced tree layout and more interconnections.

[0091] Another option is to combine parallel comparison with priority encoding. All comparators simultaneously compare the input with their respective output threshold values. Each comparator generates a Boolean signal indicating whether the input meets its condition. These Boolean signals are then fed into a priority encoder. The encoder selects the highest priority true signal and outputs the target value of the corresponding comparator. In this case, the decision range of each comparator is implicit in the priority rule: for the i-th comparator, its signal will only be selected if the input is greater than the threshold of all higher priority comparators (i.e., the threshold of the first i-1 comparators) and less than or equal to its own threshold. This method has constant latency, depending only on the latency of the comparators and encoder, and is suitable for high-speed applications. However, it requires additional logic to ensure correct priority and has higher power consumption because all comparators work simultaneously.

[0092] Another option is implicit derivation based on a lookup table, where the input value is directly used as an address index to a pre-computed lookup table that stores the corresponding output value. The decision range is embedded in the contents of the lookup table, eliminating the need for explicit derivation. This method is extremely fast and simple to design, but the size of the lookup table grows exponentially with the input bit width. For wide-bit inputs, compression techniques or hierarchical lookups are required. For example, precision compression can be used to reduce the input bit width and then index a smaller lookup table.

[0093] Another option is to use a state machine based on programmable logic or microcode, where the output value threshold is stored in a configurable register. A state machine or microcode controller performs comparison operations sequentially, and jumps to the corresponding state to output the corresponding value based on the comparison result. The decision range is defined by the conditional branch logic in the microcode. This approach is very flexible and the threshold and range can be easily adjusted.

[0094] Other options include using analog circuits or mixed-signal techniques, such as using a resistor divider network to generate multiple threshold voltages. The input voltage is then compared with these thresholds simultaneously by multiple comparators, and the range conditions are combined using analog multiplexers or digital logic. This approach is suitable for low-precision or specific sensor applications, but the accuracy is limited by the analog circuitry.

[0095] Other options include convolution or template matching based on digital signal processing, which treats the input as a signal and the threshold condition as a template, finding the matching interval through related operations, but this is too complicated for floating-point conversion.

[0096] Another option is to draw on machine learning classifiers, treating the comparator network as a simple decision tree or neural network, and determining the threshold and range through training, which is suitable for adaptive systems.

[0097] Another option is to model the behavior in a hardware description language, using consecutive if-else or case statements to describe range conditions, and have the comparator network automatically generated by a synthesis tool. This approach relies on tool optimization and may result in unpredictable hardware architectures.

[0098] Other options include hybrid architectures that combine multiple inference methods to balance performance. For example, the first level uses parallel comparisons to quickly narrow down the range, while the second level uses linear search for exact matching or uses hierarchical lookup tables.

[0099] For example, the specific choice of method needs to take into account factors such as conversion accuracy, latency requirements, power consumption budget, chip area, configurability, and process constraints. For instance, for FP32 to FP4 conversion, since the input bit width is small after compression, parallel comparison and priority encoding may be the most advantageous because the conversion can be completed in a single cycle and the hardware overhead is controllable. However, for higher precision conversion or resource-constrained embedded systems, priority chains or tree structures may be more suitable.

[0100] In another embodiment of the floating-point number format conversion apparatus provided in this application, the decision range of the comparator includes its own output value threshold and the output value inverse threshold which is opposite to the output value threshold of all preceding comparators.

[0101] Understandably, the comparator's decision range includes its own output value threshold and the output value inverse threshold that is opposite to the output value thresholds of all preceding comparators. This combination of its own positive condition and the inverse condition of the preceding stage ensures that the entire comparator array achieves mutual exclusion and complete classification.

[0102] In a system that maps a continuous input space to discrete output values, each valid input must be assigned to one and only one output class; there can be no blank regions or conflicting regions. For example, consider a series of comparators C1, C2, ..., Cn arranged in ascending order of thresholds, with thresholds T1, T2, ..., Tn respectively. If the trigger condition for comparator Ci is that the input X satisfies X <= Ti, then for inputs less than T1, all comparators will satisfy X <= Ti, leading to multiple comparators triggering simultaneously; however, for inputs greater than Tn, none of the comparators satisfy X <= Ti, resulting in no comparators triggering. Therefore, simple one-sided conditions cannot constitute an effective classifier. Introducing the preceding inverse condition, X > T_{i-1} (for C1, T_{i-1} can be considered negative infinity), limits the actual effective range of Ci to (T_{i-1}, Ti). Thus, the range of C1 is (-∞, T1], the range of C2 is (T1, T2], ..., the range of Cn is (T_{n-1}, Tn], and the last implicit interval (Tn, +∞) may require a default or overflow handling unit. This divides the real number line into n+1 non-overlapping and continuously covering intervals. The inverse condition is implemented by allowing the current comparator to take effect only when the output of the preceding comparator is not greater than a certain value, forming the logical basis for an enable chain or priority encoding.

[0103] Understandably, in digital circuits, if multiple output units might simultaneously respond to the same input event, bus contention or output conflicts can occur, leading to unpredictable results or even circuit damage. By mandating that each comparator's activation depends not only on its own judgment of the input (positive condition) but also on waiting for all higher-priority comparators to relinquish ownership of that input (negative condition), an implicit priority arbitration protocol is established through the negative condition. For example, in a parallel comparator architecture, all comparators operate simultaneously, but the outputs of all comparisons are fed into a priority encoder. The encoder works by only accepting the output of comparator number i when all outputs of comparators with smaller numbers are false (i.e., their positive condition is not satisfied, equivalent to their negative condition being true), which is equivalent to the logical expression: Output_i = (X <= Ti) AND NOT(X <= T_{i-1}) AND ... AND NOT(X <= T1). In the cascaded architecture, the input X is only passed to Ci for comparison when it is greater than the threshold T_{i-1} of the previous stage; if X <= T_{i-1}, the process is terminated at the previous stage to eliminate the possibility that any two comparators will output valid results at the same time, ensuring that there is only one valid second floating-point format code on the output bus at any given time.

[0104] From a logical expression perspective, the complete enable condition of a comparator is the logical AND of its own positive condition with the negative conditions of all preceding stages. At the transistor level, while implementing a multi-input AND gate is feasible, direct implementation linearly increases fan-in and logic depth with increasing comparator index i, thus increasing delay and area. However, this structure can be optimized. For example, in dynamic logic, a domino chain can be designed, where the non-triggered signal of the preceding comparator serves as the enable signal for pre-charging or evaluation of the current comparator. In static CMOS design, conditional activation can be achieved by using the output of the preceding comparator as the power-gated or clock-gated signal for the current comparator, significantly reducing both static and dynamic power consumption. This is because a comparator and its subsequent logic are only fully powered or timed when the input actually falls within its potential range; otherwise, they are in a low-power sleep state. Furthermore, due to the existence of inverse thresholds, many comparators are inactive in most situations, allowing for higher-performance but also higher-power circuit designs without concern for overall power consumption runaway.

[0105] For example, the comparator's decision range includes its own output value threshold and the inverse threshold setting of the output value that is opposite to the output value thresholds of all preceding comparators. This supports scalable and modular hardware design, allowing the number of comparators to be added or removed like building blocks without redesigning the global control logic. Each comparator module requires only three interfaces: an input data bus, a matched or enabled signal from the preceding module, and a pass signal to the following module and its own matching result. This modularity is extremely beneficial for generating parameterized hardware IP cores; the same RTL code can easily generate comparator arrays supporting any number of thresholds N by configuring parameters. Simultaneously, it simplifies physical layout and routing; comparators can be arranged in priority order as a line or an array, with a simple and clear signal flow, which helps reduce wiring congestion, line delay, and improve timing predictability.

[0106] For example, in floating-point format conversion, the rounding mode (rounding to the nearest even number) determines the specific location of the interval boundary. The interval boundary can be the exact midpoint between two adjacent representable values. The threshold of the comparator is set at these midpoints. Then, the decision range (T_{i-1}, Ti] corresponds exactly to the rule of rounding to the value V_i, where V_i is the representable value to the left of Ti. If the input is equal to the boundary Ti (i.e., the exact midpoint), according to the RNT rule, it is necessary to look at even numbers, which may require additional logic. However, in this embodiment, the boundary case can be absorbed by setting the value of Ti (making its corresponding V_i even) or adding a small offset, thereby supporting complex rounding while keeping the main architecture unchanged.

[0107] For example, the comparator decision range can also include enhancement, protection, and optimization clauses to meet the functional, performance, and reliability requirements of actual chips in complex operating environments. For instance, the comparator decision range can also include explicit handling conditions for outliers and special cases. Floating-point systems contain special encodings such as denormalized numbers, infinity, and NaN. The comparison semantics of these special encodings differ from those of normalized numbers. For example, comparing any number with NaN results in an unordered result, and NaN itself needs to be mapped to a specific representation in a second floating-point format or trigger an exception. Therefore, a preprocessing logic unit is placed before the comparator's range condition. This unit detects whether the input is a special value; if so, it directly bypasses the entire threshold comparison network and outputs a preset special result. This can be seen as adding a higher-priority special value range condition on top of the core threshold interval division, with a higher priority than all conventional comparators. The comparator decision range can also include dynamic offset conditions introduced by considering the configurability of the rounding mode. In some cases, the threshold Ti is statically set by default based on a certain rounding mode. However, in processors that support multiple rounding modes, the threshold may need to be dynamically adjusted according to the current rounding mode. Therefore, the range condition of each comparator actually becomes (T_{i-1} + Δ_{i-1}(RM), T_i + Δ_i(RM)], where Δ is a small offset that depends on the rounding mode RM. These offsets can be introduced by additional adders or lookup tables, or by multiplexing to select different groups of pre-stored thresholds, making the range condition dynamically configurable instead of static.

[0108] The comparator decision range can also include compensation conditions for process, voltage, and temperature variations. This is because, at advanced process nodes, transistor parameters in the comparator can drift due to manufacturing process fluctuations, operating voltage fluctuations, and junction temperature changes, causing the actual comparison threshold to deviate from the design value. To ensure correct functionality even in the worst-case scenario, an allowable deviation window for each threshold can be determined during simulation, and a safety margin can be introduced into the range conditions. Alternatively, a more complex adaptive calibration circuit can be used to measure the actual topping point of the critical comparator when the chip is powered on or idle, and adjust the reference voltage or current through digital logic to bring the threshold back to its nominal value. This effectively incorporates the calibration coefficient into the calculation of the range conditions.

[0109] For example, in a cascaded comparison chain, if the prediction mechanism can know in advance that the input cannot be less than a certain intermediate threshold T_k, then the first k comparators can be skipped directly, and the comparison can start from the (k+1)th comparator. This is equivalent to dynamically modifying the set of inverse conditions of each comparator at runtime, changing it from all the previous levels to a portion of the previous levels.

[0110] For example, an output value may correspond to multiple discontinuous intervals in the input space. For instance, in order to bypass a region that is prone to numerical instability, the range condition of a single comparator cannot be simply represented as a continuous interval, but should be the union of multiple continuous intervals. This can be achieved by having a comparator logic contain multiple sub-comparators and performing an OR operation on their outputs, or by using a programmable interval descriptor lookup table.

[0111] In another embodiment of the floating-point format conversion device provided in this application, a plurality of comparators include an exception decision unit 210 and a quantization mapping unit 220; the output value threshold of the exception decision unit 210 includes a minimum value condition when the input data is in a second floating-point format and an infinite value condition when the input data is in a first floating-point format, and the output value threshold of the quantization mapping unit 220 includes a quantization output value condition when the input data is in a second floating-point format.

[0112] Understandably, the exception decision unit 210 is used to handle boundary exceptions during the conversion process, i.e., the input value exceeds the range that the second floating-point format can normally represent, including underflow and overflow. Underflow occurs when the absolute value of the input data in the first floating-point format is less than the smallest positive normalized number (or smallest positive value) that the second floating-point format can represent. For such tiny values, the second floating-point format can usually only approximate them with extremely low precision using a denormalized number, or simply clear them to zero. Overflow occurs when the absolute value of the input data in the first floating-point format is greater than the maximum finite value that the second floating-point format can represent. In this case, the second floating-point format can only output its maximum representable value or a special value of infinity. The logic required to handle these two cases is detection and truncation, and the decision-making basis is several key maximum / minimum thresholds determined by the limits of the second floating-point format. The quantization mapping unit 220 is used to process numerical mapping within the normal range, that is, when the input value falls within the dynamic range of the second floating-point format. In this case, it is necessary to select the most suitable value from the finite set of discrete representable values ​​in the second floating-point format as the conversion result. Essentially, this is a quantization or rounding process, and the decision is based on a series of quantization thresholds calculated based on rounding rules. Since these two types of operations solve very different problems, rely on different thresholds, and have completely different output behaviors, they are placed in different hardware modules, making each module functionally pure, with clear interfaces, and easy to design and verify.

[0113] Understandably, the exception decision unit 210 needs to judge a very small number of conditions. For a format that supports both positive and negative numbers, only two comparators or one comparator with signed processing are needed to determine if there is an underflow, and two to determine if there is an overflow. The thresholds for these comparisons are fixed extreme values ​​defined by the format. The comparison logic can be designed to be extremely concise and fast. For example, to determine if an unsigned number is less than the minimum positive normalized number, it may only be necessary to check if its exponent is below a certain fixed value, which can be completed with very few logic gates and a very short delay. Since the out-of-limit situation is a low-probability event in actual computation, the circuit of this exception path can be deeply optimized into a small and fast bypass circuit. The quantization mapping unit 220 needs to handle the high-probability normal situation. The number of comparators is equal to the number of valid values ​​that the second floating-point format can represent minus one or more. For example, mapping the input to 16 FP4 values ​​may require 15 or more comparators to form a comparison network. The circuit of this normal path is the main body.

[0114] Understandably, in a unified but unclassified comparator network, the threshold conditions and output values ​​of each comparator must simultaneously consider normal and abnormal semantics. This makes the definition of the threshold set, the ordering of comparator priorities, and the allocation of output codes exceptionally complex and error-prone. For example, how to ensure that the overflow threshold is greater than all internal quantization thresholds, and how to handle an input that is exactly equal to the overflow threshold. By separating the over-limit handling, the quantization mapping unit 220 network can safely assume that its input always falls within the effective dynamic range of the second floating-point format. Thus, it only needs to focus on solving a well-defined quantization problem, and its threshold set can be strictly generated and ordered within the interval without worrying about boundary conflicts. At the same time, the exception decision unit 210, acting as a guard or watchdog circuit, intercepts data and assigns it a special output before it flows into the core quantization module. It filters out exceptions first and then processes the normal pipeline or logic flow, making the design specifications of both simpler and more rigorous, and the interfaces between modules clear and unambiguous.

[0115] It is understandable that the exception decision unit 210 and the quantization mapping unit 220 are not completely independent parallel modules, but can be organized into a priority-ordered decision pipeline or hierarchical network. For example, the input index value is first sent to the exception decision unit 210 group. If it is detected as underflow, the module directly outputs zero or the smallest denormalized number in the second floating-point format; if it is detected as overflow, it directly outputs the maximum value or infinity in the second floating-point format. Only values ​​that pass the over-limit check are allowed or enabled to flow into the quantization mapping unit 220 array for fine quantization mapping. This correlation is manifested in the hardware as the output signal of the exception decision unit 210 serving as the enable or selection signal for the quantization mapping unit 220 array. For example, a non-underflow and non-overflow global signal may be used to control the clock gating, power gating, or as one of the control terminals of its output multiplexer.

[0116] For example, since the anomaly decision unit 210 is typically designed to be extremely fast, its decision result can be generated as early as possible. This early-generated out-of-limit flag can be used for speculative execution. For instance, while the anomaly decision unit 210 is working, the quantization mapping unit 220 array can also be pre-started for computation. Once the anomaly decision unit 210 determines the result, if it is found that the input is indeed out of limit, the computation being performed by the quantization mapping unit 220 array is immediately canceled or discarded, and the output of the out-of-limit path is adopted. Although this may waste some power, it avoids the increased critical path delay caused by waiting for the out-of-limit decision result under normal circumstances, thereby achieving better overall performance.

[0117] For example, the overall control logic of the conversion mapping unit 120 needs to coordinate the behavior of the two types of comparators, including data flow control, error recovery, debugging support, performance monitoring, etc. For instance, when a large number of consecutive overflow events are detected, the control logic may record a performance counter event or trigger an interrupt notification software. This logic needs to monitor the output of the two types of comparators simultaneously. In configurable rounding mode, the threshold of the quantization mapping unit 220 may need to be adjusted, while the threshold of the exception decision unit 210 is fixed. The control logic needs to ensure that the two do not conflict when the configuration is updated.

[0118] For example, the minimum condition for input data in a second floating-point format is defined as a key threshold in the numerical space of the second floating-point format. This threshold is used to determine whether the input value in the first floating-point format is too low to be represented with normal precision in the second floating-point format, thereby triggering the underflow handling mechanism. Specifically, the minimum value can be set to the smallest positively normalized number that the second floating-point format can represent. If the second floating-point format supports denormalized numbers, it may be extended to the smallest positively denormalized number. For example, when the second floating-point format is FP4 with a common configuration of 1 sign bit, 2 exponent bits, 1 mantissa bit, and an exponent bias of 1, the exponent bit corresponding to the smallest positive normalized number is 0 or 1. For a 2-bit exponent, the bias is usually 1, so the exponent range is -2 to 1. The exponent bit 00 corresponds to the denormalized number and zero, 01 corresponds to an exponent of -1, 10 corresponds to an exponent of 0, and 11 corresponds to an exponent of 1 or a special value. Following this, the exponent of the smallest positive normalized number should be -1, and the mantissa should be at least 0, with a value of 1.0 × 2^(-1) = 0.5. However, in practice, the configuration of FP4 may vary and needs to be adjusted according to the specific definition. In any case, the minimum value condition is manifested in the hardware as a specific numerical threshold T_min. When the absolute value of the input data in the first floating-point format is less than T_min, it is considered to have underflowed. In the round-to-nearest even rounding mode, for a positive input, if its absolute value is less than half of the minimum positive normalized number, it may be rounded directly to zero; if it is between half and the minimum positive normalized number, it may be rounded to the minimum positive normalized number. Therefore, the minimum value condition can be represented in the hardware circuit as one or more comparators, with the threshold set to the rounded value. For example, T_min / 2 is used to determine whether to clear to zero, and T_min is used to determine whether to use the minimum representation value.

[0119] For example, the infinity condition for input data in a first floating-point format is defined as a threshold in the first floating-point format's numerical space. This threshold determines whether the input value exceeds the maximum finite value that the second floating-point format can represent, thus triggering overflow processing. For instance, if the maximum finite value of the second floating-point format FP4 is M_max, then when processing FP32 input, the infinity condition is to determine whether the input is greater than M_max. However, due to the existence of rounding modes, the overflow threshold may actually need to be adjusted. In the round-to-nearest even-number mode, the overflow threshold is typically set to the midpoint between the maximum finite value M_max of the second floating-point format and the next possible value (if it exists); if the second floating-point format does not support larger values, the overflow threshold may be set to M_max plus a small increment determined by the rounding rules. Specifically, if the maximum finite value of the second floating-point format corresponds to the code C_max, then the overflow threshold T_max may be set to the midpoint between C_max and the adjacent code (if any), or if C_max is the maximum code, then T_max = M_max + (M_max - M_prev) / 2, where M_prev is the second largest finite value; for example, if the maximum finite value of FP4 is 3.0 and the second largest finite value is 2.0, then T_max = 3.0 + (3.0-2.0) / 2 = 3.5. However, in practice, because FP4 representation values ​​are sparse and the intervals may be uneven, it needs to be calculated according to the specific value. The infinity condition also involves sign handling; for negative numbers, it is necessary to determine whether it is less than -M_max to trigger negative overflow. Furthermore, if the second floating-point format supports infinity, two thresholds may be set: one for saturation to a maximum finite value and the other for outputting infinity. The circuit implementation for the infinity condition includes a comparator, and the reference threshold T_max may be pre-calculated and stored as a floating-point number in the first floating-point format for direct comparison; or, to save area, it can be approximated by analyzing the exponent and mantissa of the input data. For example, if the input exponent is greater than the exponent of the maximum value in the second floating-point format, then it is definitely overflowing; if the exponents are equal, then the mantissa is compared.

[0120] For example, when the input data is in a second floating-point format, the quantization output value condition is a set of thresholds in the array of quantization mapping units 220, used to map the input within the normal range to discrete representable values ​​in the second floating-point format. For example, if the positive representable values ​​of the second floating-point format FP4 are v0, v1, ..., vk from smallest to largest, then for each i from 1 to k, the threshold t_i = (v_{i-1} + v_i) / 2, so the interval (-∞, t1] corresponds to v0, (t1, t2] corresponds to v1, ..., (tk, +∞) corresponds to vk. However, in practice, (-∞, t1] and (tk, +∞) are different values. +∞) is handled by the exception decision unit 210. Therefore, the quantization output value conditions are the set of these t_i. For the denormalized number region, the midpoint calculation needs to be precise because the intervals may be uneven. These thresholds can be pre-calculated and stored in a lookup table or register file. Each threshold corresponds to a comparator. When the input arrives, all comparators work in parallel, comparing the input with their respective thresholds, and then generating the output code through priority encoding or direct logic. In addition, since the number of second floating-point format values ​​is limited, the number of quantization output value conditions is also limited. For example, FP4 has 16 codes, and positive and negative symmetry may only require 7 thresholds, making the size of the comparator array controllable.

[0121] In another embodiment of the floating-point format conversion apparatus provided in this application, the numerical representation of the second floating-point format includes the maximum value when the input data is in the second floating-point format.

[0122] Understandably, the infinity condition is a category recognition or special value detection mechanism. It doesn't concern itself with the numerical value itself, but rather checks whether the input data is already infinity or NaN as defined by the IEEE 754 standard. Its judgment logic is fixed and based on bit patterns, simple, and can be completed within a very short combinational logic path, with the result having the highest priority. The second floating-point format maximum condition, on the other hand, is a decision range comparison. It deals with ordinary finite input values, determining whether a finite value exceeds the maximum finite value that the second floating-point format can represent. This requires comparing an FP32 value with an FP32 threshold representing the maximum finite value of FP4, a standard arithmetic comparison operation. It is more complex than simple bit pattern matching, involving a comprehensive judgment of the exponent and mantissa.

[0123] Based on this, an over-limit comparator can be set in the first stage of the decision circuit to perform fast classification and absolute anomaly removal, filtering out inputs that take special processing paths with the lowest latency and highest determinism. This creates a clean working environment for the quantization mapping unit 220 in the second stage, containing only finite ordinary values. This ensures that even for the most complex inputs, the latency of identification and redirection to special processing paths is minimized, preventing huge delays and logical confusion caused by backtracking after anomalies are detected in subsequent complex comparison networks. Furthermore, if the input is identified as infinity or NaN in the first stage, the quantization mapping unit 220 and its related logic in the second stage can be immediately gated off or disabled, avoiding useless high-power parallel comparison operations and thus significantly saving dynamic power consumption. In addition, the logic in the second stage can be based on the assumption that the input is a finite non-zero ordinary floating-point number, thereby removing a large number of boundary cases, simplifying the circuit design, verification, and formal proof of the second stage, greatly reducing the risk of design errors and improving the intrinsic reliability of the module.

[0124] After the input value is confirmed as a finite normal value in the first stage, it enters the quantization mapping unit 220 of the second stage of the conversion mapping unit 120. The problem then becomes finding the most suitable discrete representation for the current input within the continuous closed interval from the smallest positive normalized number to the largest finite value that can be expressed in the second floating-point format. Therefore, the comparator for the maximum value in the quantization mapping unit 220 of the second stage of the conversion mapping unit 120 when the input data is in the second floating-point format is an internal threshold used to divide the two highest quantization levels within this finite continuous interval. It is placed in the second stage because this comparator and all other thresholds used to distinguish the various code values ​​within the second floating-point format are identical in nature—they are numerical comparison thresholds. Placing them uniformly in an array of multiple comparators allows for a regularized hardware design, such as a parallel comparison tree or a priority coding network. Furthermore, the comparison of the maximum value when the input data is in the second floating-point format presupposes that the input has been confirmed as a finite value. If the input is infinite, the comparison is mathematically undefined and circuitically meaningless. Therefore, the comparison of the maximum value when the input data is in the second floating-point format must be based on the logical premise that the judgment result of the first stage is not infinite.

[0125] In another embodiment of the floating-point number format conversion device provided in this application, multiple comparators are arranged in series.

[0126] In another embodiment of the floating-point number format conversion apparatus provided in this application, when multiple comparators are connected in series, the preceding comparator is used to pass the index value or a decision intermediate signal to the following comparator when the index value does not fall within its decision range.

[0127] In another embodiment of the floating-point number format conversion device provided in this application, each comparator includes an input terminal, a first output terminal and a second output terminal, and multiple comparators are connected in sequence;

[0128] Between two adjacent comparators, the second output of the previous comparator is connected to the input of the next comparator. If the index value of the previous comparator does not meet its own output value threshold, the previous comparator inputs the index value into the next comparator through its second output. If the index value of the next comparator meets its own output value threshold, the next comparator outputs the corresponding second floating-point format numerical representation through its first output.

[0129] refer to Figure 3 , Figure 3 This is a schematic diagram of a floating-point format conversion device provided in another embodiment of this application. The decision circuit of the conversion mapping unit 120 includes multiple comparators with a bit width equal to the number of bits of the index value. Each comparator includes an input terminal, a first output terminal, and a second output terminal, and the multiple comparators are connected in sequence. Since the multiple comparators are connected in sequence, the input terminal of the first comparator is used to receive the original index value. Each subsequent comparator only receives the index value transmitted by the previous comparator through its input terminal if the index value does not meet the decision range of the previous comparator. The first output terminal of each comparator is used to output the corresponding numerical representation of the second floating-point format when the index value meets the decision range. Here, since each comparator includes an output value threshold, the decision range of the comparator includes its own output value threshold and an output value inverse threshold that is opposite to the output value thresholds of all preceding comparators. Therefore, the decision range of the first comparator includes its own output value threshold, the decision range of the second comparator includes its own output value threshold and the inverse threshold of the first comparator's output value threshold, the decision range of the third comparator includes its own output value threshold, the inverse threshold of the second comparator's output value threshold and the inverse threshold of the first comparator's output value threshold, and so on.

[0130] It is important to note that among the multiple comparators in the transformation mapping unit 120, the second comparator, located after the first comparator, only uses its own output value threshold for comparison when comparing index values. Furthermore, it can be assumed that the index value satisfies both the output value threshold of the second comparator following the first and the decision range of the second comparator. This is because the index value is only input to the second comparator if it does not satisfy the first comparator's own output value threshold. Since the first comparator's own output value threshold is essentially a decision range, when the index value does not satisfy the first comparator's own output value threshold, it naturally satisfies the inverse output value threshold opposite to the first comparator's output value threshold. In other words, when the index value enters the second comparator, the second comparator's decision range includes its own output value threshold and the inverse output value threshold opposite to the first comparator's output value threshold. However, since the index value already satisfies the inverse output value threshold opposite to the first comparator's output value threshold, it is only necessary to compare the index value with the second comparator's own output value threshold. And as long as the index value satisfies the second comparator's own output value threshold, it can be considered that the index value satisfies the second comparator's decision range.

[0131] Similarly, for any comparator after the first comparator, the index value can be compared using only its own output value threshold. As long as the index value meets the output value threshold of any comparator, the index value can be considered to meet the judgment range of that comparator.

[0132] It is worth noting that in some cases, if fewer comparators are used to further reduce chip area, resulting in more intervals for the second floating-point format numerical representation than the number of comparators, multiple output value thresholds can be set in the last comparator or any of the comparators to correspond to multiple intervals for the second floating-point format numerical representation. Alternatively, a single output value threshold can be used to correspond to multiple intervals for the second floating-point format numerical representation. For example, if the number of intervals for the second floating-point format numerical representation is greater than the number of comparators, one output value threshold of the last comparator can correspond to two intervals for the second floating-point format numerical representation. If the index value meets the output value threshold of the last comparator itself, one interval for the second floating-point format numerical representation is used to output one second floating-point format numerical representation. If the index value does not meet the output value threshold of the last comparator itself, another interval for the second floating-point format numerical representation is used to output another second floating-point format numerical representation. Since the last comparator is the last in the sequence, it does not need to input the index value to the next comparator through the second output terminal. Therefore, the case where the index value does not meet the output value threshold of the last comparator itself can be used to set an additional interval for the second floating-point format numerical representation.

[0133] For example, taking the conversion of input fp32 to fp4 as an example, the preprocessing unit 110 analyzes the 21 sticky bits of the input fp32 floating-point number, thereby compressing the 21 sticky bits of the input fp32 floating-point number to one bit. Specifically, the preprocessing unit 110 can decompose the input fp32 floating-point number, extract the sign bit, obtain a 31-bit floating-point number, and analyze the lower 20 bits of the 31-bit floating-point number, that is, determine whether the lower 20 bits of the 31-bit floating-point number are all 0. If the lower 20 bits of the 31-bit floating-point number are all 0, the compressed sticky bit 0 is obtained; if the lower 20 bits of the 31-bit floating-point number are all 0, the compressed sticky bit 1 is obtained. Then, the 31-bit floating-point number is right-shifted by 20 bits to obtain an 11-bit floating-point number, and the compressed sticky bit is ORed to the least significant bit of the 11-bit floating-point number to obtain the final index value.

[0134] Next, the 11-bit index value enters the first comparator of the conversion mapping unit 120. Here, the fp4 value output by the conversion mapping unit 120 needs to be added with the sign bit extracted by the preprocessing unit 110. The conversion mapping unit 120 can have eight comparators. Among them, the first and second comparators can be exception decision units 210. The first and second comparators can be minimum value condition comparators when the input data is in the second floating-point format, and infinity value condition comparators when the input data is in the first floating-point format, respectively. That is, the output value threshold of the first comparator includes the minimum value of the input data when the input data is fp4. The first comparator determines that the value of the input data is equal to the input data. In the case of the minimum value when the input data is fp4, the output is 0 plus the sign bit extracted by the preprocessing unit 110. If the first comparator determines that the value of the input data is not equal to the minimum value when the input data is fp4, the index value enters the second comparator. The output threshold of the second comparator includes the value of the input data being greater than the infinity value when the input data is fp32. If the second comparator determines that the value of the floating-point number is greater than the infinity value when the input data is fp32, the output is 7 plus the sign bit extracted by the preprocessing unit 110. If the second comparator determines that the value of the floating-point number is not greater than the infinity value when the input data is fp32, the index value enters the third comparator. It can be understood that since the first and second comparators are used to determine whether the input data represents two completely different extreme cases, the order of the first and second comparators can be interchanged.

[0135] The third to eighth comparators of the conversion mapping unit 120 are all quantization mapping units 220, used to determine various cases when the input data is in the second floating-point format. Here, the output value thresholds of the third to eighth comparators of the conversion mapping unit 120 can be boundary values ​​of the numerical representation in the second floating-point format. Since the minimum value condition comparators in the first and second comparators have already determined the minimum value boundary when the input data is in the second floating-point format, the output value thresholds of the third to eighth comparators can be interval boundary values, including the maximum value boundary, when all cases of the numerical representation in the second floating-point format are divided into multiple numerical representation intervals in the second floating-point format, except for the minimum value boundary.

[0136] Understandably, the core task of the anomaly detection unit 210 is rapid classification and absolute anomaly removal. The design goal of the anomaly detection unit 210 is to filter out inputs that must undergo special processing with the lowest latency and highest determinism, creating a clean working environment for the second-stage quantization mapping unit 220 array containing only finite ordinary values. The minimum conditional comparator for input data in the second floating-point format and the infinity conditional comparator for input data in the first floating-point format are both used for anomaly detection. Therefore, these two comparators are used as the anomaly detection unit 210 and are arranged at the very beginning. Therefore, since the judgment logic for special values ​​is simple and fixed, it can be done very quickly. Placing these two comparators in the first stage ensures that even for the most complex input, the delay in its recognition and redirection to the special processing path is minimized, preventing huge delays and logical confusion caused by backtracking after discovering anomalies in subsequent complex comparison networks. Furthermore, when the anomaly judgment unit 210 in the first stage identifies the input as a special value such as infinity or NaN, the quantization mapping unit 220 and its related logic in the second stage can be immediately gated off or disabled, avoiding useless high-power parallel comparison operations, thereby significantly saving dynamic power consumption.

[0137] The boundaries of the multiple second floating-point format numerical representation intervals divided by fp4 include minimum value boundaries, maximum value boundaries, first value boundaries, second value boundaries, third value boundaries, fourth value boundaries, fifth value boundaries, and sixth value boundaries. In addition, the minimum value boundary and the first value boundary form the first target output value interval, the first value boundary and the second value boundary form the second target output value interval, the second value boundary and the third value boundary form the third target output value interval, the third value boundary and the fourth value boundary form the fourth target output value interval, the fourth value boundary and the fifth value boundary form the fifth target output value interval, the fifth value boundary and the sixth value boundary form the sixth target output value interval, and the sixth value boundary and the maximum value boundary form the seventh target output value interval. Each target output value interval corresponds to the second floating-point format numerical representation of the input data in that interval.

[0138] Based on this, the comparators corresponding to the minimum value conditions in the first and second comparators are used to determine whether the input data is the minimum value when it is in the second floating-point format. That is, if the input data is greater than the minimum value when it is in the second floating-point format, the comparator determines a minimum boundary. The decision range of subsequent comparators all include the case where the input data is greater than the minimum value when it is in the second floating-point format.

[0139] Subsequently, the third comparator can be a comparator corresponding to the maximum boundary. In this way, the range of subsequent comparators is determined by the comparators corresponding to the maximum boundary and the comparators corresponding to the minimum boundary, so that the subsequent comparators can determine their own range, i.e. the decision range, by their own output value thresholds that represent the range boundaries.

[0140] Therefore, the fourth comparator can be a comparator corresponding to the first value boundary, that is, the output value threshold of the fourth comparator is less than the first value boundary when the index value is fp4. In this way, through the comparator corresponding to the minimum value boundary and the fourth comparator, the first target output value interval can be corresponded, and then when the index value is less than the first value boundary when it is fp4, the numerical representation of the second floating-point format corresponding to the first target output value interval is output. The fifth comparator can be a comparator corresponding to the second value boundary, that is, the output value threshold of the fifth comparator is less than the second value boundary when the index value is fp4. In this way, through the fourth comparator corresponding to the first value boundary and the fifth comparator corresponding to the second value boundary, the second target output value interval can be corresponded, and then when the index value is less than the second value boundary when it is fp4, the numerical representation of the second floating-point format corresponding to the second target output value interval is output. And so on, to achieve coverage of all target output value intervals, and thus achieve the format conversion from fp32 to fp4 through eight comparators.

[0141] In another embodiment of the floating-point number format conversion device provided in this application, multiple comparators are arranged in parallel.

[0142] In another embodiment of the floating-point number format conversion device provided in this application, each comparator includes an input terminal and an output terminal, and the input terminal of each comparator is connected to the preprocessing unit 110;

[0143] Between two adjacent comparators, the output of the previous comparator and the output of the next comparator are connected through an OR gate 310. When the index value does not meet its own decision range, the previous comparator outputs the first inverse condition information through its output terminal. When the index value meets its own decision range, the next comparator outputs the positive condition information through its output terminal, and when the index value does not meet its own decision range, it outputs the second inverse condition information.

[0144] OR gate 310 outputs the numerical representation of the second floating-point format corresponding to the next comparator when it obtains the first inverse condition information and the positive condition information, and outputs the first inverse condition information and the second inverse condition information to the next OR gate 310 when it obtains the first inverse condition information and the second inverse condition information.

[0145] refer to Figure 4 , Figure 4 This is a schematic diagram of a floating-point number format conversion device provided in another embodiment of this application. The conversion mapping unit 120 includes multiple comparators with the same bit width as the index value. Each comparator includes an input terminal and an output terminal. The input terminal of each comparator is connected to the preprocessing unit 110, meaning that multiple comparators are arranged in parallel for parallel comparison. In addition, between two adjacent comparators, the output terminal of the previous comparator is connected to the output terminal of the next comparator through an OR gate 310. Therefore, the input terminals of multiple comparators are arranged in parallel for parallel comparison, but the output terminals of multiple comparators are still connected sequentially. The output terminal of the first comparator is connected to the output terminal of the second comparator through an OR gate 310, the output terminal of the second comparator is connected to the output terminal of the third comparator through an OR gate 310, and so on. It should be noted that the output of the first comparator may include a first output and a second output. The first output of the first comparator is used to output the numerical representation of the second floating-point format corresponding to the first comparator when the index value meets the decision range of the first comparator. The second output of the first comparator is connected to the output of the second comparator. The second output of the first comparator is used to output the first inverse condition information when the index value does not meet the decision range of the first comparator.

[0146] Understandably, the first inverse condition information can indicate that the index value between two adjacent comparators does not meet the decision range of the previous comparator, and OR gate 310 determines that the first inverse condition information is false. The positive condition information can indicate that the index value between two adjacent comparators meets the decision range of the next comparator, and OR gate 310 determines that the positive condition information is true. The second inverse condition information can indicate that the index value between two adjacent comparators does not meet the decision range of the next comparator, and OR gate 310 determines that the second inverse condition information is false.

[0147] Therefore, for the next comparator to output the corresponding second floating-point format numerical representation, the index value must satisfy the decision range of the next comparator. This is because the next comparator needs to output the corresponding second floating-point format numerical representation through OR gate 310. OR gate 310 needs two inputs: positive condition information from the next comparator and first negative condition information from the previous comparator. Since OR gate 310 determines that the first negative condition information is false, only when the index value satisfies the decision range of the next comparator can the next comparator output positive condition information to OR gate 310, thus enabling OR gate 310 to output the corresponding second floating-point format numerical representation.

[0148] Furthermore, regarding two adjacent comparators, taking the first and second comparators as an example, the decision range of the second comparator includes not only its own decision range but also the decision ranges of all comparators preceding it. This is because OR gate 310 requires input from the first inverse condition information. Once OR gate 310 obtains the first inverse condition information, it indicates that the index value does not satisfy the decision range of the first comparator. Since the decision range can be considered a condition for whether a value falls within a numerical range, and each comparator has a different decision range, if the index value does not satisfy the decision range of the first comparator, it will satisfy the decision ranges of other comparators, including the second comparator. Therefore, the decision range of the second comparator includes not only its own decision range but also the decision ranges of all comparators preceding it.

[0149] It is worth noting that in some cases, if fewer comparators are set to further reduce chip area, resulting in more numerical representation intervals in the second floating-point format than the number of comparators, multiple decision ranges can be set in the last comparator or any comparator to correspond to multiple numerical representation intervals in the second floating-point format, or a single decision range can be used to correspond to multiple numerical representation intervals in the second floating-point format. For example, if the number of numerical representation intervals in the second floating-point format is more than the number of comparators, one decision range of the last comparator can correspond to two numerical representation intervals in the second floating-point format. If the index value satisfies the decision range of the last comparator itself, one numerical representation interval in the second floating-point format is used to output one numerical representation in the second floating-point format. If the index value does not satisfy the decision range of the last comparator itself, another numerical representation interval in the second floating-point format is used to output another numerical representation in the second floating-point format. Since the last comparator is the last in the order and does not need to be connected to the next comparator through OR gate 310, an additional numerical representation interval in the second floating-point format can be set by taking advantage of the situation where the index value does not satisfy the decision range of the last comparator itself.

[0150] For example, taking the conversion of input fp32 to fp4 as an example, the preprocessing unit 110 analyzes the 21 sticky bits of the input fp32 floating-point number, thereby compressing the 21 sticky bits of the input fp32 floating-point number to one bit. Specifically, the preprocessing unit 110 can decompose the input fp32 floating-point number, extract the sign bit, obtain a 31-bit floating-point number, and analyze the lower 20 bits of the 31-bit floating-point number, that is, determine whether the lower 20 bits of the 31-bit floating-point number are all 0. If the lower 20 bits of the 31-bit floating-point number are all 0, the compressed sticky bit 0 is obtained; if the lower 20 bits of the 31-bit floating-point number are all 0, the compressed sticky bit 1 is obtained. Then, the 31-bit floating-point number is right-shifted by 20 bits to obtain an 11-bit floating-point number, and the compressed sticky bit is replaced in the least significant bit of the 11-bit floating-point number to obtain the final index value.

[0151] Next, the 11-bit index value simultaneously enters the eight comparators of the conversion mapping unit 120. Here, the fp4 value output by the conversion mapping unit 120 needs to be added with the sign bit extracted by the preprocessing unit 110. The first and second comparators can be exception decision units 210. The first and second comparators can be a minimum value condition comparator for input data in the second floating-point format and an infinity value condition comparator for input data in the first floating-point format, respectively. That is, the decision range of the first comparator includes the minimum value of the input data when the input data is fp4. If the first comparator determines that the value of the input data is equal to the minimum value when the input data is fp4, it outputs 0 and adds the sign bit extracted by the preprocessing unit 110. If the first comparator determines that the value of the input data is not equal to the minimum value when the input data is fp4, it indicates that the value of the input data is not equal to the minimum value when the input data is fp4. The first inverse condition information is input to the OR gate 310 between the first and second comparators. The decision range of the second comparator includes the value of the input data being greater than the infinity value when the input data is fp32. If the second comparator determines that the value of the input data is greater than the infinity value when the input data is fp32, it outputs positive condition information indicating that the value of the input data is greater than the infinity value when the input data is fp32. The OR gate 310 outputs 7 and adds the sign bit extracted by the preprocessing unit 110 after passing the first inverse condition information output by the first comparator and the positive condition information output by the second comparator. If the second comparator determines that the value of the input data is not greater than the infinity value when the input data is fp32, it outputs the first inverse condition information indicating that the value of the input data is not greater than the infinity value when the input data is fp32 to the next OR gate 310, because the next OR gate 310 is connected to the output of the second comparator and the output of the third comparator. It can be understood that since the first and second comparators are used to determine whether the input data is two completely different extreme cases, the order of the first and second comparators can be interchanged.

[0152] The third to eighth comparators of the conversion mapping unit 120 are all quantization mapping units 220, used to determine various cases when the input data is in the second floating-point format. Here, the decision range of the third to eighth comparators of the conversion mapping unit 120 can be the boundary value of the numerical representation in the second floating-point format. Since the minimum value condition comparators in the first and second comparators have already determined the minimum value boundary when the input data is in the second floating-point format, the decision range of the third to eighth comparators can be the interval boundary value when all cases of the numerical representation in the second floating-point format are divided into multiple numerical representation intervals in the second floating-point format, except for the minimum value boundary, including the maximum value boundary.

[0153] Understandably, the core task of the anomaly detection unit 210 is rapid classification and absolute anomaly removal. The design goal of the anomaly detection unit 210 is to filter out inputs that must undergo special processing with the lowest latency and highest determinism, creating a clean working environment for the second-stage quantization mapping unit 220 array containing only finite ordinary values. The minimum conditional comparator for input data in the second floating-point format and the infinity conditional comparator for input data in the first floating-point format are both used for anomaly detection. Therefore, these two comparators are used as the anomaly detection unit 210 and are arranged at the very beginning. Therefore, since the judgment logic for special values ​​is simple and fixed, it can be done very quickly. Placing these two comparators in the first stage ensures that even for the most complex input, the delay in its recognition and redirection to the special processing path is minimized, preventing the huge delay and logical confusion caused by backtracking after discovering anomalies in subsequent complex comparison networks. Furthermore, when the anomaly judgment unit 210 in the first stage identifies the input as a special value such as infinity or NaN, the quantization mapping unit 220 in the second stage and its related logic can be immediately gated off or disabled, avoiding useless high-power parallel comparison operations, thereby significantly saving dynamic power consumption.

[0154] The boundaries of the multiple second floating-point format numerical representation intervals divided by fp4 include minimum value boundaries, maximum value boundaries, first value boundaries, second value boundaries, third value boundaries, fourth value boundaries, fifth value boundaries, and sixth value boundaries. In addition, the minimum value boundary and the first value boundary form the first target output value interval, the first value boundary and the second value boundary form the second target output value interval, the second value boundary and the third value boundary form the third target output value interval, the third value boundary and the fourth value boundary form the fourth target output value interval, the fourth value boundary and the fifth value boundary form the fifth target output value interval, the fifth value boundary and the sixth value boundary form the sixth target output value interval, and the sixth value boundary and the maximum value boundary form the seventh target output value interval. Each target output value interval corresponds to the second floating-point format numerical representation of the input data in that interval.

[0155] Based on this, the comparators corresponding to the minimum value conditions in the first and second comparators are used to determine whether the input data is the minimum value when it is in the second floating-point format. That is, the comparator determines that the input data is greater than the minimum value when it is in the second floating-point format. The comparator determines a minimum boundary, and the decision range of subsequent comparators all include the case where the input data is greater than the minimum value when it is in the second floating-point format.

[0156] Subsequently, the third comparator can be a comparator corresponding to the maximum boundary. In this way, the range of subsequent comparators is determined by the comparators corresponding to the maximum boundary and the comparators corresponding to the minimum boundary, so that subsequent comparators can determine their own range, i.e., the decision range, through their own range boundaries.

[0157] Therefore, the fourth comparator can be the comparator corresponding to the first value boundary. That is, the decision range of the fourth comparator is when the index value is less than the first value boundary. In fact, the decision range of the fourth comparator is when the index value is less than the first value boundary and greater than the minimum value and less than the maximum value, and when the index value is greater than infinity, and when the index value is fp32. Thus, through the comparator corresponding to the minimum value boundary and the fourth comparator, the first target output value interval can be identified. Then, when the index value is less than the first value boundary, the numerical representation of the second floating-point format corresponding to the first target output value interval is output. The fifth comparator can be the comparator corresponding to the second value boundary, that is, the fifth comparator... The decision range of the comparator is less than the second value boundary when the index value is fp4. In fact, the decision range of the fifth comparator is less than the second value boundary and greater than the minimum value and less than the maximum value when the index value is fp4, and greater than the infinity value when the index value is fp32. Thus, by using the fourth comparator corresponding to the first value boundary and the fifth comparator corresponding to the second value boundary, the second target output value interval can be identified. Then, when the index value is less than the second value boundary when the index value is fp4, the numerical representation of the second floating-point format corresponding to the second target output value interval is output. This process is repeated to cover all target output value intervals, thereby achieving the format conversion from fp32 to fp4 through eight comparators.

[0158] In another embodiment of the floating-point number format conversion apparatus provided in this application, the preprocessing unit 110 compresses multiple sticky bits used for rounding judgment in the low-order bits of the mantissa of the input data to generate an index value.

[0159] In another embodiment of the floating-point number format conversion device provided in this application, the preprocessing unit 110 compresses multiple sticky bits into a single sticky judgment bit.

[0160] For example, the preprocessing unit 110 can perform bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate corresponding index values. Here, the preprocessing unit 110 can adopt a sticky bit analysis method based on bit-field segmentation and dynamic compression to transform the original sticky bit vector into a more compact representation through intelligent segmentation and dynamic compression mechanisms, thereby reducing the burden on subsequent processing modules. Specifically, a detailed bit-field analysis can be performed on the sticky bits of the first floating-point format input data to identify key information regions. For example, in the conversion from FP32 to FP4, sticky bits may include multiple bits that jointly indicate the precision loss during the rounding process. The preprocessing unit 110 can divide these sticky bits into multiple segments, each segment corresponding to a different precision loss level or influence range. The basis for segmentation may include the distribution pattern of sticky bits, the statistical characteristics of historical conversion data, and the precision requirements of the second floating-point format, so as to extract the main features of sticky bits through segmentation. For example, high-order sticky bits are used to indicate significant precision loss and low-order sticky bits are used to indicate slight precision loss, thereby providing a basis for subsequent compression.

[0161] The preprocessing unit 110 can use a dynamic compression algorithm to map the segmented sticky bit information to fewer bits. Dynamic compression can employ lossless compression techniques such as Huffman coding or arithmetic coding, assigning shorter codewords to common patterns and longer codewords to rare patterns based on the frequency of sticky bit segments. For example, if certain sticky bit patterns frequently appear in historical data, they can be assigned a short binary code, while less common patterns can be assigned a longer code. In this way, the original multi-bit sticky bit vector is converted into a variable-length compressed code. However, to fix the output bit length, a fixed-bit digest representation can be further used, for example, by mapping the compressed code to a predefined bit length using a hash function. Furthermore, dynamic compression can be combined with a machine learning model to train a lightweight neural network to predict the influence of sticky bits on the final rounding decision and output a scalar value or a short vector as the dimensionality-reduced sticky bit representation. This not only reduces the number of sticky bits but also preserves key information, ensuring efficient processing in the subsequent transformation and mapping unit 120.

[0162] Furthermore, the preprocessing unit 110 needs to consider hardware resource limitations and real-time requirements. For example, in embedded systems, a lookup table can be used to store common sticky bit patterns and their corresponding compression codes, thereby avoiding complex real-time calculations. The size of the lookup table can be adjusted according to the precision of the second floating-point format. For example, for FP4 conversion, a lookup table with 16 entries can be sufficient to cover most sticky bit patterns, with each entry corresponding to a 4-bit compression code, thus reducing the original sticky bits to 4 bits. Simultaneously, an adaptive mechanism can be introduced to adjust the segmentation and compression strategies based on the dynamic changes in the input data. For example, if the sticky bits of multiple consecutive first floating-point format input data show similar patterns, the compression process can be temporarily simplified to further improve processing speed. Thus, based on bit-field segmentation and dynamic compression, through intelligent analysis and compression, the number of sticky bits is significantly reduced, improving the overall efficiency and scalability of the conversion device, while maintaining conversion precision as much as possible, making it suitable for high-throughput floating-point processing scenarios.

[0163] For example, the preprocessing unit 110 can employ a sticky bit analysis method based on statistical feature extraction and scalar quantization to extract key features from the statistical attributes of the sticky bits and transform these features into a low-dimensional representation using quantization techniques, effectively reducing the number of sticky bits in the first floating-point format input data. Specifically, statistical analysis can be performed on the sticky bit vector to calculate basic statistics such as mean, variance, peak value, and skewness. For instance, the sticky bits of an FP32 floating-point number can consist of multiple bits, each representing the precision loss of the mantissa during rounding. By calculating the mean of these bits, an overall precision loss index can be obtained, while the variance reflects the degree of fluctuation in precision loss. Peak value and skewness can indicate the concentration and symmetry of the sticky bit distribution. These statistics together constitute the high-level features of the sticky bits, capturing the core information in the original multi-bit vector, thus laying the foundation for dimensionality reduction.

[0164] After feature extraction, the preprocessing unit 110 can use scalar quantization to map continuous or high-precision statistical features to discrete low-bit representations. Scalar quantization is achieved by dividing feature values ​​into predefined intervals and assigning a unique codeword to each interval. For example, when extracting the mean and variance of sticky bits, each feature originally required multiple bits to represent. Through quantization, the mean can be divided into four intervals (no loss, low loss, medium loss, and high loss) and represented by a 2-bit code; similarly, the variance can be divided into four intervals and also represented by a 2-bit code. In this way, the original multi-bit sticky bit vector is transformed into a 4-bit quantization code (2 bits for the mean and 2 bits for the variance). The boundaries of the quantization intervals can be optimized based on historical data or theoretical analysis to minimize information loss. For example, during the training phase, a large amount of sticky bit data from floating-point samples can be used to calibrate the quantizer to ensure that common patterns are accurately captured. Non-uniform quantization strategies can also be used to set denser intervals in regions where feature values ​​change drastically to further improve the accuracy of the representation.

[0165] To ensure the validity of the dimensionality-reduced sticky bit representation in the subsequent transformation mapping unit 120, the preprocessing unit 110 can use a fusion mechanism to merge multiple statistical features into a compact scalar or short vector. For example, dimensionality reduction techniques such as principal component analysis (PCA) or linear discriminant analysis (LDA) can be used to project the extracted statistical features into a low-dimensional space. When the original sticky bit has 20 bits, 5 statistical features are calculated first, then compressed to 2 principal components through PCA, and finally each principal component is quantized to 3 bits to obtain a 6-bit final representation. This not only reduces the number of bits but also preserves statistical significance, enabling the transformation mapping unit 120 to make rounding decisions quickly based on these features.

[0166] The preprocessing unit 110 can implement a viscous bit analysis method based on statistical feature extraction and scalar quantization through a dedicated statistical computing unit and quantization logic circuit. The statistical computing unit processes the viscous bit vector in parallel, while the quantization logic uses a comparator and encoder to generate output codes. Simultaneously, it can integrate adaptive learning functionality to adjust quantization parameters based on real-time feedback to adapt to changes in different application scenarios. Thus, by focusing on the statistical essence of viscous bits, this method based on statistical feature extraction and scalar quantization achieves efficient bit reduction while balancing processing speed and accuracy.

[0167] For example, the preprocessing unit 110 can employ a sticky bit analysis method based on pattern recognition and entropy coding. By identifying repetitive or common patterns in the sticky bit vector and using entropy coding technology to compress these patterns into a compact representation, the number of sticky bits in the first floating-point format input data can be significantly reduced. Specifically, pattern analysis can be performed on the sticky bits, detecting typical sequences through sliding windows or clustering algorithms. For instance, in the FP32 to FP4 conversion, the sticky bit can be a 23-bit vector representing the precision loss of the mantissa. The preprocessing unit 110 matches these vectors with a predefined pattern library, which can be constructed based on historical data or theoretical models, including all zeros (no loss), high-order bits concentrated at one (high loss), low-order bits scattered at one (low loss), etc. Each pattern corresponds to a unique identifier, represented by fewer bits. If the sticky bit vector matches a pattern in the library, the identifier of that pattern is directly output, thereby reducing the number of bits.

[0168] For sticky bit vectors that do not match any predefined patterns, entropy coding can be used as a backup. Entropy coding is a lossless compression technique that assigns variable-length codes based on the frequency of symbol occurrence. This involves decomposing the sticky bit vector into multiple segments, for example, four 5-bit segments, with the last segment padded if it is less than 5 bits. Each segment is then encoded independently. The encoding table can be generated based on training data, ensuring that common segments receive short codes and rare segments receive long codes. To output a fixed-length result, truncation or merging strategies can be employed, such as retaining only the first N bits after encoding, or using a digest function to map the variable-length code to a fixed-length result. Furthermore, context modeling can be incorporated to optimize the current encoding based on the sticky bit pattern of the previous floating-point number, further improving the compression ratio. For example, if consecutive inputs show similar sticky bits, a more efficient context-dependent encoding table can be used to reduce redundant information.

[0169] The preprocessing unit 110 needs to balance the accuracy of pattern recognition and the efficiency of coding. Pattern recognition can be implemented through a parallel comparator array, quickly comparing the input sticky bits with entries in the pattern library; entropy coding can be performed through a lookup table or dedicated logic circuitry. To handle real-time data streams, a pipelined architecture can be adopted, where pattern recognition and entropy coding are performed in parallel. Finally, a selector outputs a dimension-reduced sticky bit representation, for example, an 8-bit code, where the high-order bits indicate whether pattern matching is used, and the low-order bits store the specific identifier or coded data. Simultaneously, an online learning mechanism can be integrated to dynamically update the pattern library and coding table to adapt to changes in the input data distribution. For example, if a new common sticky bit pattern is detected, it can be added to the pattern library, and the coding strategy can be adjusted. This not only effectively reduces the number of sticky bits but also maintains high fidelity, ensuring that the subsequent conversion mapping unit 120 can make reliable decisions based on compressed information.

[0170] For example, the preprocessing unit 110 is used to receive the raw floating-point input, extract key information, and perform in-depth analysis of the sticky bits to provide optimized data for subsequent format conversion and rounding operations. Specifically, refer to... Figure 2 , Figure 2 This is a schematic block diagram of a floating-point number format conversion device provided in another embodiment of this application. The preprocessing unit 110 can be a multi-stage pipeline structure, including multiple sub-modules, each for a different processing task. First, the input end of the preprocessing unit 110 includes a data interface for receiving floating-point data from the previous processing unit or memory. The interface supports multiple floating-point formats, including FP32, FP16, or BF16, and can process batch data streams to improve throughput. After the data enters the preprocessing unit 110, the first sub-module is a parsing unit, which decomposes the floating-point number into three parts: sign bit, exponent bit, and mantissa bit. The parsing unit can adopt a parallel processing method, capable of processing multiple floating-point numbers simultaneously.

[0171] The parsed data enters the sticky bit analysis unit, which extracts sticky bit information from the mantissa and performs preliminary processing. Sticky bits are low-precision information generated during floating-point operations or conversions. They can be discarded during rounding operations, but also include important precision loss information. The analysis unit can determine the range of sticky bits; for example, sticky bits can include the lower 16 bits of the mantissa. The analysis unit calculates various characteristics of these bits, such as the number of non-zero bits, the length of consecutive zero bits, and the complexity of the bit pattern. This is implemented using dedicated logic circuits, such as using a population counting circuit to count the number of non-zero bits and a leading zero detection circuit to analyze the characteristics of the bit pattern. Furthermore, the analysis unit may also include a pattern matching engine to identify common sticky bit patterns. The pattern matching engine is implemented based on content-addressable memory and can quickly match the input sticky bit pattern with pre-stored templates.

[0172] Following the sticky bit analysis unit, the data enters the feature extraction unit, which extracts higher-level features from the sticky bits for subsequent dimensionality reduction. Feature extraction can include statistical feature calculations, such as calculating the mean, variance, and entropy of the sticky bits; it also includes structural feature analysis, such as detecting whether the sticky bits contain a specific bit pattern sequence. To calculate the entropy of the sticky bits, the unit first needs to calculate the probability distribution of each bit value, and then perform logarithmic and summation operations. This can be achieved using a lookup table to reduce hardware costs.

[0173] Finally, the preprocessing unit 110 may also include control logic and configuration registers. The control logic coordinates the timing of operation of each submodule, handles data dependencies, and manages the interface between the module and external systems. The configuration registers control the software to dynamically adjust the behavior of the modules, including setting the analysis range of sticky bits, selecting feature extraction algorithms, and enabling or disabling certain optimization functions. The preprocessing unit 110 may also include debugging and performance monitoring circuitry for verifying the correctness of functions and evaluating performance metrics during the development phase.

[0174] Understandably, the preprocessing unit 110, by specifically analyzing and reducing the sticky bits, can significantly accelerate computation and greatly increase throughput. Since the preprocessing unit 110 does not need to process the complete 8-bit exponent and 23-bit mantissa, but only focuses on the analysis and reduction of sticky bits, the data processing path is greatly shortened, and the critical path latency is significantly reduced. In hardware design, the critical path determines the highest clock frequency at which the entire system can operate. By simplifying the processing logic and reducing the number of combinational logic stages, signals can pass through the data processing pipeline faster, thus allowing for higher clock frequencies or lower clock-to-output latency at the same frequency. In deep learning accelerators, floating-point format conversion is a critical step in the model inference pipeline, and its processing speed directly affects the overall inference latency. Optimizing this step through the preprocessing unit 110 can significantly improve end-to-end processing performance, making real-time artificial intelligence applications possible.

[0175] Understandably, the simplified design of the preprocessing unit 110 reduces dynamic power consumption. Dynamic power consumption is proportional to the switching activity rate of the circuit, the load capacitance, and the square of the voltage. By reducing the number of bits to be processed and simplifying the logic circuit, the switching activity rate on the data path is significantly reduced, as is the load capacitance that needs to be charged and discharged. Specifically, processing a complete 31-bit floating-point number requires a large number of logic gate state transitions, while processing only the reduced sticky bits significantly reduces the level switching activity on the data path, thereby directly reducing dynamic power consumption. In addition, due to the simplification of the processing logic, the silicon area required by the module is correspondingly reduced, resulting in a reduction in parasitic capacitance, further reducing power consumption. In terms of static power consumption, the simplified circuit requires fewer transistors, the leakage current path is reduced, static power consumption is reduced, and the increased processing speed allows the circuit to complete the task faster and enter a low-power state, further improving energy efficiency.

[0176] Understandably, in traditional floating-point processing units, supporting conversions to different precision formats requires designing different data paths and processing logic. However, the preprocessing unit 110, based on sticky bit analysis and dimensionality reduction, provides a more unified and flexible processing paradigm. By adjusting the analysis range and dimensionality reduction strategy of the sticky bits, the same hardware architecture can adapt to various floating-point format conversion needs with different precisions. For example, the conversion from FP32 to FP16 and from FP32 to BF16 can share the same basic processing framework; only the processing parameters of the sticky bits need to be adjusted. This enables the creation of a more adaptable computing platform to better meet diverse application requirements. Furthermore, hardware uniformity simplifies the support of programming models and toolchains. Compiler optimizations and runtime libraries can be optimized based on consistent hardware characteristics without needing to consider each format conversion separately.

[0177] One embodiment of this application provides a floating-point number format conversion method. This method can be applied to a floating-point number format conversion apparatus, which includes a preprocessing unit 110 and a conversion mapping unit 120 coupled to the preprocessing unit 110. The conversion mapping unit 120 stores multiple mapping relationships between index value ranges and numerical representations in a second floating-point format. Figure 5 As shown, Figure 5 This is a flowchart of a floating-point number format conversion method provided in one embodiment of this application; the floating-point number format conversion method may include, but is not limited to, steps S110 and S120.

[0178] Step S110: The preprocessing unit receives input data in the first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate the corresponding index value.

[0179] Step S120: The conversion mapping unit looks up the corresponding numerical representation in the second floating-point format based on the index value as the output data;

[0180] In this case, the bit width of the index value is smaller than the bit width of the mantissa of the input data, and the bit width of the mantissa in the second floating-point format is smaller than the bit width of the mantissa in the first floating-point format.

[0181] Based on the floating-point number format conversion methods of the above embodiments, the following presents various embodiments of the computer-readable storage medium and computer program product of this application.

[0182] One embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for performing the above-described floating-point number format conversion method. Exemplarily, the above-described method is executed... Figure 5 The methods and steps in the text.

[0183] It is worth noting that, since the computer-readable storage medium of this application embodiment can execute the floating-point number format conversion method of any of the above embodiments, and the floating-point number format conversion method can be applied to the floating-point number format conversion device, the specific implementation method and technical effects of the computer-readable storage medium of this application embodiment can be referred to the specific implementation method and technical effects of the floating-point number format conversion device of any of the above embodiments.

[0184] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the aforementioned floating-point number format conversion method. Exemplarily, the above-described method is performed... Figure 5 The methods and steps in the text.

[0185] It is worth noting that, since the computer program product of this application embodiment can execute the floating-point number format conversion method of any of the above embodiments, the floating-point number format conversion method can be applied to the floating-point number format conversion device. The specific implementation method and technical effect of the computer program product of this application embodiment can refer to the specific implementation method and technical effect of the floating-point number format conversion device of any of the above embodiments.

[0186] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which may include computer storage media or non-transitory media and communication media or transient media. As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc DVD or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0187] In the several embodiments provided in this application, it should be understood that the disclosed systems, instruments, and methods can be implemented in other ways. For example, the instrument embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between instruments or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0188] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0189] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A floating-point number format conversion device, characterized in that, include: A preprocessing unit is configured to receive input data in a first floating-point format and perform bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate a corresponding index value, wherein the bit width of the index value is smaller than the bit width of the mantissa of the input data; the preprocessing unit generates the index value by compressing multiple sticky bits used for rounding judgment in the low-order bits of the mantissa of the input data into a single sticky judgment bit. A conversion mapping unit is coupled to the preprocessing unit. The conversion mapping unit stores multiple index value ranges and numerical representations in a second floating-point format, and is used to find the corresponding numerical representation in the second floating-point format as output data based on the index value. The mantissa width of the second floating-point format is smaller than that of the first floating-point format.

2. The apparatus according to claim 1, characterized in that, The conversion mapping unit includes a lookup table memory, and the mapping relationship is stored in the lookup table memory in the form of a lookup table.

3. The apparatus according to claim 1, characterized in that, The conversion mapping unit includes a decision circuit, which includes multiple comparators. The bit width of each comparator is the same as the bit width of the index value. The comparators are used to compare the index value with a preset threshold and output the corresponding numerical representation in the second floating-point format.

4. The apparatus according to claim 3, characterized in that, The multiple comparators are configured in parallel or in series.

5. The apparatus according to claim 4, characterized in that, In the case of multiple comparators connected in series, the preceding comparator is used to pass the index value or a decision intermediate signal to the following comparator when the index value does not fall within its decision range.

6. The apparatus according to claim 1, characterized in that, The preprocessing unit generates the index value by extracting the sign information, exponent adjustment information, and partial mantissa information of the input data.

7. A floating-point number format conversion method, characterized in that, An application to a floating-point number format conversion device, the floating-point number format conversion device including a preprocessing unit and a conversion mapping unit coupled to the preprocessing unit, the conversion mapping unit storing a mapping relationship between multiple index value ranges and numerical representations of a second floating-point format; The method includes: The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect the rounding operation to generate corresponding index values. The conversion mapping unit looks up the corresponding numerical representation in the second floating-point format based on the index value as the output data; Wherein, the bit width of the index value is smaller than the bit width of the mantissa of the input data, and the bit width of the mantissa of the second floating-point format is smaller than the bit width of the mantissa of the first floating-point format; the preprocessing unit generates the index value by compressing multiple sticky bits used for rounding judgment in the low-order mantissa of the input data into a single sticky judgment bit.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the floating-point number format conversion method as described in claim 7.

9. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, causing the computer device to perform the floating-point number format conversion method as described in claim 7.

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