Parameter determination hardware system and method for storage application chip, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a parameter determination hardware system and method for a storage application chip, a storage medium and electronic equipment, and relates to the field of servers, and the system comprises a server host which is used for sending video data to the storage application chip; the storage application chip is used for determining parameters of the storage application chip, performing parameter adjustment on the storage application chip according to the determined parameters, and processing the video data into compressed video data after parameter adjustment; the storage hard disk is used for receiving the compressed video data; the storage application chip comprises a video graphic array module, a video compression module, a system bus, a processor, a storage controller and a frequency determination module; the video compression module comprises a storage array depth determination module; by means of the system, parameters such as the processor frequency of the storage application chip, the system bus frequency and the storage array depth of the video compression module can be determined.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of server technology, and more specifically, to a hardware system, method, storage medium and electronic device for determining parameters of a storage application chip. Background Art

[0002] Storage application chips are becoming more and more important in modern electronic devices. They are not only responsible for data storage, but also generally integrate video processing functions. This integrated video processing function is usually implemented by SoC (System on a Chip) chips. In terms of video processing functions, storage application chips can perform a series of complex operations. These operations include color space conversion of original RGB format video data, generation of YUV format video data, generation of data blocks, compression processing, and storage and transmission of compressed data. These operations involve a lot of data processing and resource consumption.

[0003] In the process of video processing, the storage application chip usually compresses the video data in frames. Before the video data of the current frame is compressed, the video data of the subsequent frames are not allowed to enter the video compression module. The data in the video processing channel is continuously generated. In order to avoid data loss in the process of video data processing, in the traditional solution, the front-end module of the video compression module, that is, the data block generation module, caches the continuously input video data. Because it is impossible to accurately predict the storage capacity required for the data block generation module to cache the data, a large-depth storage array is usually set inside the data block generation module of the storage application chip. Setting a large-depth storage array will lead to a large amount of on-chip storage resource consumption for general storage application chips, which not only increases the area of ​​the chip, but also increases the production and manufacturing cost of the chip. At the same time, setting a large-depth storage array will also bring great difficulties to the integration and packaging of the back-end of the storage application chip, thereby reducing the yield rate of the chip.

[0004] Secondly, in the traditional chip design process, the CPU (Central Processing Unit) frequency and system bus frequency of the storage application chip are often set based on the experience of engineers, and lack precise guidance schemes, so it is impossible to accurately determine the best combination of the CPU frequency and system bus frequency of the storage application chip. If the CPU frequency and system bus frequency of the storage application chip are set too high, it is necessary to increase the production process requirements to meet the design requirements, which not only increases the chip production cost, but also greatly increases the chip power consumption; if the CPU frequency and system bus frequency of the storage application chip are set too low, it may not meet the chip application requirements, resulting in chip design failure. In addition, the CPU frequency and system bus frequency of the storage application chip may also lead to a waste of the CPU and system bus performance of the storage application chip under unreasonable frequency combinations. Therefore, in the related art, there is a problem of how to accurately determine the parameters of the storage application chip.

[0005] In the related art, there is no effective solution to the problem of how to accurately determine the parameters of the storage application chip. Summary of the invention

[0006] The embodiments of the present application provide a hardware system, method, storage medium and electronic device for determining parameters of a storage application chip, so as to at least solve the problem of how to accurately determine the parameters of a storage application chip in the related art.

[0007] According to one embodiment of the present application, a parameter determination hardware system for a storage application chip, the system includes: a server host, used to send video data to the storage application chip; the storage application chip, used to determine the parameters of the storage application chip, adjust the parameters of the storage application chip according to the determined parameters, and process the video data into compressed video data after the parameter adjustment; a storage hard disk, used to receive the compressed video data; wherein the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; the video graphics array module is used to receive the video data sent by the server host, and transmit the video data to the video compression module of the storage application chip; the video compression module is used to process the video data into the Compress video data, and transmit the compressed video data to the storage controller through the system bus; the storage controller is used to send the compressed video data to the storage hard disk; wherein the video compression module includes a storage array depth determination module; the parameters of the storage application chip include: processor frequency, system bus frequency, storage array depth of the video compression module; the frequency determination module is used to determine the processor frequency and the system bus frequency according to the response time and delay time, wherein the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of the peripheral module connected to the processor through the system bus; the storage array depth determination module is used to determine the storage array depth according to the time of compressing the image frame by the video compression module.

[0008] In an exemplary embodiment, the video compression module also includes: a color space conversion module, used to perform color space conversion on the video data, wherein the color space conversion includes converting the color channel data in the video data into brightness and chrominance data; a data block generation module, used to convert the video data after color space conversion into video data in data block format; and a video core compression module, used to compress the video data in data block format into the compressed video data.

[0009] In an exemplary embodiment, the video compression module also includes: a storage array for storing the video data in the data block format; wherein the size of the storage array is determined by the storage array depth, and when compressing the video data of the current image frame, the video core compression module only obtains the video data in the data block format corresponding to the current image frame from the storage array.

[0010] In an exemplary embodiment, the storage array depth determination module includes: a hardware compression time acquisition module, used to obtain the time when the video core compression module compresses the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; a simulation compression time acquisition module, used to obtain the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and obtain the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the simulation compression time acquisition module has been configured with compression times of multiple first image frames and compression times of multiple second image frames.

[0011] In an exemplary embodiment, the storage array depth determination module further includes: a hardware compression time calculation module, which is used to calculate the target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; a storage array write speed calculation module, which is used to calculate the target data write speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to the target data volume, the first pixel clock, and the second pixel clock, wherein the target data volume represents the data write amount of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; a storage array depth calculation module, which is used to calculate the storage array depth according to the target time and the target data write speed.

[0012] In an exemplary embodiment, the frequency determination module includes: a system response time testing module, used to test the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than the preset frequency; a peripheral delay time testing module, used to test the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times.

[0013] In an exemplary embodiment, the frequency determination module also includes: a simulation frequency combination determination module, which is used to test the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determine the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; a frequency combination determination module, which is used to calculate the minimum response time and the target frequency combination corresponding to the minimum response time based on the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes the target processor frequency and the target system bus frequency.

[0014] According to another embodiment of the present application, a method for determining parameters of a storage application chip is provided, which is applied to a parameter determination hardware system of the above-mentioned storage application chip, wherein the system includes a storage application chip, the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, and a storage controller, and the parameters of the storage application chip include: processor frequency, system bus frequency, and storage array depth of the video compression module. The method includes: determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents the response time of an operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus; determining the storage array depth according to the time for compressing an image frame by the video compression module; and adjusting the parameters of the storage application chip according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

[0015] In an exemplary embodiment, the video compression module includes a video core compression module and a storage array, and the depth of the storage array is determined according to the time when the video compression module compresses an image frame, including: obtaining the time when the video core compression module compresses the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; obtaining the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and obtaining the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the compression time of multiple first image frames and the compression time of multiple second image frames have been configured in the simulation compression time acquisition module; according to the time when the video core compression module compresses the first image frame multiple times in the real environment, the video core compression module compresses the first image frame multiple times in the simulation environment The module compresses the first image frame multiple times, and the video core compression module compresses the second image frame multiple times in a simulation environment to calculate the target time, wherein the target time represents the time calculated for the video core compression module to compress the second image frame in a real environment; the target data writing speed of the storage array within a preset time length is calculated according to the target data volume, the first pixel clock, and the second pixel clock when the video core compression module compresses the second image frame, wherein the target data volume represents the data writing amount of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; the storage array depth is calculated according to the target time and the target data writing speed.

[0016] In an exemplary embodiment, the target time is calculated by the following formula: ;in, Indicates the target time, represents the time when the video core compression module first compresses the first image frame in a real environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a real environment, represents the time when the video core compression module first compresses the first image frame in the simulation environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a simulation environment, represents the time when the video core compression module first compresses the second image frame in the simulation environment, It represents the time when the video core compression module compresses the second image frame for the Nth time in a simulation environment, where N is a positive integer.

[0017] In an exemplary embodiment, determining the processor frequency and the system bus frequency according to the response time and the delay time includes: testing the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than the preset frequency; testing the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times; testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; calculating the minimum response time and the target frequency combination corresponding to the minimum response time according to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

[0018] In an exemplary embodiment, the minimum response time is calculated by the following formula: ;in, Indicates the minimum response time, Indicates the minimum delay time, represents the response time of the operating system under the first frequency combination in a real environment, represents the response time of the operating system under the Mth first frequency combination in a real environment, represents the delay time of the peripheral module under the first frequency combination in the simulation environment, It represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

[0019] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0020] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0021] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0022] Through the present application, the processor frequency and the system bus frequency can be determined according to the response time and the delay time, wherein the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of the peripheral module connected to the processor through the system bus; the storage array depth is determined according to the time for the video compression module to compress the image frame; the storage application chip is parameter-adjusted according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment. Therefore, the problem of how to accurately determine the parameters of the storage application chip in the related art can be solved, and then the design parameters of the chip can be optimized to make full use of the storage resources of the chip. Specifically, it includes reducing the occupation of RAM (Random Access Memory) resources by the video function of the chip by determining the most suitable CPU frequency and system bus frequency combination of the chip, while accurately meeting user needs, reducing the overall power consumption of the storage application chip, and greatly reducing the cost of the chip project. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural block diagram of a hardware system for determining parameters of a storage application chip according to an embodiment of the present application;

[0024] Figure 2 is a structural block diagram of a storage application chip according to an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of a data block conversion process according to an embodiment of the present application;

[0026] Figure 4 is a structural block diagram of a video compression module according to an embodiment of the present application;

[0027] Figure 5 is a structural block diagram of a storage array depth determination module according to an embodiment of the present application;

[0028] Figure 6 is a structural block diagram of a frequency determination module according to an embodiment of the present application;

[0029] Figure 7 It is a flow chart of a method for determining parameters of a storage application chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0032] According to one embodiment of the present application, a parameter determination hardware system for a storage application chip, the system includes: a server host, used to send video data to the storage application chip; the storage application chip, used to determine the parameters of the storage application chip, adjust the parameters of the storage application chip according to the determined parameters, and process the video data into compressed video data after the parameter adjustment; a storage hard disk, used to receive the compressed video data; wherein the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; the video graphics array module is used to receive the video data sent by the server host, and transmit the video data to the video compression module of the storage application chip; the video compression module is used to process the video data into the Compress video data, and transmit the compressed video data to the storage controller through the system bus; the storage controller is used to send the compressed video data to the storage hard disk; wherein the video compression module includes a storage array depth determination module; the parameters of the storage application chip include: processor frequency, system bus frequency, storage array depth of the video compression module; the frequency determination module is used to determine the processor frequency and the system bus frequency according to the response time and delay time, wherein the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of the peripheral module connected to the processor through the system bus; the storage array depth determination module is used to determine the storage array depth according to the time of compressing the image frame by the video compression module.

[0033] In an optional embodiment, if Figure 1As shown, the parameter determination hardware system of the above-mentioned storage application chip includes a HOST host (equivalent to a server host), a storage application chip with integrated video function (equivalent to a storage application chip), and a DDR storage hard disk (equivalent to a storage hard disk), wherein the storage application chip with integrated video function specifically includes a VGA (Video Graphics Array) module, a video compression module, a frequency determination module, a system bus, a CPU (equivalent to a processor), a DDR (Double Data Rate) storage controller (equivalent to a storage controller), and a DDR storage hard disk (equivalent to a storage hard disk); UART (Universal Asynchronous Receiver / Transmitter) interface module, IIC (Inter-Integrated Circuit) interface module, USB (Universal Serial Bus) module, network module and other peripheral modules are connected to the processor through the system bus, and the server management and control software program runs on the processor CPU.

[0034] During the video transmission process, the video data on the operating system of the server host is input into the storage application chip with integrated video function through the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface. After the video data of the server host is processed by the VGA module, the video data in RGB format is output to the video compression module. The video compression module processes the video data into compressed video data, and then writes the compressed video data into the external DDR storage hard disk through the storage controller.

[0035] Optionally, in the above embodiment, for example, the server management control chip is a typical storage application chip with integrated video function. In the server field, the server management control chip is used to monitor the status of the server (temperature, fan, CPU operation status, etc.). It also has an important function, which is to transmit local video information to the remote end through the network for remote video display and monitoring. It should be noted that the solution of the present application is not limited to application in server management control chips, but can also be applied to any storage application chip with integrated video processing function.

[0036] In an exemplary embodiment, the video compression module also includes: a color space conversion module, used to perform color space conversion on the video data, wherein the color space conversion includes converting the color channel data in the video data into brightness and chrominance data; a data block generation module, used to convert the video data after color space conversion into video data in data block format; and a video core compression module, used to compress the video data in data block format into the compressed video data.

[0037] Optionally, in the above embodiment, if Figure 2 As shown, the video compression module specifically includes a color space conversion module, a data block generation module, a video core compression module, and a storage array depth determination module. After the video data of the server host is processed by the VGA module, the output is RGB format video data (equivalent to color channel data). The RGB format data is input to the color space conversion module to convert the RGB format video data into YUV format video data (equivalent to brightness and chrominance data). The specific conversion formula is as follows:

[0038] Y=0.257R+0.504G+0.098B+16;

[0039] U=0.148R–0.291G+0.439B+128;

[0040] V = 0.439R - 0.368G - 0.071B + 128;

[0041] Among them, R represents the value of the red channel in the color channel data, G represents the value of the green channel in the color channel data, B represents the value of the blue channel in the color channel data, Y represents the value of the brightness in the brightness and chromaticity data, U represents the value of the blue chromaticity in the brightness and chromaticity data, and V represents the value of the red chromaticity in the brightness and chromaticity data.

[0042] After the color space conversion module converts the video data in RGB format into the video data in YUV format, the database generation module performs BLOCK (data block) conversion on the video data in YUV format. Figure 2The write control module in the program writes data into the data block generation module, and the read control module reads data from the data block generation module. The size of BLOCK can be 16*16, 16*8, and 8*8 according to the three formats of YUV444 / YUV422 / YUV420. Therefore, 16 Y_FIFOs, 16 U_FIFOs, and 16 V_FIFOs are required for data caching. FIFO is a special data structure, the full name of which is "First-In, First-Out", which is used to store and manage data in the program to ensure that the data is read out in the order in which it is written. In this embodiment, multiple FIFOs are used to store the data of Y, U, and V components respectively.

[0043] In an optional embodiment, the process of BLOCK conversion is as follows: Figure 3 As shown, the grid on the left is equivalent to multiple YUV format data blocks ( Figure 3 The size of each data block is 8*8 or 16*16 pixels. The video data can be divided into multiple data blocks in the above way. According to the brightness, red chromaticity and blue chromaticity of the pixel, it can be divided into three components: Y, U and V.

[0044] Among them, for multiple rows of pixels in the left video data, all Y data are written in YUV420 format, and U and V data in even rows and even columns are written. Therefore, in the processed data block format, the height and width of the data block representing the Y component remain unchanged, and the height and width of the data block representing the U and V components are reduced to 1 / 2 of the original.

[0045] In the YUV422 format, all Y data is written, but for U and V data, only one out of every two pixels needs to be written. Specifically, the U and V components are stored interleaved, and each U (or V) value corresponds to two Y values, which means that the sampling rate of U and V data is half the sampling rate of the Y component. This format samples all Y components in the horizontal direction, but maintains the same sampling rate as the Y component in the vertical direction. Therefore, the height and width of the data block of the Y component remain unchanged because the Y component contains information for each row and column of the image. The width of the data block representing the U and V components is reduced to half of the original width because each U and V value corresponds to two pixels in the horizontal direction. However, the height remains unchanged because the U and V components match the number of rows of the Y component in the vertical direction.

[0046] In the YUV444 format, when writing data, it is necessary to write the Y / U / V data of all rows and columns. Therefore, in the processed data block format, the height and width of the data block representing the Y, U, and V components remain unchanged.

[0047] In an exemplary embodiment, the video compression module also includes: a storage array for storing the video data in the data block format; wherein the size of the storage array is determined by the storage array depth, and when compressing the video data of the current image frame, the video core compression module only obtains the video data in the data block format corresponding to the current image frame from the storage array.

[0048] Optionally, in the above embodiment, if Figure 2 As shown, after obtaining the video data in data block format, the video data is input into the video core compression module for compression processing. During the compression process of the current image frame, the video core compression module does not receive the next frame data to be written. The video data after the current image frame is stored in the storage array. Therefore, in order to avoid the loss of subsequent frame data in the design, the depth of the storage array is generally set very deep. In the present application, the storage array depth determination module can be used to determine the storage array depth according to the time taken by the video compression module to compress the image frame.

[0049] In an exemplary embodiment, the storage array depth determination module includes: a hardware compression time acquisition module, used to obtain the time when the video core compression module compresses the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; a simulation compression time acquisition module, used to obtain the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and obtain the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the simulation compression time acquisition module has been configured with compression times of multiple first image frames and compression times of multiple second image frames.

[0050] In an exemplary embodiment, the storage array depth determination module further includes: a hardware compression time calculation module, which is used to calculate the target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; a storage array write speed calculation module, which is used to calculate the target data write speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to the target data volume, the first pixel clock, and the second pixel clock, wherein the target data volume represents the data write amount of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; a storage array depth calculation module, which is used to calculate the storage array depth according to the target time and the target data write speed.

[0051] Optionally, in the above embodiment, if Figure 4 As shown, the storage array depth determination module includes:

[0052] Hardware compression time acquisition module: obtains the time for the video core compression module to compress low-resolution image frames in low-resolution scenarios that can be tested on the real hardware environment of the storage application chip (such as resolutions of 640*480, 800*600, 1024*768, etc., and the resolution does not exceed the maximum resolution that can be tested in the above real hardware environment (equivalent to the preset resolution)), which are recorded as T_L_H_0, T_L_H_1...T_L_H_N-1 respectively. Among them, L (Low) represents low resolution, H (Hard) represents hardware, T_L_H is the low-resolution hardware environment, and N represents the number of statistics. T_L_H_0, T_L_H_1...T_L_H_N-1 are equivalent to the time for the video core compression module to compress the first image frame multiple times in the simulation environment. The resolution of the first image frame is, for example, an image frame with a resolution of 640*480, 800*600, or 1024*768. In this module, the total data blocks of the current image frame are calculated using the resolution information and the YUV format (YUV444 / YUV420 / YUV422), and the compressed frame tail flag (such as FFD9 of the number of JPEGs) at the output of the video core compression module is detected to determine when the last data block of the previous frame is and when the compression of the current frame is completed. The number of clock cycles T_num in the time period from the last data block of the previous frame to the completion of the compression of the current frame is counted, multiplied by the length of each clock cycle T_length (such as the frequency of 50M, the corresponding clock cycle length is 1000 / 50=20ns), T_num*T_length is the statistical time.

[0053] Simulation compression time acquisition module: This module is configured with the time for the video core compression module in the simulation software to compress low-resolution image frames and the time for compressing high-resolution image frames, where high resolution means exceeding the maximum resolution that can be tested in the real hardware environment of the storage application chip. It should be noted that the specific simulation process is completed by the user in advance, and this module is only configured with the compression time obtained from the simulation result. Among them, the time for compressing low-resolution image frames (equivalent to the first image frame) is recorded as T_L_S_0, T_L_S_1... T_L_S_N-1, and the time for compressing high-resolution image frames (equivalent to the second image frame) is recorded as T_H_S_0, T_H_S_1... T_H_S_N-1, where L (Low) means low resolution, H (High) means high resolution, S (Simulation) means software simulation, T_L_S means low-resolution simulation environment, and T_H_S means high-resolution simulation environment.

[0054] Hardware compression time calculation module: receives the time of compressing low-resolution image frames in the real hardware environment by the storage application chip, receives the time of compressing low-resolution image frames in the simulation environment, and receives the time of compressing high-resolution image frames in the simulation environment. Based on the above time, the estimated time of compressing high-resolution image frames in the real hardware environment (equivalent to the target time) is calculated. The specific calculation formula is as follows:

[0055] ,in, Indicates the target time, represents the time when the video core compression module first compresses the first image frame in a real environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a real environment, represents the time when the video core compression module first compresses the first image frame in the simulation environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a simulation environment, represents the time when the video core compression module first compresses the second image frame in the simulation environment, It represents the time when the video core compression module compresses the second image frame for the Nth time in a simulation environment, where N is a positive integer.

[0056] Storage array write speed calculation module: estimates the video data write speed in high-resolution scenarios, and counts the amount of data written to the storage array in a T period in a low-resolution scenario, data_num_0, data_num_1...data_num_N-1 (in bytes), where the pixel clock pixel_clk_L (equivalent to the first pixel clock) corresponding to the low resolution and the pixel clock pixel_clk_H (equivalent to the second pixel clock) corresponding to the high resolution are all standard known quantities. The calculation formula for the data write speed Wr_Speed_H_estimate of the storage array in the T period is as follows:

[0057] .

[0058] Storage array depth calculation module: The depth of the storage array in the high-resolution scenario is calculated based on the time T_H_H_estimate for compressing high-resolution image frames in the real hardware environment and the calculated data writing speed Wr_Speed_H_estimate of the storage array in the high-resolution scenario. The calculation formula is as follows:

[0059] ,

[0060] Among them, Array_Width is the width of the storage array. The widths set for SoC chips of different specifications may be different, such as 8 or 16, and Array_Depth_estimate is the calculated storage array depth. It should be noted that for different chip projects, the highest resolution required to be supported is different. For example, the storage application chip needs to support a high resolution value of 1920*1200, while the imaging-specific display chip may support 4K resolution, that is, 4096×2160 resolution. Therefore, this application can calculate the most suitable storage array depth for different SoC chip projects of different customers and different application scenarios. Therefore, the technical solution of this patent has extremely strong application flexibility.

[0061] In an exemplary embodiment, the frequency determination module includes: a system response time testing module, used to test the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than the preset frequency; a peripheral delay time testing module, used to test the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times.

[0062] In an exemplary embodiment, the frequency determination module also includes: a simulation frequency combination determination module, which is used to test the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determine the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; a frequency combination determination module, which is used to calculate the minimum response time and the target frequency combination corresponding to the minimum response time based on the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes the target processor frequency and the target system bus frequency.

[0063] Optionally, in the above embodiment, if Figure 5 As shown, the frequency determination module includes:

[0064] The system response time test module tests the operating system response time corresponding to different CPU main frequencies (equivalent to processor frequency) and system bus frequency combinations of the storage application chip in a real hardware environment, wherein the operating system runs on the CPU. It should be noted that the real hardware environment can only test frequency combinations in the low-frequency range (equivalent to multiple first frequency combinations lower than the preset frequency). The operating system response time refers to the system response time when the operating system and the application are running at the same time. This response time reflects the impact of the CPU main frequency and the system bus frequency on the system performance of the chip in a real hardware environment. Different chips use different applications. Therefore, this application can be applied to the determination of the optimal CPU main frequency and system bus frequency combination for different chips, and has strong application flexibility. After testing, a system response time mapping table corresponding to different low-frequency range CPU main frequencies and system bus frequency combination modes can be created inside the module according to the test results, as shown in Table 1.

[0065] Table 1

[0066]

[0067] The peripheral delay time test module tests the delay time of the peripheral module corresponding to different CPU main frequency and system bus frequency combinations in the simulation environment. The tested frequency combination is the same as the frequency combination tested by the above-mentioned system response time test module, which are all low-frequency combinations. For example, if the peripheral module is a network module, the delay time refers to the delay value (equivalent to the delay time) of the network module sending data from the software to the DDR storage hard disk, and then the network module reads the DDR storage hard disk to obtain the sent data, and then processes it internally in the network module to form a network frame format. After the test, a mapping table of the CPU main frequency and system bus frequency combination and the delay value in the simulation environment can be created inside the module according to the test results, as shown in Table 2.

[0068] Table 2

[0069]

[0070] The simulation frequency combination determination module tests the delay value of the peripheral module under different CPU main frequency and system bus frequency combinations in the simulation environment. The tested frequency combinations include high-frequency combinations that the FPGA cannot test in the real hardware environment (equivalent to multiple second frequency combinations within all frequency ranges). When the CPU main frequency and the system bus frequency are both low, as the CPU main frequency and the system bus frequency increase, the delay value of the peripheral module decreases accordingly. When the CPU main frequency increases to a certain high frequency value, further increasing the CPU main frequency has almost no effect on the delay value of the peripheral module. Then the CPU main frequency value is fixed to obtain the best CPU main frequency CPU_FREQ_BEST, and then the system bus frequency value is increased. When the increase in the system bus frequency value has almost no effect on the delay value of the peripheral module, the system bus frequency value is fixed to obtain the best system bus frequency SYS_BUS_FREQ_BEST. The frequency combination of the best CPU main frequency CPU_FREQ_BEST and the best system bus frequency SYS_BUS_FREQ_BEST is the best frequency combination (equivalent to the frequency combination corresponding to the minimum delay time), and the delay value DELAY_BEST corresponding to this frequency combination is the minimum delay time.

[0071] The frequency combination determination module, based on the test results of the system response time test module and the peripheral delay time test module, establishes the corresponding relationship between the system response time of the real hardware environment under the low-frequency combination and the delay value of the peripheral module under the simulation environment. Then, based on the best frequency combination of the simulation environment under the high-frequency combination obtained by the simulation frequency combination determination module, that is, the best CPU main frequency CPU_FREQ_BEST and the best system bus frequency SYS_BUS_FREQ_BEST, the minimum system response time corresponding to the best frequency combination under the real hardware environment is inferred. The calculation formula is as follows:

[0072] ;

[0073] in, Indicates the minimum response time, Indicates the minimum delay time, represents the response time of the operating system under the first frequency combination in a real environment, represents the response time of the operating system under the Mth first frequency combination in a real environment, represents the delay time of the peripheral module under the first frequency combination in the simulation environment, It represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

[0074] Optionally, in the above embodiment, after calculating the system response time corresponding to the optimal frequency combination, if the system response time meets the project requirements, the CPU main frequency and system bus frequency of the storage application chip are set according to the optimal CPU main frequency CPU_FREQ_BEST and the optimal system bus frequency SYS_BUS_FREQ_BEST; if the project requirements are not met, continue to test a group of efficient CPU main frequency and system bus frequency combinations in the simulation environment, and continue to use the above formula to calculate the system response time corresponding to the combination.

[0075] In an optional embodiment, after obtaining the optimal CPU main frequency and system bus frequency and the optimal storage array depth mentioned above, the designer modifies the design parameters of the storage application chip according to the above parameters, as follows: Figure 6 As shown, the following steps are included:

[0076] 1. RTL code development:

[0077] RTL (Register Transfer Level) is a description method of hardware description language (such as Verilog or VHDL) at a higher level of abstraction. At this stage, designers will use hardware description language to write code to define the behavior of digital circuits.

[0078] 2. RTL code simulation:

[0079] Use simulation software (such as ModelSim, VCS or Vivado simulation tools) to simulate the behavior of RTL code under various conditions. Through simulation, designers can test and verify whether the circuit functions as expected without the need for actual hardware. This stage can discover circuit logic errors, timing problems and performance bottlenecks. For example, in this embodiment, the optimal CPU main frequency and system bus frequency of the chip are obtained by determining the performance bottleneck.

[0080] 3.FPGA prototype verification:

[0081] FPGA is a programmable logic circuit chip that can be repeatedly programmed. Different functions can be realized by loading different logic circuit configurations. In the field of chip design, FPGA prototype verification is a necessary process. After the chip design code is synthesized, the FPGA configuration file of the corresponding function is generated. In this way, the logical function of the chip code is run on the FPGA to verify the functional correctness of the design code and the performance of the system. At this stage, the above-determined optimal CPU main frequency, system bus frequency, storage array depth and other parameters can be verified. If the verification is passed, the next stage of back-end design chip tape-out will be entered. If the verification does not meet the requirements, the parameters need to be adjusted, and steps 1-3 are repeated to determine the parameters that meet the requirements.

[0082] 4. Back-end design chip tape-out:

[0083] After determining the various parameters of the chip, the back-end design is carried out, including layout, routing, timing analysis, power consumption analysis, etc. After the design is completed, the chip is taped out. Tape-out means sending the designed circuit diagram to the manufacturer to make the actual silicon chip. After the tape-out is successful, the actual chip is obtained, and these chips will be put into use in the product.

[0084] Through the above embodiments, it is more convenient for chip designers to determine chip parameters that meet the requirements, thereby reducing the chip performance waste or chip performance failure caused by inappropriate chip parameters.

[0085] In this embodiment, a method for determining parameters of a storage application chip is also provided, which is applied to the parameter determination hardware system of the storage application chip. Figure 7 is a flow chart of a method for determining parameters of a storage application chip according to an embodiment of the present application. Figure 7 As shown, the process includes the following steps:

[0086] Step S702, determining the processor frequency and the system bus frequency according to the response time and the delay time, wherein the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of the peripheral module connected to the processor through the system bus;

[0087] Step S704, determining the storage array depth according to the time taken by the video compression module to compress the image frame;

[0088] Step S706, adjusting parameters of the storage application chip according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

[0089] Through the above steps, the processor frequency and the system bus frequency can be determined according to the response time of the operating system running on the processor and the delay time of the peripheral module connected to the processor through the system bus, and then the storage array depth can be determined according to the time of the video compression module compressing the image frame, and finally the storage application chip is parameter-adjusted according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment. Therefore, the problem of how to accurately determine the parameters of the storage application chip in the related art can be solved.

[0090] In an exemplary embodiment, the video compression module includes a video core compression module and a storage array, and the depth of the storage array is determined according to the time when the video compression module compresses an image frame, including: obtaining the time when the video core compression module compresses the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; obtaining the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and obtaining the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the compression time of multiple first image frames and the compression time of multiple second image frames have been configured in the simulation compression time acquisition module; according to the time when the video core compression module compresses the first image frame multiple times in the real environment, the video core compression module compresses the first image frame multiple times in the simulation environment The module compresses the first image frame multiple times, and the video core compression module compresses the second image frame multiple times in a simulation environment to calculate the target time, wherein the target time represents the time calculated for the video core compression module to compress the second image frame in a real environment; the target data writing speed of the storage array within a preset time length is calculated according to the target data volume, the first pixel clock, and the second pixel clock when the video core compression module compresses the second image frame, wherein the target data volume represents the data writing amount of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; the storage array depth is calculated according to the target time and the target data writing speed.

[0091] In an exemplary embodiment, the target time is calculated by the following formula: ;in, Indicates the target time, represents the time when the video core compression module first compresses the first image frame in a real environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a real environment, represents the time when the video core compression module first compresses the first image frame in the simulation environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a simulation environment, represents the time when the video core compression module first compresses the second image frame in the simulation environment, It represents the time when the video core compression module compresses the second image frame for the Nth time in a simulation environment, where N is a positive integer.

[0092] In an exemplary embodiment, determining the processor frequency and the system bus frequency according to the response time and the delay time includes: testing the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than the preset frequency; testing the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times; testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; calculating the minimum response time and the target frequency combination corresponding to the minimum response time according to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

[0093] In an exemplary embodiment, the minimum response time is calculated by the following formula: ;in, Indicates the minimum response time, Indicates the minimum delay time, represents the response time of the operating system under the first frequency combination in a real environment, represents the response time of the operating system under the Mth first frequency combination in a real environment, represents the delay time of the peripheral module under the first frequency combination in the simulation environment, It represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

[0094] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0095] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0096] S1, determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents the response time of an operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus;

[0097] S2, determining the storage array depth according to the time taken by the video compression module to compress the image frame;

[0098] S3, adjusting parameters of the storage application chip according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

[0099] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0100] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0101] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0102] S1, determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents the response time of an operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus;

[0103] S2, determining the storage array depth according to the time taken by the video compression module to compress the image frame;

[0104] S3, adjusting parameters of the storage application chip according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

[0105] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0106] Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

[0107] S1, determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents the response time of an operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus;

[0108] S2, determining the storage array depth according to the time taken by the video compression module to compress the image frame;

[0109] S3, adjusting parameters of the storage application chip according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

[0110] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0111] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0112] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A hardware system for determining parameters of a storage application chip, characterized in that: The system comprises: A server host, used for sending video data to a storage application chip; The storage application chip is used to determine parameters of the storage application chip, adjust the parameters of the storage application chip according to the determined parameters, and process the video data into compressed video data after the parameter adjustment; A storage hard disk, used for receiving the compressed video data; Wherein, the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; The video graphics array module is used to receive the video data sent by the server host, and transmit the video data to the video compression module of the storage application chip; The video compression module is used to process the video data into the compressed video data, and transmit the compressed video data to the storage controller through the system bus; The storage controller is used to send the compressed video data to the storage hard disk; Wherein, the video compression module includes a storage array depth determination module; The parameters of the storage application chip include: processor frequency, system bus frequency, and storage array depth of the video compression module; The frequency determination module is used to determine the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents the response time of an operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus; The storage array depth determination module is used to determine the storage array depth according to the time taken by the video compression module to compress the image frame.

2. The system according to claim 1, characterized in that The video compression module also includes: A color space conversion module, used for performing color space conversion on the video data, wherein the color space conversion includes converting color channel data in the video data into brightness and chrominance data; A data block generation module, used for converting the video data after the color space conversion into video data in a data block format; The video core compression module is used to compress the video data in the data block format into the compressed video data.

3. The system according to claim 2, characterized in that The video compression module also includes: A storage array, used for storing the video data in the data block format; The size of the storage array is determined by the depth of the storage array, and when compressing the video data of the current image frame, the video core compression module only obtains the video data in the data block format corresponding to the current image frame from the storage array.

4. The system according to claim 3, characterized in that The storage array depth determination module comprises: A hardware compression time acquisition module, used to acquire the time when the video core compression module compresses the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; A simulation compression time acquisition module is used to obtain the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and to obtain the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the simulation compression time acquisition module has been configured with the compression time of multiple first image frames and the compression time of multiple second image frames.

5. The system according to claim 4, characterized in that The storage array depth determination module further includes: a hardware compression time calculation module, used to calculate a target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; a storage array write speed calculation module, configured to calculate a target data write speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, wherein the target data volume represents the data write volume of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; A storage array depth calculation module is used to calculate the storage array depth according to the target time and the target data writing speed.

6. The system according to claim 1, characterized in that The frequency determination module comprises: A system response time test module, used for testing the response time of the operating system under a plurality of first frequency combinations in a real environment to obtain a plurality of response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the plurality of first frequency combinations are all lower than a preset frequency; The peripheral delay time testing module is used to test the delay time of the peripheral module under the plurality of first frequency combinations in a simulation environment to obtain a plurality of delay times.

7. The system according to claim 6, characterized in that The frequency determination module further includes: A simulation frequency combination determination module, used for testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; A frequency combination determination module is used to calculate the minimum response time and the target frequency combination corresponding to the minimum response time based on the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

8. A method for determining parameters of a storage application chip, characterized in that: Applied to the system described in any one of claims 1 to 7, the system comprises a storage application chip, the storage application chip comprises a video graphics array module, a video compression module, a system bus, a processor, and a storage controller, the parameters of the storage application chip comprise: processor frequency, system bus frequency, and storage array depth of the video compression module, the method comprises: Determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents a response time of an operating system running on the processor, and the delay time represents a delay time of a peripheral module connected to the processor through the system bus; Determining the storage array depth according to the time taken by the video compression module to compress the image frame; The storage application chip is parameter-adjusted according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

9. The method according to claim 8, characterized in that The video compression module includes a video core compression module and a storage array, and the depth of the storage array is determined according to the time for compressing the image frame by the video compression module, including: Acquire the time for the video core compression module to compress the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; Acquire the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and acquire the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the compression time of multiple first image frames and the compression time of multiple second image frames are configured in the simulation compression time acquisition module; Calculate the target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; Calculating a target data writing speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, wherein the target data volume represents the data writing volume of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; The storage array depth is calculated according to the target time and the target data writing speed.

10. The method according to claim 9, characterized in that The target time is calculated by the following formula: ； in, Indicates the target time, represents the time when the video core compression module first compresses the first image frame in a real environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a real environment, represents the time when the video core compression module first compresses the first image frame in the simulation environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a simulation environment, represents the time when the video core compression module first compresses the second image frame in the simulation environment, It represents the time when the video core compression module compresses the second image frame for the Nth time in a simulation environment, where N is a positive integer.

11. The method according to claim 8, characterized in that Determining the processor frequency and the system bus frequency according to the response time and the delay time includes: Testing the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than a preset frequency; Testing the delay time of the peripheral module under the plurality of first frequency combinations in a simulation environment to obtain a plurality of delay times; Testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; According to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, the minimum response time and the target frequency combination corresponding to the minimum response time are calculated, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

12. The method according to claim 11, characterized in that The minimum response time is calculated by the following formula: ； in, Indicates the minimum response time, Indicates the minimum delay time, represents the response time of the operating system under the first frequency combination in a real environment, represents the response time of the operating system under the Mth first frequency combination in a real environment, represents the delay time of the peripheral module under the first frequency combination in the simulation environment, It represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 8 to 12 when executed by a processor.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 8 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 8 to 12 are implemented.

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