Wafer-level integrated structure and manufacturing method thereof

Abstract

The present invention discloses a wafer-level integrated structure and a method for manufacturing the same. The wafer-level integrated structure includes: a glass substrate, a chip unit layer, a conductive protrusion layer, and a device module layer. The glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer via the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the chip unit layer is located on a side of the first conductive pattern layer away from the interlayer substrate and is electrically connected to the first conductive pattern layer; the conductive protrusion layer is located on a side of the second conductive pattern layer away from the interlayer substrate and is electrically connected to the second conductive pattern layer; the device module layer is located on a side of the conductive protrusion layer away from the second conductive pattern layer and is electrically connected to the conductive protrusion layer. The present invention provides a wafer-level integrated structure and a method for manufacturing the same, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer-level integrated structure and a manufacturing method thereof. Background Art

[0002] Wafer-level packaging (WLP) involves packaging and testing most or all chips directly on the wafer before dicing them into individual components. WLP offers the advantages of smaller package size and better electrical performance.

[0003] The existing wafer-level packaging structure has the following problems: the number of wafer-level multi-chip connections is limited, the number of interconnection lines between wafer-level chips is limited, the bandwidth between wafer-level chips is limited, and communication between wafer-level chips requires the use of multiple channels such as substrates and PCB boards, resulting in long communication links and large delays. Summary of the Invention

[0004] The present invention provides a wafer-level integrated structure and a manufacturing method thereof, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

[0005] According to one aspect of the present invention, there is provided a wafer-level integrated structure, the wafer-level integrated structure comprising:

[0006] A glass substrate, the glass substrate comprising a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer being electrically connected to the second conductive pattern layer via the interlayer substrate; the interlayer substrate comprising at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the interlayer conductive pattern layers and the interlayer glass bodies being alternately stacked; a film layer in the interlayer substrate adjacent to the first conductive pattern layer and a film layer adjacent to the second conductive pattern layer both comprising the interlayer glass bodies;

[0007] a chip unit layer, located on a side of the first conductive pattern layer away from the interlayer substrate and electrically connected to the first conductive pattern layer; the chip unit layer includes a plurality of semiconductor chips;

[0008] a conductive protrusion layer, located on a side of the second conductive pattern layer away from the interlayer substrate and electrically connected to the second conductive pattern layer;

[0009] The device module layer is located on a side of the conductive protrusion layer away from the second conductive pattern layer and is electrically connected to the conductive protrusion layer.

[0010] Optionally, the plurality of semiconductor chips include a plurality of computing chips and a plurality of storage chips;

[0011] The computing chip and the storage chip are connected and communicated with each other via the glass substrate;

[0012] The computing chips are connected and communicated with each other through the glass substrate.

[0013] Optionally, the device module layer includes a plurality of power modules;

[0014] The power supply module is used to supply power to the chip unit layer, and the power supply direction of the power supply module to the chip unit layer is the thickness direction of the glass substrate.

[0015] Optionally, the device module layer further includes a plurality of passive components, a plurality of low-speed connectors and a plurality of high-speed connectors;

[0016] The low-speed connector is adjacent to the power module;

[0017] A vertical projection of the high-speed connector on the glass substrate is located at an edge region of the glass substrate.

[0018] Optionally, the wafer-level integrated structure provided in this embodiment further includes a metal bump layer;

[0019] The metal bump layer is located between the chip unit layer and the glass substrate;

[0020] The chip unit layer is electrically connected to the first conductive pattern layer in the glass substrate through the metal bump layer.

[0021] Optionally, the wafer-level integrated structure provided in this embodiment further includes a first heat dissipation layer and a second heat dissipation layer;

[0022] The first heat dissipation layer is located on a side of the chip unit layer away from the glass substrate;

[0023] The second heat dissipation layer is located on a side of the device module layer away from the conductive protrusion layer.

[0024] Optionally, the glass substrate includes resistors and capacitors inside.

[0025] Optionally, the interlayer substrate further includes at least one entire metal layer.

[0026] Optionally, the glass substrate further includes a first insulating layer, a second insulating layer and at least one interlayer insulating layer;

[0027] The first insulating layer is used to fill the gaps in the first conductive pattern layer;

[0028] The number of interlayer insulating layers is equal to the number of interlayer conductive pattern layers, the interlayer insulating layers correspond to the interlayer conductive pattern layers one by one, the interlayer insulating layers are used to cover the corresponding interlayer conductive pattern layers, the interlayer insulating layers include insulating through holes, and the insulating through holes expose glass through holes electrically connected to the interlayer conductive pattern layers;

[0029] The second insulating layer is used to fill gaps in the second conductive pattern layer.

[0030] According to another aspect of the present invention, a method for manufacturing a wafer-level integrated structure is provided, the method comprising:

[0031] A glass substrate is formed, wherein the glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer through the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the interlayer conductive pattern layers and the interlayer glass bodies are alternately stacked; and a film layer in the interlayer substrate close to the first conductive pattern layer and a film layer close to the second conductive pattern layer are both the interlayer glass bodies;

[0032] forming a chip unit layer electrically connected to the first conductive pattern layer on a side of the first conductive pattern layer away from the interlayer substrate, wherein the chip unit layer includes a plurality of semiconductor chips;

[0033] forming a conductive protrusion layer electrically connected to the second conductive pattern layer on a side of the second conductive pattern layer away from the interlayer substrate;

[0034] A device module layer electrically connected to the conductive protrusion layer is formed on a side of the conductive protrusion layer away from the second conductive pattern layer.

[0035] An embodiment of the present invention provides a wafer-level integrated structure, which includes a glass substrate, a chip unit layer located on one side of the glass substrate, a conductive protrusion layer located on the side of the glass substrate away from the chip unit layer, and a device module layer located on the side of the conductive protrusion layer away from the glass substrate. The glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence. The chip unit layer includes a plurality of semiconductor chips, and the device module layer includes a plurality of devices and modules. The plurality of semiconductor chips in the chip unit layer are all electrically connected to the first conductive pattern layer, and the plurality of semiconductor chips can communicate with each other through the first conductive pattern layer and the interlayer conductive pattern layer in the interlayer substrate. The chip unit layer and the device module layer can also communicate with each other through the glass substrate, the device module layer is electrically connected to the second conductive pattern layer, and the devices in the device module layer can communicate with each other through the second conductive pattern layer and the interlayer conductive pattern layer in the interlayer substrate, thereby replacing the PCB board with the glass substrate. This embodiment places the device module layer on the side of the glass substrate away from the chip unit layer, allowing more semiconductor chips to be placed on one side of the glass substrate, thereby increasing the bandwidth of the wafer-level integrated structure. The semiconductor chips communicate with each other through the glass substrate, reducing the number of communication paths. In summary, the wafer-level integrated structure provided by this embodiment can increase the bandwidth of the wafer-level integrated structure and reduce the number of communication paths.

[0036] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 2. It is a schematic diagram of the front structure of a wafer-level integrated structure provided in an embodiment of the present invention;

[0039] Figure 2 2 is a schematic diagram of the back side structure of a wafer-level integrated structure provided in an embodiment of the present invention;

[0040] Figure 3 is a schematic cross-sectional structural diagram of a wafer-level integrated structure provided according to an embodiment of the present invention;

[0041] Figure 4 is a schematic cross-sectional structural diagram of another wafer-level integrated structure provided according to an embodiment of the present invention;

[0042] Figure 5 is a schematic cross-sectional structural diagram of another wafer-level integrated structure provided according to an embodiment of the present invention;

[0043] Figure 6 The figure is a flow chart of a method for manufacturing a wafer-level integrated structure provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] Figure 1 1 is a schematic diagram of the front structure of a wafer-level integrated structure provided according to an embodiment of the present invention. Figure 2 1 is a schematic diagram of the back structure of a wafer-level integrated structure provided according to an embodiment of the present invention. Figure 3 is a schematic cross-sectional view of a wafer-level integrated structure provided according to an embodiment of the present invention, with reference to Figure 1-Figure 3The wafer-level integrated structure provided in this embodiment includes: a glass substrate 110, a chip unit layer 120, a conductive protrusion layer 130 and a device module layer 140; the glass substrate 110 includes a first conductive pattern layer 111, an interlayer substrate 112 and a second conductive pattern layer 113 stacked in sequence; the first conductive pattern layer 111 is electrically connected to the second conductive pattern layer 113 through the interlayer substrate 112; the interlayer substrate 112 includes at least one interlayer conductive pattern layer 101 and at least two interlayer glass bodies 102; the interlayer conductive pattern layer 101 and the interlayer glass body 102 are alternately stacked; the interlayer substrate 112 is close to the The film layer of the first conductive pattern layer 111 and the film layer close to the second conductive pattern layer 113 are both the interlayer glass body 102; the chip unit layer 120 is located on the side of the first conductive pattern layer 111 away from the interlayer substrate 112, and is electrically connected to the first conductive pattern layer 111; the chip unit layer 120 includes a plurality of semiconductor chips 121; the conductive protrusion layer 130 is located on the side of the second conductive pattern layer 113 away from the interlayer substrate 112, and is electrically connected to the second conductive pattern layer 113; the device module layer 140 is located on the side of the conductive protrusion layer 130 away from the second conductive pattern layer 113, and is electrically connected to the conductive protrusion layer 130.

[0047] Specifically, the glass substrate 110 is a wafer-level substrate using glass as a carrier and has wafer-level dimensions. The semiconductor chips 121 in the chip unit layer 120 can be bare chips that have been cut and tested but not yet packaged. The chip unit layer 120 can include multiple semiconductor chips 121 with different functions. The device module layer 140 can include multiple devices and modules with different functions. For example, the device module layer 140 includes multiple passive components such as resistors, capacitors, and inductors, as well as power modules, low-speed connectors, and high-speed connectors. The conductive bump layer 130 includes multiple conductive bumps 131, each of which is electrically connected to the second conductive pattern layer 113 in the glass substrate 110. The conductive bumps 131 can be spherical in shape. The device module layer 140 is electrically connected to the second conductive pattern layer 113 via the conductive bump layer 130.

[0048] The material of the first conductive pattern layer 111, the material of the second conductive pattern layer 113, and the material of each interlayer conductive pattern layer 101 can all be copper. The difference between the number of layers of the interlayer glass body 102 and the number of layers of the interlayer conductive pattern layer 101 can be 1. Each interlayer glass body 102 also includes at least one through-glass via 103. The material of the through-glass via 103 can be metal. The through-glass via 103 is formed by drilling a hole in the interlayer glass body 102 and filling the hole with a conductive material. The material of the interlayer glass body 102 other than the through-glass via 103 can be glass. The first conductive pattern layer 111 and the second conductive pattern layer 113 are both electrically connected to the interlayer conductive pattern layer 101 through the through-glass via 103. The interlayer conductive pattern layers 101 are also electrically connected to each other through the through-glass via 103. Each interlayer glass body 102 has at least one through-glass hole 103 whose vertical projections on the first conductive pattern layer 111 overlap with each other, that is, the interlayer substrate 112 has at least one connecting through-glass hole 104 that directly and electrically connects the first conductive pattern layer 111 and the second conductive pattern layer 113.

[0049] The first conductive pattern layer 111 and the interlayer conductive pattern layer 101 can electrically connect the semiconductor chips 121. Communication between the semiconductor chips 121 is achieved through the first conductive pattern layer 111 and the interlayer conductive pattern layer 101, reducing the length of the signal link and the number of connectors connecting the semiconductor chips 121. The devices and modules in the device module layer 140 can be electrically connected through the second conductive pattern layer 113 and the interlayer conductive pattern layer 101, reducing the length of the signal link and the number of connectors. The conductive patterns of the first conductive pattern layer 111, the second conductive pattern layer 113, and the interlayer conductive pattern layers 101 can be different.

[0050] Each semiconductor chip 121 is electrically connected to the first conductive pattern layer 111. The semiconductor chips 121 can communicate with each other through the first conductive pattern layer 111 and the interlayer conductive pattern layer 101. The device module layer 140 can communicate with the chip unit layer 120 through the glass substrate 110. The devices and modules within the device module layer 140 can communicate with the interlayer conductive pattern layer 101 through the second conductive pattern layer 113. As can be seen, the glass substrate 110 in this embodiment can replace the existing PCB board, eliminating the need for a redistribution layer (RDL). This enables communication between different semiconductor chips 121, reducing the communication paths between different semiconductor chips 121. The semiconductor chips 121 can also be connected to external devices through the device module layer 140. In this embodiment, the device module layer 140 is disposed on a side of the glass substrate 110 away from the chip unit layer 120, without occupying the space on the glass substrate 110 where the chip unit layer 120 is disposed. This allows more semiconductor chips 121 to be disposed on one side of the glass substrate 110, thereby increasing the bandwidth of the wafer-level integrated structure.

[0051] This embodiment provides a wafer-level integrated structure, which includes a glass substrate, a chip unit layer located on one side of the glass substrate, a conductive protrusion layer located on the side of the glass substrate away from the chip unit layer, and a device module layer located on the side of the conductive protrusion layer away from the glass substrate. The glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence. The chip unit layer includes a plurality of semiconductor chips, and the device module layer includes a plurality of devices and modules. The plurality of semiconductor chips in the chip unit layer are all electrically connected to the first conductive pattern layer, and the plurality of semiconductor chips can communicate with each other through the first conductive pattern layer and the interlayer conductive pattern layer in the interlayer substrate. The chip unit layer and the device module layer can also communicate with each other through the glass substrate, the device module layer is electrically connected to the second conductive pattern layer, and the devices and modules in the device module layer can communicate with each other through the second conductive pattern layer and the interlayer conductive pattern layer in the interlayer substrate, thereby replacing the PCB board with the glass substrate. This embodiment places the device module layer on the side of the glass substrate away from the chip unit layer, allowing more semiconductor chips to be placed on one side of the glass substrate, thereby increasing the bandwidth of the wafer-level integrated structure. The semiconductor chips communicate with each other through the glass substrate, reducing the number of communication paths. In summary, the wafer-level integrated structure provided by this embodiment can increase the bandwidth of the wafer-level integrated structure and reduce the number of communication paths.

[0052] Optional, continue to refer to Figure 1 and Figure 3 The plurality of semiconductor chips 121 include a plurality of computing chips 122 and a plurality of storage chips 123 ; the computing chips 122 and the storage chips 123 are connected and communicated with each other via the glass substrate 110 ; and the computing chips 122 and the computing chips 122 are connected and communicated with each other via the glass substrate 110 .

[0053] Specifically, the computing chip 122 and the memory chip 123 are connected and communicated with each other via the first conductive pattern layer 111 and the interlayer conductive pattern layer 101 in the glass substrate 110, and the computing chips 122 are connected and communicated with each other via the first conductive pattern layer 111 and the interlayer conductive pattern layer 101 in the glass substrate 110. Exemplarily, one computing chip 122 and one memory chip 123 are connected and communicated with each other via the first conductive pattern layer 111 in the glass substrate 110, and another computing chip 122 and another memory chip 123 are connected and communicated with each other via the through-glass via 103 and the interlayer conductive pattern layer 101.

[0054] The computing chip 122 may be a SOC chip, and the memory chip 123 may be an HBM chip or a DDR chip. The computing chip 122 may be arranged in an array, and the memory chip 123 may also be arranged in an array. The computing chip 122 may be adjacent to the memory chip 123.

[0055] The computing chip 122 and the memory chip 123 are connected and communicated via the glass substrate 110, which can reduce the length of the signal link and the number of connectors. The computing chip 122 and the memory chip 123 are connected and communicated via the glass substrate 110, which can reduce the length of the signal link and the number of connectors.

[0056] Optional, Figure 4 is a schematic cross-sectional view of another wafer-level integrated structure provided according to an embodiment of the present invention, with reference to Figure 4 The device module layer 140 includes a plurality of power modules 141 . The power modules 141 are used to supply power to the chip unit layer 120 . The power supply direction of the power modules 141 to the chip unit layer 120 is the thickness direction of the glass substrate 110 .

[0057] Specifically, each power module 141 is electrically connected to the conductive raised layer 130 and can be arranged in an array. The vertical projection of a power module 141 on the glass substrate 110 overlaps the vertical projection of at least one semiconductor chip 121 on the glass substrate 110. The power module 141 can supply power to either the computing chip 122 or the memory chip 123. A single power module 141 can supply power to a single semiconductor chip 121 or to multiple semiconductor chips 121 simultaneously. The power module 141 supplies power to each semiconductor chip 121 in the direction of the thickness of the glass substrate 110.

[0058] The power supply direction of the power module 141 refers to the current transmission direction when the power module 141 supplies power to the chip unit layer 120. The power supply direction of the power module 141 is the thickness direction of the glass substrate 110, indicating that the power module 141 supplies power vertically to the semiconductor chip 121 in the chip unit layer 120. Using a vertical power supply method can reduce the wiring length of the power path, thereby reducing voltage drop and improving power supply efficiency.

[0059] Optional, reference Figure 2 and Figure 4 The device module layer 140 also includes multiple passive devices 142, multiple low-speed connectors 143 and multiple high-speed connectors 144; the low-speed connectors 143 are adjacent to the power module 141; the vertical projection of the high-speed connectors 144 on the glass substrate 110 is located in the edge area of ​​the glass substrate 110.

[0060] Specifically, the passive device 142 can be a resistor, capacitor, inductor or other device. By arranging the passive device 142 on the side of the glass substrate 110 away from the chip unit layer 120, more semiconductor chips 121 can be arranged on the first surface of the glass substrate 110 (the first surface refers to the surface on which the chip unit layer 120 is arranged), thereby further improving the bandwidth of the wafer-level integrated structure. The low-speed connector 143 can be electrically connected to the power module 141, and can also be electrically connected to the high-speed connector 144. The semiconductor chip 121 can be connected to the high-speed connector 144 through the glass substrate 110 and the low-speed connector 143, and connected to external devices through the high-speed connector 144. Arranging the high-speed connector 144 in the edge area of ​​the glass substrate 110 can facilitate the connection of the high-speed connector 144 to external devices, and the high-speed connector 144 can surround the power module 141. The transmission path of the high-speed connector 144 is separated from the power supply path of the power module 141, which can further improve the interconnection between systems.

[0061] Optional, Figure 5 is a schematic cross-sectional view of another wafer-level integrated structure provided according to an embodiment of the present invention, with reference to Figure 5 The wafer-level integrated structure provided in this embodiment also includes a metal bump layer 170; the metal bump layer 170 is located between the chip unit layer 120 and the glass substrate 110; the chip unit layer 120 is electrically connected to the first conductive pattern layer (not shown in the figure) in the glass substrate 110 through the metal bump layer 170.

[0062] Specifically, the metal bump layer 170 includes a plurality of metal bumps 171 , and each semiconductor chip 121 is electrically connected to the first conductive pattern layer via the metal bumps 171 .

[0063] Optional, continue to refer to Figure 5 The wafer-level integrated structure provided in this embodiment also includes a first heat dissipation layer 150 and a second heat dissipation layer 160; the first heat dissipation layer 150 is located on the side of the chip unit layer 120 away from the glass substrate 110; the second heat dissipation layer 160 is located on the side of the device module layer 140 away from the conductive protrusion layer 130.

[0064] Specifically, the first heat dissipation layer 150 includes a first thermal conductive layer 151 and a first heat dissipation module 152. The first thermal conductive layer 151 is located on one side of the chip unit layer 120, and the first heat dissipation module 152 is located on the side of the first thermal conductive layer 151 away from the chip unit layer 120. The second heat dissipation layer 160 includes a second thermal conductive layer 161 and a second heat dissipation module 162. The second thermal conductive layer 161 is located on one side of the device module layer 140, and the second heat dissipation module 162 is located on the side of the second thermal conductive layer 161 away from the device module layer 140. Both the first thermal conductive layer 151 and the second thermal conductive layer 161 can be made of thermal interface materials. The first heat dissipation module 152 and the second heat dissipation module 162 can be heat dissipation structures such as metal heat sinks or microchannels. The first heat dissipation layer 150 can quickly dissipate heat generated by the multiple semiconductor chips 121, improving the operating performance of the semiconductor chips 121. The second heat dissipation layer 160 can quickly dissipate heat generated by the devices and modules in the device module layer 140, improving the operating performance of the devices and modules. The first heat dissipation layer 150 and the second heat dissipation layer 160 can improve the heat dissipation performance of the wafer-level integrated structure. The inventors have found that the wafer-level integrated structure provided by this embodiment can still effectively dissipate heat when generating power consumption exceeding kilowatts during operation, ensuring that the wafer-level integrated structure can operate normally.

[0065] Optionally, the glass substrate includes resistors and capacitors inside.

[0066] Specifically, the resistors and capacitors within the glass substrate can be located in the first conductive pattern layer, the interlayer conductive pattern layer, the interlayer glass body, or the second conductive pattern layer. The resistors and capacitors within the glass substrate are electrically connected to the first conductive pattern layer, the interlayer conductive pattern layer, or the second conductive pattern layer. The placement of resistors and capacitors within the glass substrate can address the need for high-frequency decoupling in wafer-level integrated structures.

[0067] Optionally, the interlayer substrate further includes at least one entire metal layer.

[0068] Specifically, the entire metal layer is electrically connected to the through-glass via and can serve as a return path for high-speed signals within the wafer-level integrated structure. Providing the entire metal layer in the interlayer substrate can improve the signal quality of the wafer-level integrated structure.

[0069] Optionally, the glass substrate further includes a first insulating layer, a second insulating layer and at least one interlayer insulating layer; the first insulating layer is used to fill the gaps in the first conductive pattern layer; the number of interlayer insulating layers is equal to the number of interlayer conductive pattern layers, the interlayer insulating layers correspond one-to-one to the interlayer conductive pattern layers, the interlayer insulating layers are used to cover the corresponding interlayer conductive pattern layers, the interlayer insulating layers include insulating through-holes, the insulating through-holes expose glass through-holes electrically connected to the interlayer conductive pattern layers; the second insulating layer is used to fill the gaps in the second conductive pattern layer.

[0070] Specifically, the first conductive pattern layer and the second conductive pattern layer are both conductive patterns, not entire metal layers. The thickness of the first insulating layer can be equal to or slightly greater than the thickness of the first conductive pattern layer, and the thickness of the second insulating layer can be equal to or slightly greater than the thickness of the second conductive pattern layer. The thickness of the interlayer insulating layer can also be equal to or slightly greater than the thickness of the interlayer conductive pattern layer.

[0071] Providing a first insulating layer to fill areas of the first conductive pattern layer without conductive patterns can alleviate the problem of the first conductive pattern layer being prone to short circuits. Providing a second insulating layer to fill areas of the second conductive pattern layer without conductive patterns can alleviate the problem of the second conductive pattern layer being prone to short circuits. An interlayer insulating layer covering the interlayer conductive pattern layer can provide support and alleviate the problem of the interlayer conductive pattern layer being prone to short circuits. The interlayer insulating layer covers its corresponding conductive pattern layer but does not cover the glass through-holes electrically connected to the conductive pattern layer. The insulating through-holes expose the glass through-holes, thereby ensuring that the interlayer conductive pattern layer can communicate normally with other conductive pattern layers.

[0072] Figure 6 is a flow chart of a method for manufacturing a wafer-level chip integrated structure according to an embodiment of the present invention, with reference to Figure 6 The method for manufacturing a wafer-level chip integrated structure provided in this embodiment includes the following steps:

[0073] S110. Form a glass substrate, wherein the glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer through the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the interlayer conductive pattern layers and the interlayer glass bodies are alternately stacked; and the film layer close to the first conductive pattern layer and the film layer close to the second conductive pattern layer in the interlayer substrate are both interlayer glass bodies.

[0074] S120 , forming a chip unit layer electrically connected to the first conductive pattern layer on a side of the first conductive pattern layer away from the interlayer substrate, wherein the chip unit layer includes a plurality of semiconductor chips.

[0075] S130 , forming a conductive protrusion layer electrically connected to the second conductive pattern layer on a side of the second conductive pattern layer away from the interlayer substrate.

[0076] S140 , forming a device module layer electrically connected to the conductive protrusion layer on a side of the conductive protrusion layer away from the second conductive pattern layer.

[0077] The manufacturing method of a wafer-level chip integrated structure provided in this embodiment has corresponding beneficial effects as the wafer-level chip integrated structure provided in any embodiment of the present invention. For technical details not detailed in this embodiment, please refer to the wafer-level chip integrated structure provided in any embodiment of the present invention.

[0078] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0079] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A wafer-level integrated structure, characterized in that: include: A glass substrate, the glass substrate comprising a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer via the interlayer substrate; the interlayer substrate comprises at least one interlayer conductive pattern layer and at least two interlayer glass bodies; The interlayer conductive pattern layer and the interlayer glass body are alternately stacked; the film layer close to the first conductive pattern layer and the film layer close to the second conductive pattern layer in the interlayer substrate are both the interlayer glass body; a chip unit layer, located on a side of the first conductive pattern layer away from the interlayer substrate and electrically connected to the first conductive pattern layer; the chip unit layer includes a plurality of semiconductor chips; a conductive protrusion layer, located on a side of the second conductive pattern layer away from the interlayer substrate and electrically connected to the second conductive pattern layer; The device module layer is located on a side of the conductive protrusion layer away from the second conductive pattern layer and is electrically connected to the conductive protrusion layer.

2. The wafer-level integrated structure according to claim 1, wherein: The plurality of semiconductor chips include a plurality of computing chips and a plurality of memory chips; The computing chip and the storage chip are connected and communicated with each other via the glass substrate; The computing chips are connected and communicated with each other through the glass substrate.

3. The wafer-level integrated structure according to claim 1, wherein: The device module layer includes a plurality of power modules; The power supply module is used to supply power to the chip unit layer, and the power supply direction of the power supply module to the chip unit layer is the thickness direction of the glass substrate.

4. The wafer-level integrated structure according to claim 3, wherein: The device module layer further includes a plurality of passive components, a plurality of low-speed connectors and a plurality of high-speed connectors; The low-speed connector is adjacent to the power module; A vertical projection of the high-speed connector on the glass substrate is located at an edge region of the glass substrate.

5. The wafer-level integrated structure according to claim 1, wherein: Also included is a metal bump layer; The metal bump layer is located between the chip unit layer and the glass substrate; The chip unit layer is electrically connected to the first conductive pattern layer in the glass substrate through the metal bump layer.

6. The wafer-level integrated structure according to claim 1, wherein: Also includes a first heat dissipation layer and a second heat dissipation layer; The first heat dissipation layer is located on a side of the chip unit layer away from the glass substrate; The second heat dissipation layer is located on a side of the device module layer away from the conductive protrusion layer.

7. The wafer-level integrated structure according to claim 1, wherein: The glass substrate includes resistors and capacitors inside.

8. The wafer-level integrated structure according to claim 1, wherein: The interlayer substrate further includes at least one entire metal layer.

9. The wafer-level integrated structure according to any one of claims 1 to 8, characterized in that: The glass substrate further includes a first insulating layer, a second insulating layer and at least one interlayer insulating layer; The first insulating layer is used to fill the gaps in the first conductive pattern layer; The number of interlayer insulating layers is equal to the number of interlayer conductive pattern layers, the interlayer insulating layers correspond to the interlayer conductive pattern layers one by one, the interlayer insulating layers are used to cover the corresponding interlayer conductive pattern layers, the interlayer insulating layers include insulating through holes, and the insulating through holes expose glass through holes electrically connected to the interlayer conductive pattern layers; The second insulating layer is used to fill gaps in the second conductive pattern layer.

10. A method for manufacturing a wafer-level integrated structure, characterized in that: include: A glass substrate is formed, wherein the glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer through the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the interlayer conductive pattern layers and the interlayer glass bodies are alternately stacked; and a film layer in the interlayer substrate close to the first conductive pattern layer and a film layer close to the second conductive pattern layer are both the interlayer glass bodies; forming a chip unit layer electrically connected to the first conductive pattern layer on a side of the first conductive pattern layer away from the interlayer substrate, wherein the chip unit layer includes a plurality of semiconductor chips; forming a conductive protrusion layer electrically connected to the second conductive pattern layer on a side of the second conductive pattern layer away from the interlayer substrate; A device module layer electrically connected to the conductive protrusion layer is formed on a side of the conductive protrusion layer away from the second conductive pattern layer.

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