Package and method of manufacturing same

Abstract

A package includes: a carrier; the first chip is provided with an integrated transistor and comprises a second terminal, a third terminal and a first terminal attached to the carrier, the first terminal and the third terminal are formed on one main surface of the first chip, the second terminal is formed on the other opposite main surface of the first chip, and the third terminal is formed on the other opposite main surface of the first chip. The first terminal is a source or emitter terminal, the second terminal is a drain or collector terminal, and the third terminal is a gate or base terminal; a conductive structure at least partially conductive and attached to the second terminal; an encapsulation material at least partially encapsulating the carrier, the first chip, and the conductive structure; and an insulating layer disposed on a surface portion of the electrically conductive structure or of the carrier, the surface portion being exposed outside the encapsulation material, where the insulating layer is thermally conductive and electrically insulating.

Description

Technical Field

[0001] The present invention relates to a package and a method for manufacturing the package. Background Art

[0002] Packages, for example for automotive applications, provide physical protection for one or more electronic chips including one or more integrated circuit components. Examples of integrated circuit components of a package are metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and diodes.

[0003] There is still potential room for improvement in the electrical performance and thermal reliability of the package. Summary of the invention

[0004] A package having high electrical performance and thermal reliability may be desired.

[0005] According to an exemplary embodiment, a package is provided, which includes: a carrier; a first chip having an integrated transistor and including a second terminal, a third terminal and a first terminal attached to the carrier, wherein the first terminal and the third terminal are formed on one main surface of the first chip, and the second terminal is formed on another main surface opposite to the first chip, wherein the first terminal is a source or emitter terminal, the second terminal is a drain or collector terminal, and the third terminal is a gate or base terminal; a conductive structure that is at least partially conductive and attached to the second terminal; an encapsulation material that at least partially encapsulates the carrier, the first chip and the conductive structure; and an insulating layer arranged on a surface portion of the conductive structure or the carrier, the surface portion being exposed outside the encapsulation material, wherein the insulating layer is thermally conductive and electrically insulating.

[0006] According to another exemplary embodiment, a method for manufacturing a package is provided, wherein the method comprises: attaching a first terminal of a first chip having an integrated transistor to a carrier; providing a second terminal and a third terminal for the first chip, wherein the first terminal and the third terminal are formed on one main surface of the first chip, and the second terminal is formed on another main surface opposite to the first chip, wherein the first terminal is a source or emitter terminal, the second terminal is a drain or collector terminal, and the third terminal is a gate or base terminal; attaching an at least partially conductive conductive structure to the second terminal; at least partially encapsulating the carrier, the first chip and the conductive structure by an encapsulation material; and arranging an insulating layer on a surface portion of the conductive structure or the carrier, the surface portion being exposed outside the encapsulation material, wherein the insulating layer is thermally conductive and electrically insulating.

[0007] According to an exemplary embodiment, an encapsulated package includes a carrier, a conductive structure and a first chip, which can be implemented as a field effect transistor chip or a bipolar transistor chip. Two chip terminals can be located on one side of the first chip, and a third terminal can be located on the other side opposite to the first chip. Advantageously, a thin insulating layer providing thermal conductivity can be arranged on an exposed surface portion of the conductive structure or the carrier. Such a thin thermally conductive and electrically insulating layer can reliably electrically insulate the carrier or the conductive structure from the outside of the package, and at the same time can help remove heat from the inside of the package when the encapsulated first chip generates heat during operation. Advantageously, the first chip can be arranged in a source-down (or emitter-down) configuration, wherein the thin insulating layer can be placed on an exposed carrier (e.g., a lead frame) or a conductive structure (e.g., a clip). This configuration can provide a package with excellent electrical and thermal reliability, which can be manufactured in a compact design.

[0008] In one embodiment, if one of the conductive structure or the carrier on which the insulating layer is arranged is controlled to be at a fixed potential during operation of the package, this can effectively suppress capacitive coupling with a metal heat sink, which can be attached to the other side opposite to the insulating layer. Therefore, a package with a thin insulating layer providing appropriate performance can be manufactured in a simple and compact manner. More specifically, with a fixed potential on such a capacitor, induced currents and EMI (electromagnetic interference) can be suppressed or even prevented.

[0009] Description of Further Exemplary Embodiments

[0010] In the following, further exemplary embodiments of the package and the method will be explained.

[0011] In the context of the present application, the term "package" may particularly denote an arrangement which may comprise, for example, one or two chips mounted on a (particularly partially or fully conductive) carrier. The components of the package may optionally be at least partially encapsulated by an encapsulation material. Furthermore, the connection structure may form part of the package.

[0012] In the context of the present application, the term "carrier" may particularly refer to a support structure (which may be at least partially conductive) that serves as a mechanical support for the (one or more) electronic chips to be mounted thereon, and the support structure may also facilitate electrical interconnection between the (one or more) electronic chips and the periphery of the package. In other words, the carrier may implement a mechanical support function and an electrical connection function. The carrier may include or consist of a single component, a plurality of components bonded via encapsulation materials or other package components, or a subassembly of the carrier. When the carrier forms part of a lead frame, the carrier may be or may include a die pad. For example, such a carrier may be a lead frame structure (e.g., made of copper), a DAB (Direct Aluminum Bonding) substrate, a DCB (Direct Copper Bonding) substrate, etc. In addition, the carrier may also be configured as an active metal brazing (AMB: Active Metal Brazing) substrate.

[0013] In the context of the present application, the term "chip" may particularly denote a semiconductor chip (particularly a power semiconductor chip). The chip may be an active electronic device. In particular, the chip may be a semiconductor chip having at least one integrated circuit element (e.g. a transistor) in its surface portion. The chip may be a bare die or may have been packaged or encapsulated. The semiconductor chip implemented according to the exemplary embodiment may be formed, for example, with silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0014] In the context of the present application, the term "chip with integrated transistors" may particularly denote a chip, such as a semiconductor chip, in which at least a transistor may be integrated, in particular monolithically integrated. Optionally, the chip may include at least one further integrated circuit element, such as a diode or a further transistor. In particular, the corresponding chip with integrated transistors may be a field effect transistor chip with a source terminal (or pad), a drain terminal (or pad) and a gate terminal (or pad). Alternatively, the corresponding chip with integrated transistors may be a bipolar transistor chip with an emitter terminal (or pad), a collector terminal (or pad) and a base terminal (or pad). Specific examples of transistor chips are metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

[0015] In the context of the present application, the term "conductive structure" may particularly denote one or more electrical conductors or elements. Thus, the conductive structure may consist of one or more conductive elements (e.g. metal pillars, bumps and / or clips) and may be implemented in a package, e.g. for electrically coupling and / or mechanically supporting one or more chips. Preferably, the conductive structure may comprise one or two clips. A "clip" may particularly denote a three-dimensionally curved connecting element, which comprises a conductive material such as copper and is an integral body having sections to be connected to chip terminals and / or chip carriers and / or leads.

[0016] In the context of the present application, the term "encapsulation material" may particularly denote a material, structure or component that surrounds at least a portion of a transistor chip and at least a portion of a carrier to provide mechanical protection and optionally provide electrical insulation and / or contribute to the removal of heat during operation. In particular, the encapsulation material may be primarily or even entirely electrically insulating, such as a molding compound. The molding compound may include a matrix of a flowable and hardenable material and filler particles embedded therein. For example, filler particles may be used to adjust the properties of the molded component, in particular to enhance thermal conductivity. As an alternative to a molding compound (e.g. based on epoxy resin), the encapsulation material may also be a potting compound (e.g. based on silicone gel).

[0017] In the context of the present application, the term "insulating layer" may particularly denote a flat film having electrically insulating properties. At the same time, the insulating layer may be thermally conductive, i.e. capable of conducting heat. The insulating layer may be embodied as a single insulating film, for example a single layer. Alternatively, the insulating layer may be a stack of two or more electrically insulating materials. The insulating layer may also consist of at least two separate island-shaped insulating elements or segments. For example, the insulating layer may comprise ceramics, organic materials, thermal interface materials and / or electrically insulating foils (e.g. made of Kapton).

[0018] In the context of the present application, the term "main surface" of a body may particularly denote one of the largest body surfaces. For example, a body (e.g. a clip or a carrier or a chip or a part thereof) may be plate-shaped or substantially plate-shaped and may have two opposite main surfaces separated in the thickness direction by body material and connected to each other by a circumferential edge. For example, one main surface of the body may be at least partially exposed. Additionally or alternatively, one main surface of the body (e.g. another main surface) may be connected to one or more chips.

[0019] In one embodiment, the carrier comprises a lead frame structure or a laminate, such as a printed circuit board (PCB).

[0020] In the context of the present application, the term "lead frame" may particularly denote a sheet metal structure, which may be bent, stamped and / or patterned so as to form a lead frame body as a mounting section for mounting a chip and connecting leads for electrically connecting the package to an electronic environment. In one embodiment, the lead frame may be a metal plate (in particular made of copper), which may be patterned, for example, by stamping or etching. Forming the chip carrier as a lead frame is cost-effective and a mechanically and electrically highly advantageous configuration, in which a low-ohmic connection of the chip may be combined with the solid supporting capabilities of the lead frame. In addition, the lead frame may contribute to the thermal conductivity of the package and may remove heat generated during operation of the chip due to the high thermal conductivity of the metal (in particular copper) material of the lead frame.

[0021] In the context of the present application, the term "laminate" may particularly denote a carrier formed as a stack of a plurality of interconnected layers, such as metal foil or deposited metal layers and dielectric layers, such as including resins. The laminate may be formed by heating and / or pressing the individual layers together, such as for curing the resin, thereby interconnecting the individual layers. An example of a laminate is a PCB.

[0022] In one embodiment, the carrier has an electrical wiring structure extending between two opposite main surfaces of the carrier and connecting the first terminal to the first terminal lead and the third terminal to the third terminal lead. For example, a metal through-connection structure can be formed to extend vertically through the carrier. Such a through-connection structure can include, for example, stacked metal vias and / or metal pillars. The electrical wiring structure can also include, for example, horizontal metal sections of a patterned metal layer. The electrical wiring structure can allow current to be vertically conducted through the carrier along a short and well-defined path to provide current at the bottom main surface of the carrier. In such an embodiment, the package can be an SMD (surface mounted device) package having source and gate terminals at the bottom.

[0023] In one embodiment, at least a portion of the first terminal lead and the third terminal lead are exposed relative to the encapsulation material for attachment to a mounting base, such as a printed circuit board (PCB). In a single-chip package, a mounting base such as (e.g., an additional) PCB may be provided at the bottom side of the carrier for further processing of signals from the first terminal and the third terminal, respectively, disposed at the first terminal lead and the third terminal lead. This may contribute to a compact design of the package and low-loss transmission of electrical signals.

[0024] In one embodiment, the carrier comprises at least one thermal channel for dissipating heat from the first chip to a side of the carrier facing away from the conductive structure. In addition to the electrical routing capabilities of the carrier, the carrier may also be provided with an array of parallel thermal vias (e.g. filled with copper) or the like extending vertically through the carrier to remove heat generated by the encapsulated chip during operation of the package. This may improve the thermal performance of the package.

[0025] In one embodiment, the conductive structure comprises a lead frame structure or a clip.Preferably, the conductive structure comprises one integrated clip or two separate clips for attachment to respective sides of one or more chips.

[0026] In one embodiment, the conductive structure protrudes from the encapsulation material and serves as a second terminal lead (i.e., for connection to the drain terminal). Thus, the conductive structure can not only be coupled to the one or more chips, but can also provide the additional function of one or more leads, which extend out of the encapsulation material and allow the second terminal of the first chip connected to the conductive structure to be coupled to a peripheral device of the package.

[0027] In one embodiment, the package includes a heat sink attached to the insulating layer. A suitable heat sink may be a heat sink, which may be made of a highly thermally conductive material such as copper or aluminum. For example, such a heat sink may have a base facing the insulating layer and may have a plurality of cooling fins extending from the base and parallel to each other to remove heat to the environment.

[0028] In one embodiment, the package comprises a second chip having an integrated transistor and comprising a fourth terminal, a sixth terminal and a fifth terminal attached to the carrier, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip, and the fifth terminal is formed on another main surface opposite to the second chip, wherein the fourth terminal is a source or emitter terminal, the fifth terminal is a drain or collector terminal, and the sixth terminal is a gate or base terminal, wherein the conductive structure is attached to the fourth terminal, and wherein the encapsulation material encapsulates at least a portion of the second chip. In short, a second chip electrically coupled to the first chip can be provided, and the second chip can be implemented as another field effect transistor chip or another bipolar transistor chip. The fifth terminal of the second chip, i.e., the drain (or collector) terminal, can be attached to the carrier. This can achieve a combination of a first chip with a source down and a second chip with a drain down. In addition, one of the first chip and the second chip can be a high-side chip of a half bridge, and the other can be a low-side chip of a half bridge, but other applications are also possible. When combining a first chip with source down and a second chip with drain down, the first terminal of the (e.g. low side) first chip and the fifth terminal of the (e.g. high side) second chip can be coupled to the carrier covered by a very thin insulating layer. The benefit of this configuration comes from the fact that when the package is in operation, the first terminal and the fifth terminal can have a fixed potential so that an external heat sink can be attached on top of the very thin insulating layer without risk of electrical breakdown. In a half-bridge package, the second chip can be a drain down bare die.

[0029] In one embodiment, the carrier comprises a first die pad on which the first chip is mounted, and comprises a separate second die pad on which the second chip is mounted, wherein the first die pad and the second die pad comprise a conductive material. Preferably, the first die pad and the second die pad form part of a lead frame structure. For example, the first die pad and the second die pad may form part of the same lead frame structure, but may be physically and electrically separated from each other. This allows different potentials to be applied to the first die pad and the second die pad.

[0030] In one embodiment, the insulating layer comprises a first insulating layer section located on the first die pad and comprises a separate second insulating layer section located on the second die pad. When different insulating layer sections are provided for the first die pad and the second die pad, the insulating layer only needs to be provided where needed, which contributes to the compactness of the package. In addition, the different insulating layer sections can be adjusted individually to suitably meet their respective requirements.

[0031] In another embodiment, the insulating layer is a single integral layer extending over the first die pad and over the second die pad. This may allow the package to be manufactured with a low effort, since only a single integral insulating layer needs to be manufactured, without patterning or the like. Furthermore, this may allow uniform electrical isolation characteristics to be obtained for the two die pads. For example, in Figure 5 In the embodiment, the single integral insulating layer may cover two fixed potential (DC+ and DC-) die pads.

[0032] In one embodiment, when the package is operated in a half-bridge configuration, the second terminal and the fourth terminal are configured as switch nodes of the package and therefore have a floating potential, the first terminal and the fifth terminal are configured to have a fixed potential, and the insulating layer is arranged on the first die pad and the exposed second die pad having a fixed potential and at least partially exposed from the encapsulation material. Therefore, each of the chips can include a fixed potential terminal located on the chip carrier (i.e., the first terminal of the first chip and the fifth terminal of the second chip) and a floating potential terminal (i.e., the second terminal of the first chip and the fourth terminal of the second chip) facing away from the chip carrier and connected to the conductive structure. In this case, the thermally conductive and electrically insulating layer arranged on the exposed surface portion of the chip carrier can be formed to have a very low thickness, for example in the range of 10μm to 100μm. This is because the insulating layer faces the fixed potential side of the chip, which is not prone to electrical breakdown. Therefore, a very thin insulating layer may be sufficient for this package configuration. A parasitic capacitor is formed using the carrier (or conductive structure), the insulating layer and the external heat sink. With a fixed DC potential across the capacitor, induced currents and EMI (Electromagnetic Interference) can be suppressed or even prevented.

[0033] In one embodiment, the conductive structure includes a conductive element connected to the first chip and another conductive element connected to the second chip, wherein the package body further includes a second terminal lead, a fourth terminal lead and a connecting element, wherein the conductive element is connected to the second terminal lead, wherein the other conductive element is attached to the fourth terminal and connected to the fourth terminal lead, and wherein the connecting element is embedded inside the encapsulation material and connects the second terminal lead to the fourth terminal lead via the inside of the package body. For example, in Figure 6A corresponding embodiment is shown in FIG. In this configuration, each of the chips may be provided with a separate conductive element, wherein the electrical coupling between the conductive elements may be achieved by wire connection elements arranged to be encapsulated in the encapsulation material. This approach allows coupling of the individual conductive elements with short electrical paths and a small manufacturing effort.

[0034] In one embodiment, the second terminal lead and the fourth terminal lead are arranged on the first side of the package body, and the first terminal lead and the fifth terminal lead are arranged on the opposite second side of the package body. This design can make the spatial distance between the mentioned leads located at the two opposite sides of the package body large, which can suppress the undesirable electrical interaction between the mentioned leads at the two opposite sides of the package body.

[0035] In one embodiment, at least one of the conductive element and the further conductive element comprises a clip. Thus, two separate clips may be provided for forming the conductive element with a reasonable amount of effort.

[0036] In one embodiment, the package body comprises a direct connection structure arranged to directly electrically connect the second terminal and the fourth terminal inside the encapsulation material. For example, such a direct connection structure can be implemented as a metal loop for providing a short electrical path between the second terminal and the fourth terminal.

[0037] In one embodiment, the conductive structure comprises an integrated clip contacting the second terminal and the fourth terminal. Figure 8 and Fig. 9 In the configuration shown in , the conductive structure can be implemented as a continuous, one-piece conductive body. This allows for low wiring effort inside the package.

[0038] In one embodiment, the carrier comprises an integrated die pad of a lead frame, wherein the first terminal and the fifth terminal are attached to the integrated die pad, wherein the integrated die pad protrudes out of the encapsulation material and forms a first terminal lead and a fifth terminal lead of the package, wherein a conductive element of the conductive structure is attached to the second terminal and connected to the second terminal lead, and wherein another conductive element of the conductive structure is attached to the fourth terminal and connected to the fourth terminal lead. In e.g. Fig.12 In the configuration shown, the carrier can be implemented as a continuous, one-piece electrical conductor. This allows for a low wiring effort inside the package.

[0039] In one embodiment, at least a portion of the conductive element and the further conductive element are exposed relative to the encapsulation material, wherein the insulating layer covers the exposed surface of the conductive element and the further conductive element. By exposing the conductive structure or a portion of the conductive structure relative to the encapsulation material and by covering the exposed surface with the insulating layer, high electrical reliability and high thermal performance can be achieved simultaneously due to the heat dissipation capability of the conductive structure being located very close to the external surface of the package. A heat sink can be attached to such a dielectric layer to further increase thermal performance.

[0040] In one embodiment, the insulating layer comprises a first insulating layer section located on the conductive element and comprises a separate second insulating layer section located on the further conductive element. When different insulating layer sections are provided for the conductive element and the further conductive element, the insulating layer only needs to be provided where it is needed, which contributes to the compactness of the package. Furthermore, the different insulating layer sections can be adjusted individually to suitably meet their respective requirements.

[0041] In one embodiment, when the package is operated in a half-bridge configuration of the first chip and the second chip, the first terminal lead and the fifth terminal lead are configured as switch nodes and have a floating potential, and wherein the package includes a second terminal lead connected to the conductive element and includes a fourth terminal lead connected to the other conductive element, the second terminal lead and the fourth terminal lead having a fixed potential. Therefore, each of the chips may include a fixed potential terminal located on the conductive structure (i.e., the second terminal of the first chip and the fourth terminal of the second chip) and a floating potential terminal (i.e., the first terminal of the first chip and the fifth terminal of the second chip) away from the conductive structure and connected to the carrier. In this case, the thermally conductive and electrically insulating layer arranged on the exposed surface portion of the conductive structure can be formed to have a very low thickness in the range of from 10 μm to 100 μm. This is because the insulating layer faces the fixed potential side of the chip, which is not prone to electrical breakdown. Therefore, a very thin insulating layer may be sufficient for such a package configuration. By means of a fixed potential across a capacitor formed by an insulating layer with a carrier or conductive structure on one side and a heat sink on the other side, induced currents and electromagnetic interference can be suppressed or even prevented.

[0042] Still referring to the aforementioned embodiment, the first chip may be a source-down chip and may be used as a high-side chip, and the second chip may be a drain-down chip and may be used as a low-side chip. Figures 10 to 12 Such an embodiment is shown in .

[0043] As already mentioned, the first chip and the second chip can be connected to form a half-bridge. In the context of the present application, the term "half-bridge" can particularly denote a circuit consisting of an upper transistor switch ("high side") and a lower transistor switch ("low side"). For example, the transistor can be a MOSFET, i.e. a metal oxide semiconductor field effect transistor. The transistor can be connected in a common source and common gate arrangement. By applying a corresponding voltage waveform at the control terminal, the two transistor switches can be turned on and off complementary to each other (especially with non-overlapping dead times). The desired result can be an idealized DC-DC conversion scenario, in which a square wave intermediate voltage level switches between a first potential (e.g., a DC (direct current) bus voltage) and a second potential (e.g., ground). However, other shapes of output signals that do not have square wave characteristics are also possible. The two transistors can be interconnected by mutual connection of their connection terminals, so that a switch based on two transistors with an implemented diode characteristic can be obtained. The mentioned half-bridge configuration can be used as such or alone, or can be combined with one or more additional half-bridges (or other circuits) to achieve more complex electrical functions. For example, two such half-bridges can form a full bridge.

[0044] In one embodiment, the first chip is a source-down chip and serves as a low-side chip, and the second chip is a drain-down chip and serves as a high-side chip. Figures 5 to 9 A corresponding embodiment is shown in FIG.

[0045] In one embodiment, at least a portion of the conductive structure is exposed from the encapsulating material at a surface opposite to another surface where at least a portion of the carrier is exposed from the encapsulating material, wherein the insulating layer is arranged on the exposed surface of at least a portion of the carrier, wherein the package comprises an additional insulating layer arranged on the exposed surface of the conductive structure, and wherein the thickness of the additional insulating layer is greater than the thickness of the insulating layer. Thus, the package can be configured for double-sided cooling. In this configuration, both the carrier and the conductive structure can be exposed relative to the encapsulating material and can be covered with corresponding insulating layers. When the fixed potential exists on the carrier side and the floating potential exists on the conductive structure side, a thinner insulating layer on the carrier side may be sufficient. A thin insulating layer is advantageous, but it will produce capacitance. However, if it only has a fixed or DC potential, this is not a disadvantage.

[0046] In another embodiment, at least a portion of the conductive structure is exposed from the encapsulation material at a surface opposite to another surface of the carrier at least a portion of which is exposed from the encapsulation material, wherein the insulating layer is arranged on the exposed surface of at least a portion of the conductive structure, wherein the package comprises an additional insulating layer arranged on the exposed surface of the carrier, and wherein the thickness of the additional insulating layer is greater than the thickness of the insulating layer. When the fixed potential is present on the conductive structure side and the floating potential is present on the carrier side, a thinner insulating layer on the conductive structure side may be sufficient.

[0047] In one embodiment, one of the conductive structures (which may, for example, consist of different conductive elements, or it may be an integral clip) or the carrier (which may, for example, consist of different die pads, or it may be an integral carrier) on which an insulating layer is arranged (for example by direct physical contact) is at at least one fixed potential (for example at two different fixed potentials) during operation of the package. In contrast, the other of the conductive structures or the carrier on which no insulating layer is arranged may be at at least one floating potential (for example corresponding to a switching node of a half-bridge) during operation of the package. Advantageously, this may result in a reduction in capacitive coupling caused by parasitic capacitors between a metal heat sink formed on the insulating layer and a metal carrier or electrical conductor on the other side opposite the insulating layer. Thus, the insulating layer may be formed very thin.

[0048] In one embodiment, the package is configured to apply the fixed potential to one of the conductive structures or the carrier on which the insulating layer is arranged, for suppressing capacitive coupling. More specifically, this can be done to suppress capacitive coupling between a carrier or conductive structure attached to one side of the insulating layer and a heat sink attached to the other side of the insulating layer. In short, this can allow a reduction in capacitive coupling between a package carrier (or conductive structure) and a heat sink, wherein the insulating layer is located between the package carrier (or conductive structure) and the heat sink.

[0049] Therefore, a preferred feature of the exemplary embodiments is to apply a thin insulating layer to a fixed potential of the half-bridge package. This can suppress the undesirable phenomenon of parasitic capacitors (using the insulating layer as a capacitor dielectric) and can result in less unintentional current induction and proper EMI behavior.

[0050] In one embodiment, the insulating layer has a thickness in the range of 10 μm to 100 μm and comprises a ceramic material (eg, aluminum oxide, aluminum nitride, boron nitride and / or aluminum oxynitride) or an organic material (eg, prepreg).

[0051] More generally, the insulating layer may have a thickness in the range of 1 μm to 500 μm, for example in the range of 15 μm to 70 μm or in the range of 20 μm to 50 μm. In particular, due to the configuration of the package according to example embodiments, a smaller thickness range may become possible.

[0052] In one embodiment, the package has a voltage rating in the range of 650 V to 2000 V. Due to the good protection of the package against creepage currents and electrical breakdown, the package meets even demanding requirements regarding electrical stability. To increase high voltage ratings, the encapsulation material may also be provided with one or more creepage distance increasing grooves for extending the length and complexity of the creepage path along the outside of the package.

[0053] In one embodiment, the insulating layer has a thermal conductivity of at least 1 W / mK, such as at least 50 W / mK, preferably at least 100 W / mK. Thus, the thermal conductivity of the material of the insulating layer can be significantly better than the thermal conductivity of a typical molding compound. Thus, the insulating layer can significantly contribute to removing heat from the package.

[0054] For example, the encapsulation material may be implemented as a single encapsulation covering all mentioned elements. Alternatively, separate encapsulations may be provided for different chips.

[0055] In one embodiment, the encapsulating material is selected from the group consisting of a molding compound and a laminate. For encapsulation by molding, a plastic material or a ceramic material can be used. The encapsulating material may include an epoxy resin material. For example, filler particles (such as SiO2, Al2O3, Si3N4, BN, AlN, diamond, etc.) for improving thermal conductivity can be embedded in the epoxy matrix of the encapsulating material.

[0056] In one embodiment, the package is configured as a tie-bar-less package. In such an embodiment, the entire package may be completely free of any tie-bars. This may simplify the manufacturing process and may improve the electrical reliability of the package, as there is no metal tie-bar material to form part of the outer surface of the package. The absence of tie-bars at the package surface may improve electrical reliability. Tie-bar-less embodiments may be advantageous when high voltages are used.

[0057] However, embodiments without or with tie bars are possible. For example, in a split die pad design, tie bars may be present to avoid significant mold flash due to die pad tilting during molding. Here, methods such as retractable pins, vacuum molding tools, etc. may be advantageous.

[0058] In one embodiment, the first chip and the second chip are made of the same chip technology. The first chip and the second chip can even be the same. In one embodiment, the first chip and the second chip have the same shape and size. In other words, the first chip and the second chip can be substantially the same semiconductor chip. When the two chips (providing transistors) of a half-bridge package are identical in shape, size and electrical properties, it is sufficient to provide only one type of transistor chip to manufacture the package. The advantage of this measure is simplicity. Using only one type of chip to provide the transistor function keeps the manufacturing workload of the package at a low level.

[0059] Alternatively, the first chip and the second chip may have at least one of a different shape and a different size. Thus, the two chips may also have different sizes and / or different electrical properties, for example to take into account different duty cycles of the chips, or to achieve separate optimizations for DC-DC functions. For example, in an asymmetric half-bridge, the high-side chip and the low-side chip may have different sizes to allow the die that is in the ON state for a longer time to have a lower RDSON.

[0060] In one embodiment, at least one of the first chip and the second chip is configured to operate with vertical current flow, in particular current flow perpendicular to a plane in which the carrier and / or the conductive structure extends. The chip configured for vertical current flow may have transistor terminals at both the upper main surface and the lower main surface of the chip, respectively. In particular, in such a vertical flow configuration, the package can be formed to have an extremely short current path and thus a very simple layout.

[0061] The described circuit architecture with a single chip and two chips connected to form a half bridge can be implemented by many different package types. More specifically, various different package architectures are compatible with the described connection architecture with a compact layout and short electrical paths. For example, the PQFN package type is compatible with the described connection technology, and the HSOF package is also compatible with the described connection technology. In other embodiments, a dual side small outline (DSO) package can be provided. In addition, according to an exemplary embodiment, a quad package (having pins on all four sides of the package) can be formed. Therefore, the mentioned layout design can be easily adapted to various different packaging technologies.

[0062] In one embodiment, one or more chips with transistors are configured as power semiconductor chips. Therefore, the corresponding chip (e.g., semiconductor chip) can be used for power applications in, for example, the automotive field, and can, for example, have at least one integrated insulated gate bipolar transistor (IGBT) and / or at least one transistor of another type (e.g., MOSFET, JFET, etc.). Such integrated circuit components can be made, for example, in silicon technology or based on wide bandgap semiconductors (e.g., silicon carbide, gallium nitride, or silicon-based gallium nitride). The semiconductor power package can include inverter circuits, half bridges, full bridges, drivers, logic circuits, etc.

[0063] As a substrate or wafer forming the basis of one or more chips, a semiconductor substrate, preferably a silicon substrate, may be used. Alternatively, a silicon oxide or another insulator substrate may be provided. A germanium substrate or a III-V semiconductor material may also be implemented. For example, exemplary embodiments may be implemented with GaN or SiC technology.

[0064] The above and other objects, features and advantages of the present invention will become apparent from the following description and appended claims taken in conjunction with the accompanying drawings in which like parts or elements are designated by like reference numerals. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of this specification, illustrate exemplary embodiments.

[0066] In the attached picture:

[0067] Figure 1 A cross-sectional view of a package and its details according to an exemplary embodiment is shown.

[0068] Figure 2 Shown according to Figure 1 A 3D view of the package.

[0069] Figure 3 Shown according to Figure 1 A top view of the package body.

[0070] Figure 4 Shown according to Figure 1 Bottom view of the package body.

[0071] Figure 5 A schematic circuit diagram of a package having an interconnect structure according to another exemplary embodiment is shown.

[0072] Figure 6 Shown according to Figure 5 A three-dimensional perspective view of the package.

[0073] Figure 7A schematic circuit diagram of a package having an interconnect structure according to yet another exemplary embodiment is shown.

[0074] Figure 8 Shown according to Figure 7 A three-dimensional perspective view of the package.

[0075] Fig. 9 Shown according to Figure 7 Another 3D perspective view of the package.

[0076] Fig.10 A schematic circuit diagram of a package having an interconnect structure according to yet another exemplary embodiment is shown.

[0077] Fig.11 Shown according to Fig.10 A 3D opaque view of the package.

[0078] Fig.12 Shown according to Fig.10 A three-dimensional perspective view of the package.

[0079] Fig.13 Shown as Figure 5 and Figure 6 A cross-sectional view of a package body of a variant of an embodiment.

[0080] Fig.14 Shown as Figures 7 to 9 A cross-sectional view of a package body of a variant of an embodiment.

[0081] Fig.15 Shown as Figures 10 to 12 A cross-sectional view of a package body of a variant of an embodiment. DETAILED DESCRIPTION

[0082] The illustrations in the drawings are schematic.

[0083] Before describing further exemplary embodiments in more detail, some basic considerations based on which exemplary embodiments have been developed will be outlined.

[0084] According to an exemplary embodiment, a package includes a carrier, a conductive structure, and a first chip (e.g., a field effect transistor chip or a bipolar transistor chip) that can be encapsulated by an encapsulation material. The first chip can have terminals or pads at its two opposite main surfaces. At least one thermally conductive and electrically insulating layer located on the exposed surface portion of the conductive structure and / or the carrier can enhance the electrical reliability and thermal performance of the package. Preferably, a first chip with a source facing down (or an emitter facing down) can be provided, wherein a thin insulating layer can be formed on the exposed carrier (e.g., a lead frame) and / or the conductive structure (e.g., a clip). This can allow a high-performance and highly reliable package that can be manufactured with a reasonable amount of work to be provided.

[0085] In a preferred embodiment, the package may be a discrete package having a single encapsulated die (see Figures 1 to 4 ).

[0086] In other preferred embodiments (see Figures 5 to 12 ), the package additionally includes a second transistor chip having terminals formed on two opposite main surfaces thereof. In half-bridge applications, a combination of a first chip with a source electrode downward and a second chip with a drain electrode downward may be particularly preferred. The advantages of this embodiment can be attributed to an exemplary configuration in which the terminals of the first chip and the terminals of the second chip can have a fixed potential during operation, which allows the use of a very thin insulating layer on an exposed carrier or an exposed conductive structure connected to the fixed potential terminal without compromising electrical reliability and thermal performance. When the carrier or conductive structure is exposed here, a thicker insulating layer may be required on the side of the package corresponding to the floating terminal of the chip. Therefore, forming an insulating layer on the fixed potential side of the package can achieve a compact design and still have excellent electrical reliability and thermal reliability. Having an insulating layer on both the exposed carrier and the exposed conductive structure can achieve double-sided cooling.

[0087] In particular, the following four embodiments are provided:

[0088] The first embodiment involves a single die package having a source-down die and a thin insulating layer ( Figures 1 to 4 ).

[0089] The second to fourth embodiments relate to a half-bridge package:

[0090] Second embodiment ( Figure 5 and Figure 6 ) has: two separated die pads, one source down die used as low side die, one drain down die used as high side die. In addition, a thin insulating layer can be placed on the drain side of the high side die and the source side of the low side die. In addition, two separate clips can be integrated in the package.

[0091] Third embodiment ( Figures 7 to 9 ) has: two separated die pads; one source-down die used as a low-side die; one drain-down die used as a high-side die, with a thin insulating layer placed on the drain side of the high-side die and the source side of the low-side die; and a single integrated clip.

[0092] Fourth embodiment ( Figures 10 to 12) has: an integrated die pad, a source-down die used as a high-side die, a drain-down die used as a low-side die, two separate clips connected to two fixed potentials respectively, and one or two insulating layers covering the two clips.

[0093] According to an exemplary embodiment, capacitive displacement currents at thin package insulating layers can be avoided:

[0094] Power components are used to switch and control large currents and voltages. Therefore, they also generate losses, which require heat dissipation. The general trend of increasing power density makes heat dissipation more difficult. For many power components, the collector or drain or positive connection structure is mounted to a carrier, which can be a substrate or tin like a lead frame. This lead frame side acts as a heat sink and transfers the heat to a dissipation area like a heat sink, but since the component is handling high voltages, it needs to be isolated from the heat sink. However, the arrangement structure of lead frame-isolation structure-heat sink creates a parasitic capacitance. When the component switches continuously and the voltage moves up and down, which for high voltage isolation devices can be several thousand volts with fast transient times, there is a displacement current on this capacitor. This current can reach very high values ​​(such as several amperes) or charge and discharge the heat sink, in any case causing severe electromagnetic interference, endangering the normal function of the application. With respect to voltage isolation, for thermal management, the insulation layer should be as thin as possible, but in order to reduce the capacitor current, the insulation layer must be thick to reduce the capacitance to a tolerable value.

[0095] An exemplary embodiment provides a solution to reconcile these opposing requirements. A very thin insulating layer can be provided that can be attached to an exposed metal surface and is sufficiently stable for high voltage isolation. For example, such a thin insulating layer can be made of a ceramic material. A specific example of an insulating layer can be AlON deposited as a ceramic material on a copper lead frame with a layer thickness of 25 μm for isolation up to 1500V or more. The capacitance of such a layer can be 140 pF / cm 2 The resulting current Ic can be calculated from the equation Ic = C*dV / dt (C capacitance, V voltage, t time), and for the upcoming fast switching applications, dV / dt can even reach 100V / ns. With these values, a resulting peak current of 14A may occur.

[0096] Traditionally, this has not been as severe because lower switching speeds were used and processes for thin insulating layers were not yet available, but this is a problem when using modern components such as SiC chips.

[0097] As MOSFET switching speeds continue to increase, improving heat dissipation is required, and thin isolation materials and processes are advantageous. In order to avoid high currents in the range of several amperes, it may be advantageous to keep the potential variation of the connected lead frame low or zero. The source-down configuration can provide such conditions to utilize a thin insulating layer.

[0098] Applications according to exemplary embodiments can use one, two or three half-bridge configurations, where one switch is located on the high side (HS) and one switch is located on the low side (LS). The power switch can connect the collector or drain on its back side to the carrier (e.g. substrate or lead frame). The HS-emitter / source can then be connected to the LS-collector / drain. However, the collector / drain is located on the carrier side and may produce capacitance with the described negative effects. To avoid this, the LS emitter / source can be mounted on the carrier.

[0099] With this source-down design, only a DC potential (also indicated as fixed potential) can be present on the carrier side, and the HS-emitter / source and LS-collector / drain can be located on the upper side, both driving the load with rapidly changing potentials, but the back side / carrier layer remains at a DC level.

[0100] This approach may make it possible to apply a thin insulating layer to the other side of the carrier, since the resulting capacitance is only loaded by the direct voltage and there is then no significant voltage derivative at the carrier.

[0101] A corresponding approach can be applied to a single switch using a classical drain / collector-down switch and a source / emitter-down switch, both separated by a thin insulating layer.

[0102] Another embodiment involves a monolithically integrated GaN topology isolated by a very thin ceramic layer deposited on the lead frame.

[0103] Exemplary embodiments may utilize the fast switching capabilities of SiC MOSFETs to reduce losses. This may allow for the creation of an off-board charger. This may also allow for efficient heat dissipation.

[0104] One exemplary embodiment may provide a package that combines a source-down assembly with an insulating layer, for example, less than 50 μm thick, deposited on a lead frame. Use of a source-down configuration may enable implementation of a thin insulating layer to meet challenging low thermal resistance to a heat sink. The source-down design prevents system-level coupling capacitance issues.

[0105] The preferred thickness range of the insulating layer can be 10 μm to 50 μm, more preferably 10 μm to 30 μm. Preferably, the thickness of the insulating layer can be less than 200 μm. Suitable materials for the insulating layer can be ceramic aluminum oxide, aluminum nitride, aluminum oxynitride, boron nitride. However, organic materials can also be used as materials for the insulating layer. This can allow the manufacture of packages that meet the voltage level range from 650V to 2000V. The package according to the exemplary embodiment can reduce capacitance loss and can achieve compliance with stringent EMI (electromagnetic interference) requirements.

[0106] In the following description of the drawings, the exemplary embodiments will be described for field effect transistors having source, drain and gate terminals. However, those skilled in the art will appreciate that these and other embodiments may also be configured as bipolar transistors having emitter (instead of source), collector (instead of drain) and base (instead of gate) terminals.

[0107] Figure 1 A cross-sectional view of a single die package 100 and details 193 thereof is shown according to an exemplary embodiment. Figure 2 Shown according to Figure 1 A three-dimensional view of the package 100 is shown. Figure 3 Shown according to Figure 1 FIG. 1 is a top view of the package body 100 . Figure 4 Shown according to Figure 1 FIG. 1 is a bottom view of the package body 100 .

[0108] according to Figure 1 The package 100 of the embodiment of the present invention comprises a carrier 102, which is a laminated printed circuit board (PCB) here. The carrier 102 comprises a dielectric region 195 (e.g., comprising resin and glass fiber) and a metal region 197 (e.g., a patterned copper layer and copper vias or copper pillars). In short, the carrier 102 can be implemented as a PCB with an adapted contact layer. Advantageously, the carrier 102 implemented as a PCB or laminate can have the routability from the source / gate pads of the first chip 104 described below to the source / gate leads of the package 100.

[0109] A single or first chip 104 (which may be a power semiconductor die) is mounted on the carrier 102 and is provided with an integrated field effect transistor (or alternatively with an integrated bipolar transistor). The first chip 104 may be, for example, a semiconductor chip manufactured in silicon carbide or gallium nitride technology (for example implementing a vertical GaN chip architecture). The first chip 104 is assembled on the carrier 102, for example, by soldering or sintering.

[0110] The first chip 104 may be a power semiconductor transistor chip that may include a monolithically integrated MOSFET (or alternatively an IGBT) that is not shown. As shown in a separate illustration 199, the transistor of the first chip 104 may be monolithically integrated in a semiconductor body 154 that includes, for example, silicon or silicon carbide. The first chip 104 includes a first terminal 106 (a source terminal labeled S1) attached to the carrier 102. In addition, the first chip 104 includes a second terminal 108 (a drain terminal labeled D1) and a third terminal 110 (a gate terminal labeled G1). As shown in the illustration 199, the first terminal 106 and the third terminal 110 are formed on a common main surface of the first chip 104 facing the carrier 102. In contrast, the second terminal 108 is formed on another main surface of the first chip 104 that is opposite to the carrier 102. The first chip 104 may be configured to experience vertical current flow between its opposite main surfaces during operation of the package 100. A control signal may be applied to the third terminal 110 to control the operation of the first chip 104.

[0111] Furthermore, an optional source sense terminal may be provided at the first chip 104 , which is denoted as SS1 .

[0112] As described above, the first terminal 106 and the third terminal 110 are attached to the carrier 102. In contrast, the second terminal 108 may be attached to the conductive structure 103, which is implemented here as a metal clip. Thus, the first chip 104 may be implemented as a source-down die, the source pad and the gate pad of which are arranged on the bottom surface of the die and on the top surface of the carrier 102. The drain pad of the first chip 104 is arranged on the top side of the die.

[0113] The conductive structure 103 may be a lead frame, or Figure 1 As shown, it may be a clip. The conductive structure 103 is arranged on top of the drain pad of the source-down first chip 104 and extends out of the encapsulation material 138 as a drain lead.

[0114] The mold-type encapsulation material 138 encapsulates a portion of the carrier 102 , the entire first chip 104 , and a portion of the conductive structure 103 .

[0115] The upper major surface and lateral portions of the conductive structure 103 extend beyond the encapsulation material 138 and are exposed.

[0116] The insulating layer 142 is arranged on the exposed upper surface portion of the conductive structure 103. Advantageously, the insulating layer 142 can be provided with a very small vertical thickness D in the range of 10 μm to 100 μm. The insulating layer 142 can be thermally conductive and electrically insulating. For example, the insulating layer 142 can be made of a ceramic (e.g., boron nitride), an organic material (e.g., a prepreg), or a thermal interface material (TIM). Such a thermal interface material 142 can be, for example, a thermal paste that provides thermal coupling with the heat sink 146 with a low thermal resistance between the thermal interface material 142 and the heat sink 146. Due to the thermal conductivity of the insulating layer 142, the insulating layer 142 can contribute to the heat dissipation from the interior of the package 100, wherein the heat can be mainly generated by the first chip 104. In addition, the insulating layer 142 can contribute to electrical safety.

[0117] The portion of the conductive structure 103 that protrudes laterally from the encapsulation material 138 serves as a second terminal lead 159 , ie, a lead connected to the second terminal 108 .

[0118] For example, the heat sink 146 mentioned above may include a heat conducting plate 160, and a plurality of cooling fins 162 also made of a heat conducting material extend upward from the heat conducting plate 160. Preferably, the heat sink 146 may be made of metal or ceramic to provide high thermal conductivity. The heat generated by the first chip 104 may be dissipated to the environment, for example, by air cooling via the conductive structure 103, the insulating layer 142 and the heat sink 146. The heat sink 146 may also be implemented as a liquid cooler (for example, a water cooler), etc.

[0119] Referring again to the carrier 102, the carrier 102 has an electrical wiring structure 151 extending between two opposite main surfaces of the carrier 102 and connecting the first terminal 106 to the first terminal lead 153 and the third terminal 110 to the third terminal lead 155. The first terminal lead 153, i.e., the lead connected to the first terminal 106 and the third terminal lead 155, i.e., the lead connected to the third terminal 110 are exposed relative to the encapsulation material 138 to attach to the bottom side mounting base 191, such as another printed circuit board (PCB). The mounting base 191 can be connected to the encapsulation material 138 and the bottom main surface of the carrier 102.

[0120] In addition, the carrier 102 includes a plurality of parallel thermal channels 157 arranged below the first chip 104 and extending over the entire vertical extension of the carrier 102 for dissipating heat from the first chip 104 to a side of the carrier 102 facing away from the conductive structure 103. The thermal channels 157 may, for example, be implemented as thermal vias filled with copper material. In other words, the thermal channels 157 may be vias for heat transfer.

[0121] also, Figure 1Reference numeral 101 in FIG. 1 schematically shows a creepage current path, which is long and complex enough to effectively suppress the risk of creepage current.

[0122] The PCB type or laminated carrier 102 has at least one source lead, one gate lead, and an optional source sense lead on its bottom surface. The carrier 102 includes at least a first conductive path that connects the source pad of the first chip 104 from the top surface of the carrier 102 to the bottom surface of the carrier 102 and then to the source terminal of the package 100. In addition, the carrier 102 includes at least a second conductive path that connects the gate pad of the first chip 104 to the gate lead of the package 100. These conductive paths may include traces, vias, and pads located on at least one side of the carrier 102 and within the carrier 102. In addition, the first chip 104 may include a source sense pad, and the package 100 may have a source sense lead. In addition to this, the carrier 102 may include a third conductive path that connects the source sense pad and the source sense lead through the carrier 102. The source lead, the gate lead, and the source sense lead may be at least partially covered by an insulating material, such as a solder mask.

[0123] Figure 1 The package 100 shown is a SMD (surface mount device) package.The drain lead is arranged at a first side of the package 100 opposite to a second side where the source lead, the gate lead and the optional source sense lead are arranged.

[0124] therefore, Figure 1A semiconductor package 100 is shown that includes a carrier 102 and a first power semiconductor chip 104, the first power semiconductor chip 104 including a first terminal 106 and a third terminal 110 arranged on a first side of the first chip 104 and a second terminal 108 arranged on a second side of the first chip 104 opposite to the first side. The first terminal 106 includes an emitter terminal or a source terminal. The second terminal 108 includes a collector terminal or a drain terminal. The first terminal 106 is arranged to be attached to a first surface of the carrier 102. The conductive structure 103 is attached to the second terminal 108 of the first chip 104. The encapsulation material 138 is configured to encapsulate a portion of the carrier 102, the first chip 104 and a portion of the conductive structure 103. Another portion of the conductive structure 103 is exposed from the first surface of the package 100. An insulating layer 142 is arranged on the exposed surface of the conductive structure 103, wherein the insulating layer 142 includes a thermally conductive and electrically insulating layer. The insulating layer 142 may have a thickness D in the range of 10 μm to 100 μm, and may include a ceramic material (e.g., aluminum oxide, aluminum nitride, boron nitride, and / or aluminum oxynitride) or an organic material (e.g., prepreg). Alternatively, the insulating layer 142 may have a thickness D in the range of 1 μm to 500 μm, 15 μm to 70 μm, or 20 μm to 50 μm.

[0125] The carrier 102 comprises a PCB, a laminate or a lead frame. The carrier 102 can be configured to provide electrical wiring for connecting the first terminal 106 of the first chip 104 to the first terminal lead 153 of the package 100 and the third terminal 110 of the first chip 104 to the third terminal lead 155 of the package 100 from the first surface of the carrier 102 to the opposite second surface of the carrier 102. The carrier 102 also includes at least one thermal channel 157 for dissipating heat from the first chip 104 to the bottom of the package 100. At least a portion of the first terminal lead 153 and the third terminal lead 155 can be exposed from the bottom surface of the package 100 and will be electrically attached to another carrier in the form of a mounting base 191 (preferably a PCB). The conductive structure 103 comprises a clip or another lead frame, which protrudes from the encapsulation material 138 and serves as a second terminal lead 159 (i.e., as a collector lead or a drain lead) of the package 100. The heat sink 146 is attached to the insulating layer 142.

[0126] Next, the second, third and fourth embodiments mentioned above will be explained: each of the embodiments involves a first chip 104 and a second chip 112 connected in a half-bridge configuration and implemented as a high-side die and a low-side die. In some of these embodiments, the drain terminal D2 of the second chip 112 and the source terminal S1 of the first chip 104 are separated and can be covered by a (e.g., separated or continuous) thin insulating layer 142. Advantageously, when the package 100 is in operation, D2 and S1 can have a fixed potential. An external heat sink 146 can be attached to the top of the thin insulating layer 142. Terminals S2 and D1 can be connected to each other inside the package 100.

[0127] In the second embodiment ( Figure 5 and Figure 6 ), two separate die pads of carrier 102 can be exposed, and two separate clips of conductive structure 103 can be provided. First chip 104 can be arranged in source-down configuration, and can be used as low-side die. Second chip 112 can be arranged in drain-down configuration, and can be used as high-side die. These two die pads can have fixed potential and can be exposed, so a thin insulating layer 142 can be applied here.

[0128] In the third embodiment ( Figures 7 to 9 ), two separated die pads of carrier 102 can be exposed. An integrated clip can be foreseen as conductive structure 103. First chip 104 can be arranged in source down configuration and can be used as low side die. Second chip 112 can be arranged in drain down configuration and can be used as high side die. The two die pads can have a fixed potential and can be exposed, so a thin insulating layer 142 can be applied here.

[0129] In the fourth embodiment ( Figures 10 to 12 ), an integrated die pad may be provided as carrier 102. Two separate clips may be exposed and may form a conductive structure 103. The first chip 104 may be arranged in a source-down configuration and may be used as a high-side die. The second chip 112 may be arranged in a drain-down configuration and may be used as a low-side die. The two clips of the conductive structure 103 may have a fixed potential and may be exposed so that a thin insulating layer 142 may be applied on the clips.

[0130] In the context of this application, the term "source-down chip" may refer to a chip or die whose source pads or terminals are attached to a die pad or other type of carrier. Thus, if the source pad is attached to a clip, the corresponding chip will not be interpreted as a source-down die by a person skilled in the art.

[0131] Figure 5A schematic circuit diagram of a package 100 having an interconnect structure according to an exemplary embodiment is shown. Figure 6 Shown according to Figure 5 3D perspective view of the package body 100.

[0132] according to Figure 5 and Figure 6 The package 100 includes a lead frame type carrier 102 composed of a metal first die pad 150 and a separate metal second die pad 152 .

[0133] The first chip 104, which may be a power semiconductor chip, has an integrated field effect transistor. The first chip 104 includes a first terminal 106, which is a first source terminal S1, and the first terminal 106 is attached to a first die pad 150 of the carrier 102. A second terminal 108 as a first drain terminal D1 and a third terminal 110 as a first gate terminal G1 are also provided on the first chip 104. The first terminal 106 and the third terminal 110 are formed on one main surface of the first chip 104, while the second terminal 108 is formed on another opposite main surface of the first chip 104. The first chip 104 is configured for vertical current flow between the terminals on its opposite main surfaces.

[0134] In addition, according to Figure 5 and Figure 6 The package 100 includes a second chip 112 with an integrated transistor. The second chip 112 includes a fourth terminal 114 as a second source terminal S2, a fifth terminal 116 as a second drain terminal D2 and attached to the carrier 102, and a sixth terminal 118 as a second gate terminal G2. The fourth terminal 114 and the sixth terminal 118 are formed on one main surface of the second chip 112, while the fifth terminal 116 is formed on the other opposite main surface of the second chip 112. The fifth terminal 116 is attached to the second die pad 152 of the carrier 102. The second chip 112 is configured for vertical current flow between the terminals on its opposite main surfaces.

[0135] In addition, according to Figure 5 and Figure 6 The package 100 of FIG. 1 comprises a conductive structure 103 which is divided into a first conductive element 165 and a separate second conductive element 167 . The first conductive element 165 is attached to the second terminal 108 . The second conductive element 167 is attached to the fourth terminal 114 .

[0136] Encapsulation material 138 , such as a mold compound, partially encapsulates carrier 102 , completely encapsulates first chip 104 , completely encapsulates second chip 112 , and completely or partially encapsulates electrically conductive structure 103 .

[0137] The thermally conductive and electrically insulating layer 142, which may be implemented as in the first embodiment described above, may be arranged on the exposed surface portion of the carrier 102. More specifically, the insulating layer 142 may cover the exposed surface portions of the first die pad 150 and the second die pad 152. Thus, the insulating layer 142 is arranged on the exposed surface of the carrier 102.

[0138] The first chip 104 and the second chip 112 are connected in a half-bridge configuration. In the half-bridge configuration, the first chip 104 is a source-down chip and serves as a low-side chip, and the second chip 112 is a drain-down chip and serves as a high-side chip. During operation, the second terminal 108 and the fourth terminal 114 are configured as switch nodes of the package 100 and therefore have a floating potential. Figure 5 In contrast, the first terminal 106 and the fifth terminal 116 are configured to have fixed potentials DC- and DC+, respectively, see Figure 5 The insulating layer 142 is arranged on the exposed first die pad 150 and the exposed second die pad 152 having the fixed potential DC-, DC+. In view of the fixed potential DC+, DC- directly below the insulating layer 142, the insulating layer 142 can be formed to have a small vertical thickness D of less than 100 μm. As described above, a heat sink 146 can be attached on top of the insulating layer 142.

[0139] During operation of the package 100, the exposed first and second die pads 150, 152 covered by the insulating layer 142 with the heat sink 146 thereon are at a fixed potential DC-, DC+ (rather than at a floating potential like the switch node type conductive elements 165, 167 of the conductive structure 103). In view of the fixed potential DC+, DC-, the effect of the parasitic capacitance formed by the metal die pads 150, 152 and the metal heat sink 146 (where the insulating layer 142 is located between the metal die pads 150, 152 and the metal heat sink 146) is not significant. More specifically, the capacitive coupling of the fixed potential die pads 150, 152 with the metal heat sink 146 is advantageously weaker or reduced via the dielectric in the form of the insulating layer 142 compared to the case where the pads 150, 152 are at a floating potential. Due to this reduced capacitive coupling, it is advantageous to provide the insulating layer 142 with a small thickness D, for example in the range of 10 μm to 100 μm. Figure 5 and Figure 6 The embodiment of FIG. 1 provides a thin insulating layer 142 directly on the fixed potential pads 150, 152. This can reduce unintentional current induction and can achieve favorable EMI behavior.

[0140] exist Figure 5 and Figure 6In the embodiment of the present invention, the conductive structure 103 includes the conductive element 165 connected to the first chip 104 and the separate further conductive element 167 connected to the second chip 112. Each of the conductive elements 165, 167 may be implemented as a respective clip that may be connected to each other via a conductive connecting element 173.

[0141] Reference now Figure 6 The three-dimensional illustration of the package body 100 in FIG. 1 further includes a first terminal lead 153 (i.e., a lead connected to the first terminal 106), a second terminal lead 159 (i.e., a lead connected to the second terminal 108), a third terminal lead 155 (i.e., a lead connected to the third terminal 110), a fourth terminal lead 171 (i.e., a lead connected to the fourth terminal 114), a fifth terminal lead 177 (i.e., a lead connected to the fifth terminal 116), a sixth terminal lead 124 (i.e., a lead connected to the sixth terminal 118), and the connecting element 173 mentioned above.

[0142] As shown, the conductive element 165 is connected to the second terminal lead 159. In addition, another conductive element 167 is attached to the fourth terminal 114 and connected to the fourth terminal lead 171. The connecting element 173 is embedded inside the encapsulation material 138, and connects the second terminal lead 159 to the fourth terminal lead 171 via the inside of the package body 100. In addition, the second terminal lead 159 and the fourth terminal lead 171 are arranged on a first side of the package body 100, and the first terminal lead 153 and the fifth terminal lead 177 are arranged on the opposite second side of the package body 100. In addition, the direct connection structure 179 is arranged to directly electrically connect the second terminal 108 located below the conductive element 165 and the fourth terminal 114 located below the another conductive element 167 inside the encapsulation material 138.

[0143] like Figure 6 As shown, the third terminal lead 155 is electrically connected to the third terminal 110 through the third terminal connecting element 122. After being encapsulated by the molded encapsulation material 138, the third terminal lead 155 will partially extend beyond the encapsulation material 138 to achieve electrical coupling with the peripheral electronic devices of the package body 100. In the illustrated embodiment, the third terminal connecting element 122 can be a connecting wire extending between the third terminal 110 and the third terminal lead 155. Figure 6 As shown, the connecting wires may extend above the chip mounting surface of the carrier 102 or may protrude beyond the chip mounting surface of the carrier 102 .

[0144] Furthermore, the package 100 includes a sixth terminal lead 124 electrically connected to the sixth terminal 118 via a sixth terminal connecting element 126. In the illustrated embodiment, the sixth terminal connecting element 126 may be another connecting wire extending between the sixth terminal 118 and the sixth terminal lead 124.

[0145] therefore, Figure 5 and Figure 6 Embodiments provide a semiconductor package including two separate die pads 150, 152. In addition, two separate clips are provided as conductive elements 165, 167. A first chip 104 is implemented as a source-down low-side die, whose source pad is arranged on a first surface of the first die pad 150. The gate pad of the first chip 104 is arranged on the same side as the source pad, but does not contact the first die pad 150. The drain pad of the first chip 104 is arranged on the opposite side of the first chip 104 and faces away from the first die pad 150.

[0146] With respect to the second chip 112, the die is arranged in a drain-down high-side configuration. The drain pad is arranged on a first surface of the second die pad 152, and the source pad and gate pad of the second chip 112 are arranged on the opposite side of the die. The second surfaces of the first die pad 150 and the second die pad 152 are exposed from the package 100. A thin insulating layer 142 (which may include two separate sections for separate die pads 150, 152) may be arranged on top of the exposed second surface of the carrier 102.

[0147] The conductive element 165 implemented as a first clip is arranged to connect the drain pad of the first chip 104 to the drain lead (D1 of the package 100). Another conductive element 167 implemented as a second clip is arranged to connect the source pad of the second chip 112 to the second source lead (S2 of the package 100), wherein the drain lead D1 and the source lead S2 are connected via a connecting element 173 embedded inside the package 100.

[0148] Regarding the thin insulating layer 142 , the first and second sections thereof may be separated from each other, or the first insulating layer 142 may be implemented as an integral component.

[0149] according to Figure 5 and Figure 6The package 100 includes a plurality of first source leads (S1) and a plurality of second drain leads (D2), and when the package 100 is configured with a half-bridge circuit and operates accordingly, the plurality of first source leads and the plurality of second drain leads respectively have different fixed potentials. The package 100 has a plurality of first drain leads and a plurality of second source leads, and the plurality of first drain leads and the plurality of second source leads are arranged at one side of the package 100 and can be interconnected via an internal conductive element (e.g., a portion of a lead frame or a metal strip). Since the first clip and the second clip are directly connected by the internal connecting element 173 (see the reference numerals 165, 167), the terminal D1 of the first chip 104 and the terminal S2 of the second chip 112 can have the same potential. An additional conductive element (represented as a direct connection structure 179, for example, in Figure 6 The wire or clip shown in the middle of the two clips in FIG. 1 directly connects the top surfaces of the first clip and the second clip, or the drain pad of the first chip 104 and the source pad of the second chip 112. The top surfaces of the first clip and the second clip may be embedded in the molding compound, or may be partially exposed from the bottom surface of the package body 100. Figure 5 and Figure 6 The package 100 may be implemented as a SMD package.

[0150] Reference again Figure 6 , Figure 6 The bottom side in may be the top side of the package 100 to which the external heat sink 146 may be attached.

[0151] Figure 6 The semiconductor package 100 includes a first die pad 150 and a second die pad 152 of a common lead frame structure. The first die pad 150 and the second die pad 152 may be made of a conductive metal. The fifth terminal 116 of the second chip 112 is attached to a first surface of the second die pad 152. The first die pad 150 and the second die pad 152 are exposed from the top surface of the package 100. The first insulating layer section is arranged on top of the exposed surface of the first die pad 150, and the second insulating layer section is arranged on top of the exposed surface of the second die pad 152. The first die pad 150 and the second die pad 152 are separated from each other, so that the first insulating layer section and the second insulating layer section can be separated from each other, or an integral insulating layer can be formed.

[0152] The first conductive element 165 may be attached to the second terminal of the first chip 104 and may be configured to be connected to the first drain lead of the package 100. The second conductive element 167 may be attached to the source terminal of the second chip 112 and may be connected to the second source lead of the package 100. The connecting element 173 may be embedded inside the encapsulation material 138 and may connect the first drain lead of the package 100 to the second source lead of the package 100 via the inside of the package 100.

[0153] Direct connection element 179 may be arranged to directly connect a drain terminal of first chip 104 and a source terminal of second chip 112 inside encapsulation material 138 .

[0154] The first gate element may connect the gate terminal of the first chip 104 to the first gate lead of the package 100. Correspondingly, the second gate element may connect the gate terminal of the second chip 112 to the second gate lead of the package 100.

[0155] according to Figure 5 and Figure 6 The first die pad 150 may protrude out of the encapsulation material 138 and may be formed as a first source lead of the package 100 . Accordingly, the second die pad 152 may protrude out of the encapsulation material 138 and may be formed as a second drain lead of the package 100 .

[0156] Figure 7 A schematic circuit diagram of a package 100 having an interconnect structure according to yet another exemplary embodiment is shown. Figure 8 Shown according to Figure 7 3D perspective view of the package body 100. Fig. 9 Shown according to Figure 7 Another three-dimensional perspective view of the package 100 is shown.

[0157] according to Figures 7 to 9 Embodiments and basis Figure 5 and Figure 6 The embodiments of Figures 7 to 9 , the conductive structure 103 includes a single integrated clip that contacts the second terminal 108 and the fourth terminal 114. Figures 7 to 9 There is no need to provide connecting elements 173, 179.

[0158] according to Figures 7 to 9, the conductive structure 103 is a common clip and is connected to both the first chip 104 and the second chip 112. More specifically, the second terminal 108 (which is a drain terminal) is directly connected to the common clip type single integrated conductive structure 103. In addition, the fourth terminal 114 (which is a source terminal) of the second chip 112 is directly connected to the same main surface of the common clip type single integrated conductive structure 103 as the second terminal 108 of the first chip 104.

[0159] In addition to the common clip-type single integrated conductive structure 103, Figures 7 to 9 The embodiment also includes a lead frame type chip carrier 102 on which the other main surfaces of the first chip 104 and the second chip 112 are mounted. More specifically, the chip carrier 102 includes a first die pad 150 on which the first chip 104 is mounted, and includes a second die pad 152 on which the second chip 112 is mounted.

[0160] An encapsulation material 138, such as a molding compound, may encapsulate the common clip-type conductive structure 103, the first chip 104, and the second chip 112. In addition, the encapsulation material 138 may only partially encapsulate the chip carrier 102 in a manner such that one major surface of the first die pad 150 and one major surface of the second die pad 152 are exposed outside the encapsulation material 138. The exposed major surfaces of the first die pad 150 and the second die pad 152 may be opposite to the other major surfaces of the first die pad 150 and the second die pad 152 connected to the chips 104, 112, respectively. Optionally, a surface portion of the conductive structure 103 may also be exposed outside the encapsulation material 138. The exposed major surfaces may help remove heat generated by the chips 104, 112 during operation of the package 100.

[0161] In order to efficiently remove heat and simultaneously ensure electrical isolation (and therefore electrical reliability) of the package 100, an insulating layer 142 may be disposed on the exposed major surfaces of the first die pad 150 and the second die pad 152. A heat sink 146 may be disposed on the insulating layer 142 to enhance the heat dissipation capability of the package 100. As shown, the single integral conductive structure 103 faces away from the insulating layer 142.

[0162] During operation of the package 100, the exposed first die pad 150 and the second die pad 152 covered by the insulating layer 142 with the heat sink 146 thereon are at a fixed potential DC-, DC+ (rather than at a floating potential as in the switch node type conductive structure 103 implemented as a single integrated clip). In view of the fixed potential DC+, DC-, the influence of the parasitic capacitance formed by the metal die pads 150, 152 and the metal heat sink 146 (where the insulating layer 142 is located between the metal die pads 150, 152 and the metal heat sink 146) is not very significant. More precisely, the capacitive coupling of the fixed potential die pads 150, 152 with the metal heat sink 146 via the dielectric in the form of the insulating layer 142 is advantageously weaker or reduced compared to the case where the pads 150, 152 are at a floating potential. Due to this reduced capacitive coupling, the insulating layer 142 can advantageously be provided with a small thickness D, for example in the range of 10 μm to 100 μm. in short, Figures 7 to 9 The embodiment of FIG. 1 provides a thin insulating layer 142 directly on the fixed potential pads 150 , 152 .

[0163] As in Fig. 9 As best shown in FIG. 1 , the die pad 152 physically connects the D2 pad with the D2 lead (see reference numeral 177 ) as a single, unitary metal structure.

[0164] exist Figures 7 to 9 In the embodiment, the clip-type conductive structure 103 may be attached to the lead according to reference numeral 159 / 171 , for example by welding, gluing or the like, so that two different metal pieces may be present.

[0165] Figures 7 to 9 The embodiment of the present invention provides improved loop inductance for the integrated half-bridge package 100 shown. In terms of loop inductance, compared with conventional methods, the loop inductance of the integrated half-bridge package 100 is improved by the following method: Figures 7 to 9 The DC loop may be significantly reduced. In particular, it may be beneficial to obtain a spatial clamp extension along the DC path to suppress magnetic fields that are detrimental to performance (thereby obtaining advantageous characteristics in terms of eddy currents).

[0166] according to Figures 7 to 9 , a common single clip is arranged as a single common conductive structure 103. This allows collection of the full switch node potential from the high-side second chip 112 and the low-side first chip 104. Advantageously, only DC potentials DC-, DC+ are present on the exposed die pads 150, 152. Furthermore, the shown clip design ensures a high current carrying capacity. Furthermore, the clip extensions can suppress magnetic fields that could be detrimental in terms of performance. Advantageously, the clip extensions do not contribute to the effective current path, but rather act as magnetic field suppression elements by allowing induced eddy currents to extend in. Apart from this, the shown design allows small commutation loops to be realized, such as Figure 8As shown in the figure mark 181.

[0167] Therefore, an integrated half-bridge package 100 with improved electrical performance may be obtained. Therefore, ease of package handling on the user side may be achieved.

[0168] Especially for silicon carbide technology, the improvement in electrical properties is significant. Figures 7 to 9 The package design may allow high current density to be paired with low package inductance. Advantageously, package 100 may allow electrical quality factors such as loop inductance to be reduced or even minimized.

[0169] in short, Figures 7 to 9 The embodiment of the present invention provides an integrated semiconductor package 100 with a half-bridge configuration with one power chip assembled face-up and one power chip assembled face-down. Advantageously, the switch node potentials of the two power chips 104, 112 (at Figures 7 to 9 , shown as D1 / S2 or AC (for alternating current)) directly interconnected to a clip-type single integral conductive structure 103. Advantageously, Figures 7 to 9 Embodiments of the invention rely on a power interconnect technology that may be a single clip architecture.

[0170] Advantageously, Figures 7 to 9 The clip structure forming the conductive structure 103 extends beyond the die size in the direction in which it is not electrically connected to form a vortex plate.

[0171] In accordance with Figures 7 to 9 In the embodiment of FIG. 1 , the integrated clip is arranged on the drain pad of the first chip 104 and the source pad of the second chip 112 . Figure 8 The bottom side in the embodiment may refer to the top side of the package 100, wherein the external heat sink 146 ( Figure 8 142 is attached to the thin insulating layer 142. Fig. 9 The top side in may be the top side of the package 100 where the external heat sink 146 is attached to the thin insulating layer 142 .

[0172] from Figure 8 and Fig. 9 As can be seen in FIG. 1 , the package 100 has a plurality of second terminal leads 159 and a plurality of fourth terminal leads 171, which are arranged at one side of the package 100 and connected to each other via an integrated clip. Due to the integrated clip, the terminal D1 of the first chip 104 and the terminal S2 of the second chip 112 have the same potential.

[0173] The integrated clip may be embedded in the molding compound or may be partially exposed from the bottom surface of the package body 100 .

[0174] The clip may also protrude from the package body 100, and may form a plurality of fourth terminal leads 171 (corresponding to the terminal S2) and a plurality of second terminal leads 159 (related to the terminal D1), wherein the terminals S2 and D1 may be connected via the clip inside the package body 100. Alternatively, the integral conductive body 103 may be arranged on the plurality of fourth terminal leads 171 (corresponding to the terminal S2) and the plurality of second terminal leads 159 (related to the terminal D1). Therefore, the clip may also be a component separate from the lead frame.

[0175] When the package 100 is configured as a half-bridge circuit, the plurality of fifth terminal leads 177 (related to the terminal D2 ) and the plurality of first terminal leads 153 (corresponding to the terminal S1 ) respectively have different fixed potentials (DC+ or DC−).

[0176] The clip may be embedded in the molding compound. Alternatively, the clip may be exposed from a surface of the package 100 opposite to another surface of the package 100 that exposes the carrier 102. Alternatively, an additional insulating layer (see Fig.14 The second heat sink 142 may be arranged on top of the conductive structure 103, but its thickness may be thicker than the thickness of the insulating layer 142 on top of the fixed potential terminals D2, S1. Furthermore, a second heat sink may be arranged on top of the further insulating layer 143. The integrated clip-type conductive structure 103 may be arranged to contact the second terminal 108 of the first chip 104 and the fourth terminal 114 of the second chip 112 simultaneously.

[0177] When operating in the illustrated half-bridge configuration, the second terminal lead 159 and the fourth terminal lead 171 of the package 100 are configured as switch nodes of the package 100 and thus have a floating potential. In contrast, the first terminal lead 153 and the fifth terminal lead 177 are configured to have a fixed potential compared to the floating potential of the second terminal lead 159 and the fourth terminal lead 171. Therefore, the insulating layer 142 (or a separate insulating layer section) is arranged on the exposed first die pad 150 and the exposed second die pad 152 having a fixed potential.

[0178] Fig.10 A schematic circuit diagram of a package 100 having an interconnect structure according to yet another exemplary embodiment is shown. Fig.11 Shown according to Fig.10 A three-dimensional opaque view of the package 100. Fig.12 Shown according to Fig.10 3D perspective view of the package body 100.

[0179] according to Figures 10 to 12 The carrier 102 includes an integrated die pad of a lead frame. The first chip 104 and the second chip 112 are constructed in Fig.12131. Corresponding to the semiconductor body 154 of the first chip 104, the second chip 112 is also provided with a corresponding semiconductor body 156, in which a field effect transistor can be monolithically integrated.

[0180] The first terminal 106 and the fifth terminal 116 are attached to the integrated die pad type carrier 102 and have a floating potential during the operation of the package 100. The second terminal 108 is attached to the conductive element 165 of the conductive structure 103 and has a fixed potential DC+ during the operation of the package 100. The fourth terminal 114 is attached to another conductive element 167 of the conductive structure 103 and has a fixed potential DC- during the operation of the package 100. In the half-bridge configuration shown, the first chip 104 with the source electrode downward is operated as a high-side chip, and the second chip 112 with the drain electrode downward is operated as a low-side chip. Therefore, when the package 100 is operated with the half-bridge configuration of the first chip 104 and the second chip 112, the first terminal lead 153 and the fifth terminal lead 177 are configured as switch nodes and have a floating potential. The second terminal lead 159 connected to the conductive element 165 and the fourth terminal lead 171 connected to another conductive element 167 have fixed potentials DC+, DC- respectively.

[0181] like Fig.12 As shown, the integrated die pad type carrier 102 protrudes from the encapsulation material 138 , thereby forming exposed first terminal leads 153 and fifth terminal leads 177 of the package 100 .

[0182] Surface portions of the conductive element 165 and the other conductive element 167 are exposed relative to the encapsulation material 138. An insulating layer 142 may be formed to cover the exposed surfaces of the conductive element 165 and the other conductive element 167, and a heat sink 146 (not shown) may be attached to the insulating layer 142. The insulating layer 142 may be a single layer covering the two conductive elements 165, 167, or may include two separate sections, each section being assigned to a corresponding one of the conductive elements 165, 167.

[0183] Although not shown, the package 100 may include a further insulating layer 143 (see FIG. 1 ) which may be arranged on the exposed surface of the carrier 102. Fig.15 ). The thickness H of the further insulating layer 143 on the floating potential carrier 102 may be greater than the thickness D of the insulating layer 142 on the fixed potential conductive structure 103 .

[0184] Thus, the package 100 according to an exemplary embodiment may include an integral conductive body, namely a common die pad type carrier 102 in the presently described embodiment, Figures 7 to 9 In the embodiment of FIG. 1 , a common clip-type conductive structure 103 is provided.

[0185] Reference again Figures 10 to 12 , a conductive element 165 implemented as a first clip is arranged on top of the drain pad of the first chip 104 and is connected to a plurality of second terminal leads 159. Another conductive element 167 implemented as a second clip is arranged on top of the source pad of the second chip 112 and is connected to a plurality of fourth terminal leads 171. Both clips may be exposed at one surface of the package body 100. A (separate or integrated) thin insulating layer 142 may be arranged on the exposed portion of the clip.

[0186] Fig.12 The top side in FIG. 1 may be the top side of the package 100 (with two clips exposed at the top), where an external heat sink 146 may be attached to the thin insulating layer 142 (neither shown). Fig.11 The bottom side in may be the top side of the package body 100 .

[0187] refer to Fig.12 The integrated carrier 102 protrudes from the encapsulation material 138 and forms a plurality of first terminal leads 153 (corresponding to the terminal S1 ) and a plurality of fifth terminal leads 177 (related to the terminal D2 ), wherein the terminals D1 and S2 are connected to the conductive elements 165 , 167 via their inner portions.

[0188] When the package 100 is configured as a half-bridge circuit, the plurality of second terminal leads 159 (corresponding to the terminal D1 ) and the plurality of fourth terminal leads 171 (related to the terminal S2 ) respectively have different fixed potentials.

[0189] In one embodiment, the carrier 102 may be embedded in a molding compound.Alternatively, the carrier 102 may be exposed from a surface of the package 100 opposite to another surface of the package 100 where the conductive elements 165, 167 may be exposed.

[0190] Another advantageous feature of package 100 is the external creepage increasing groove 140, which Fig.12 This can be best seen in (see also Figure 6 , Figure 8 and Fig. 9). The creepage distance increasing groove 140 may be formed as an external recess in the encapsulation material 138 extending along the entire distance between the opposite edges of the encapsulation material 138. Advantageously, the creepage distance increasing groove 140 may be arranged to increase the creepage distance between the exposed cooling surface of the carrier 102 on the one hand and the lead structures 159, 171 on the other hand. The lead structures 159, 171 are spaced apart relative to the carrier 102 by the material of the encapsulation material 138, and the creepage distance increasing groove 140 is formed in the spaced apart area. For example, due to humidity in the environment, a parasitic conductive path may be unintentionally generated between the exposed surface of the carrier 102 and the lead structures 159, 171. By forming the creepage distance increasing groove 140 between the exposed surface of the carrier 102 and the lead structures 159, 171, the length of the parasitic creepage path may be extended, and the complexity of the parasitic creepage path may be enhanced. Therefore, the creepage distance increasing groove 140 may improve the electrical reliability of the package 100. Therefore, the creepage increasing groove 140 may improve electrical isolation and may make the package 100 suitable for high voltage applications.

[0191] During operation of the package 100, the exposed conductive elements 165, 167 of the conductive structure 103 covered by the insulating layer 142 with the heat sink 146 thereon are at a fixed potential DC+, DC- (rather than at a floating potential as in the case of the switch node type carrier 102). In view of the fixed potential DC+, DC-, the influence of the parasitic capacitance formed by the metal conductive elements 165, 167 and the metal heat sink 146 (wherein the insulating layer 142 is located between the metal conductive elements 165, 167 and the metal heat sink 146) is not significant. More precisely, the capacitive coupling of the fixed potential conductive elements 165, 167 to the metal heat sink 146 via the dielectric in the form of the insulating layer 142 is advantageously weaker or reduced compared to the case where the conductive elements 165, 167 are at a floating potential. Due to this reduced capacitive coupling, it is advantageously possible to provide the insulating layer 142 with a small thickness D, for example in the range of 10μm to 100μm. In short, Figures 10 to 12 The embodiment of FIG. 1 provides a thin insulating layer 142 directly on the fixed potential conductive elements 165 , 167 .

[0192] It will be described below Figures 13 to 15 The present invention relates to an embodiment for realizing double-sided cooling. Figures 13 to 15 The package body 100 may have excellent thermal performance. Figures 13 to 15 Only a portion of the package 100 that is relevant to the aforementioned embodiment in a corresponding double-sided cooling architecture is shown.

[0193] Fig.13 Shown as Figure 5 and Figure 6A cross-sectional view of a package 100 according to a variant of an embodiment of the present invention. Fig.13 , the first main surface of the encapsulation material 138 exposes the first die pad 150 and the second die pad 152 of the carrier 102. Correspondingly, the second main surface of the encapsulation material 138 exposes the conductive element 165 and the further conductive element 167 of the conductive structure 103. In the illustrated embodiment, the insulating layer 142 comprises a first insulating layer section 161 located on the first die pad 150, and comprises a separate second insulating layer section 163 located on the second die pad 152. Furthermore, a further insulating layer 143 is provided, which comprises a first further insulating layer section 183 located on the conductive element 165 and a second further insulating layer section 185 located on the further conductive element 167. Since the die pads 150, 152 are at fixed potentials DC-, DC+ (compare Figure 5 ), so the dielectric layer 142 on the die pads 150, 152 can be formed to have a small thickness D, for example, less than 100 μm, without significantly reducing the electrical reliability. In contrast, the thickness H of the further insulating layer 143 should be greater than the thickness D, because the conductive elements 165, 167 are at a floating potential during operation of the package 100 (again, compare Figure 5 ).

[0194] Fig.13 Embodiments may ensure double-sided cooling while providing high electrical reliability.

[0195] Fig.14 Shown as Figures 7 to 9 A cross-sectional view of a package 100 which is a variation of an embodiment of the present invention and also enables double-sided cooling.

[0196] according to Fig.14 Embodiments and basis Fig.13 The embodiments of Fig.14 The insulating layer 142 is a single integral layer extending over the first die pad 150 and over the second die pad 152 , and the insulating layer 143 is a single integral layer extending over the conductive element 165 and over the further conductive element 167 .

[0197] Fig.15 Shown as Figures 10 to 12 1 is a cross-sectional view of a package 100 according to a variation of an embodiment.

[0198] according to Fig.15, the first main surface of the encapsulation material 138 exposes the single die carrier 102. Correspondingly, the second main surface of the encapsulation material 138 exposes the conductive element 165 and the further conductive element 167 of the conductive structure 103. In the illustrated embodiment, the insulating layer 142 comprises a first insulating layer section 161 located on the conductive element 165, and comprises a separate second insulating layer section 163 located on the further conductive element 167. In addition, an integral and continuous further insulating layer 143 is provided, which covers the entire exposed surface of the carrier 102. Since the conductive elements 165, 167 are at a fixed potential (compare Fig.10 ), so the dielectric layer 142 on the conductive elements 165, 167 can be provided with a small thickness D, for example below 100 μm, without significantly reducing the electrical reliability. In contrast, the thickness H of the dielectric layer 143 on the carrier 102 should be greater than the thickness D, because the carrier 102 is at a floating potential during operation of the package 100 (again compare Fig.10 ).

[0199] Fig.15 Embodiments may ensure double-sided cooling while providing high electrical reliability.

[0200] It should be noted that the term "comprising" does not exclude other elements or features, and "one" or "an" does not exclude a plurality. Elements described in association with different embodiments may also be combined. It should also be noted that the reference numerals should not be interpreted as limiting the scope of the claims. In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods and steps described in the specification. Therefore, the appended claims are intended to include these processes, machines, manufactures, compositions of matter, means, methods or steps within their scope.

Claims

1. A package (100), comprising: A carrier (102); a first chip (104) having an integrated transistor and comprising a second terminal (108), a third terminal (110) and a first terminal (106) attached to the carrier (102), the first terminal (106) and the third terminal (110) being formed on one main surface of the first chip (104), the second terminal (108) being formed on another opposite main surface of the first chip (104), the first terminal (106) being a source or emitter terminal, the second terminal (108) being a drain or collector terminal, and the third terminal (110) being a gate or base terminal; a conductive structure (103) which is at least partially conductive and is attached to the second terminal (108); an encapsulation material (138) at least partially encapsulating the carrier (102), the first chip (104) and the conductive structure (103); and an insulating layer (142) arranged on a surface portion of the conductive structure (103) or of the carrier (102), the surface portion being exposed outside the encapsulation material (138), the insulating layer (142) being thermally conductive and electrically insulating; a second chip (112) having an integrated transistor and comprising a fourth terminal (114), a sixth terminal (118) and a fifth terminal (116) attached to the carrier (102), the fourth terminal (114) and the sixth terminal (118) being formed on one main surface of the second chip (112), the fifth terminal (116) being formed on the other opposite main surface of the second chip (112), the fourth terminal (114) being a source or emitter terminal, the fifth terminal (116) being a drain or collector terminal, and the sixth terminal (118) being a gate or base terminal; wherein the conductive structure (103) is attached to the fourth terminal (114); The encapsulation material (138) encapsulates at least a portion of the second chip (112); At least a portion of the conductive structure (103) is exposed from the encapsulation material (138); One of the conductive structure (103) or the carrier (102) on which the insulating layer (142) is arranged is at at least one fixed potential (DC+, DC-) during operation of the package (100), and in particular, the other of the conductive structure (103) or the carrier (102) on which the insulating layer (142) is not arranged is at at least one floating potential during operation of the package (100).

2. The package (100) according to claim 1, wherein: The carrier (102) comprises a lead frame structure or a laminate, such as a printed circuit board.

3. The package (100) according to claim 1 or 2, wherein: The carrier (102) has an electrical wiring structure (151) extending between two opposite main surfaces of the carrier (102) and connecting the first terminal (106) to a first terminal lead (153) and connecting the third terminal (110) to a third terminal lead (155).

4. The package (100) according to claim 3, wherein: At least a portion of the first terminal lead (153) and the third terminal lead (155) are exposed relative to the encapsulation material (138) for attachment to a mounting base (191), such as a printed circuit board.

5. The package (100) according to any one of claims 1 to 4, wherein: The carrier (102) comprises at least one thermal channel (157) for dissipating heat from the first chip (104) to a side of the carrier (102) facing away from the electrically conductive structure (103).

6. The package (100) according to any one of claims 1 to 5, wherein: The conductive structure (103) comprises a lead frame structure or a clip.

7. The package (100) according to any one of claims 1 to 6, wherein: The conductive structure (103) protrudes from the encapsulation material (138) and serves as a second terminal lead (159).

8. The package (100) according to any one of claims 1 to 7, wherein: The package (100) includes a heat sink (146) attached to the insulating layer (142).

9. The package (100) according to any one of claims 1 to 8, wherein: The carrier (102) includes a first die pad (150) on which the first chip (104) is mounted, and includes a separate second die pad (152) on which the second chip (112) is mounted, the first die pad (150) and the second die pad (152) comprising conductive material.

10. The package (100) according to claim 9, wherein: The first die pad (150) and the second die pad (152) form part of a lead frame structure.

11. The package (100) according to any one of claims 1 to 10, wherein: The package (100) comprises one of the following features: The insulating layer (142) includes a first insulating layer section (161) located on the first die pad (150), and includes a separate second insulating layer section (163) located on the second die pad (152); The insulating layer (142) is a single unitary layer extending over the first die pad (150) and over the second die pad (152).

12. The package (100) according to any one of claims 1 to 11, in, The conductive structure (103) comprises a conductive element (165) connected to the first chip (104) and another conductive element (167) connected to the second chip (112); The package body (100) further comprises a second terminal lead (159), a fourth terminal lead (171) and a connecting element (173); The conductive element (165) is connected to the second terminal lead (159); The further conductive element (167) is attached to the fourth terminal (114) and connected to the fourth terminal lead (171); and The connecting element (173) is embedded in the encapsulation material (138) and connects the second terminal lead (159) to the fourth terminal lead (171) via the interior of the package body (100).

13. The package (100) according to claim 12, wherein: The second terminal lead (159) and the fourth terminal lead (171) are arranged on a first side of the package body (100), and the first terminal lead (153) and the fifth terminal lead (177) are arranged on an opposite second side of the package body (100).

14. The package (100) according to claim 12 or 13, wherein: At least one of the conductive element (165) and the further conductive element (167) comprises a clip.

15. The package (100) according to any one of claims 1 to 14, wherein: The package (100) includes a direct connection structure (179) arranged to directly electrically connect the second terminal (108) and the fourth terminal (114) inside the encapsulation material (138).

16. The package (100) according to any one of claims 1 to 15, wherein: The conductive structure (103) includes an integrated clip contacting the second terminal (108) and the fourth terminal (114).

17. The package (100) according to any one of claims 1 to 16, in, The carrier (102) includes an integrated die pad of a lead frame; The first terminal (106) and the fifth terminal (116) are attached to the integrated die pad; The integrated die pad protrudes out of the encapsulation material (138) and forms a first terminal lead (153) and a fifth terminal lead (177) of the package (100); The conductive element (165) of the conductive structure (103) is attached to the second terminal (108) and connected to a second terminal lead (159); Another conductive element (167) of the conductive structure (103) is attached to the fourth terminal (114) and connected to a fourth terminal lead (171).

18. The package (100) according to claim 17, in, At least a portion of the conductive element (165) and the further conductive element (167) are exposed relative to the encapsulation material (138); The insulating layer (142) covers the exposed surfaces of the conductive element (165) and the further conductive element (167).

19. The package (100) according to claim 18, wherein: The package (100) comprises one of the following features: The insulating layer (142) comprises a first insulating layer section (161) located on the conductive element (165), and comprises a separate second insulating layer section (163) located on the further conductive element (167); The insulating layer (142) is a single integral layer extending over the conductive element (165) and over the further conductive element (167).

20. The package (100) according to any one of claims 17 to 19, in, When the package (100) is operated in a half-bridge configuration of the first chip (104) and the second chip (112), the first terminal lead (153) and the fifth terminal lead (177) are configured as switch nodes and have a floating potential; and The package body (100) includes a second terminal lead (159) connected to the conductive element (165) and includes a fourth terminal lead (171) connected to the other conductive element (167), the second terminal lead (159) and the fourth terminal lead (171) having a fixed potential.

21. The package (100) according to any one of claims 17 to 20, wherein: The first chip (104) is a source-down chip and serves as a high-side chip, and the second chip (112) is a drain-down chip and serves as a low-side chip.

22. The package (100) according to any one of claims 1 to 21, wherein: The package (100) includes a heat sink (146) disposed on the insulating layer (142).

23. The package (100) according to any one of claims 1 to 22, wherein: The insulating layer (142) has a thickness (D) in the range of 10 μm to 100 μm and comprises one of the following: Ceramic materials such as aluminum oxide, aluminum nitride, boron nitride and / or aluminum oxynitride; Organic materials such as prepregs.

24. The package (100) according to any one of claims 1 to 22, wherein: The insulating layer (142) has a thickness (D) in the range of 1 μm to 500 μm, for example in the range of 15 μm to 70 μm or in the range of 20 μm to 50 μm.

25. The package (100) according to any one of claims 1 to 24, wherein: The first chip (104) and the second chip (112) are connected to form a half bridge.

26. The package (100) according to claim 25, wherein: The first chip (104) is a source-down chip and serves as a low-side chip, and the second chip (112) is a drain-down chip and serves as a high-side chip.

27. The package (100) according to any one of claims 1 to 26, in, At least a portion of the conductive structure (103) is exposed from the encapsulation material (138) at a surface opposite to another surface where at least a portion of the carrier (102) is exposed from the encapsulation material (138); The insulating layer (142) is arranged on at least a portion of the exposed surface of the carrier (102); The package (100) comprises a further insulating layer (143) arranged on an exposed surface of the conductive structure (103); and The thickness (H) of the additional insulating layer (143) is greater than the thickness (D) of the insulating layer (142).

28. The package (100) according to any one of claims 1 to 27, in, At least a portion of the conductive structure (103) is exposed from the encapsulation material (138) at a surface opposite to another surface where at least a portion of the carrier (102) is exposed from the encapsulation material (138); The insulating layer (142) is arranged on an exposed surface of at least a portion of the conductive structure (103); The package (100) comprises a further insulating layer (143) arranged on an exposed surface of the carrier (102); and The thickness (H) of the additional insulating layer (143) is greater than the thickness (D) of the insulating layer (142).

29. The package (100) according to any one of claims 1 to 28, wherein: The package (100) comprises one of the following features: At least one of the first chip (104) and the second chip (112) is a power semiconductor chip; At least one of the first chip (104) and the second chip (112) is configured to operate with vertical current flow; At least one of the first chip (104) and the second chip (112) is a field effect transistor chip or a bipolar transistor chip; The package (100) has a voltage rating in the range of 650V to 2000V; The carrier (102) comprises a lead frame structure or a printed circuit board; The conductive structure (103) includes at least one clip; The insulating layer (142) has a thermal conductivity of at least 1 W / mK, for example at least 50 W / mK, preferably at least 100 W / mK.

30. The package (100) according to any one of claims 1 to 29, wherein: The other of the conductive structure (103) or the carrier (102) on which the insulating layer (142) is not disposed is at least one floating potential during operation of the package (100).

31. The package (100) according to any one of claims 1 to 30, wherein: The package (100) is configured to apply the at least one fixed potential (DC+, DC-) to one of the conductive structure (103) or the carrier (102) on which the insulating layer (142) is arranged, for suppressing capacitive coupling.

32. A method for manufacturing a package (100), the method comprising: Attaching a first terminal (106) of a first chip (104) having an integrated transistor to the carrier (102); providing the first chip (104) with a second terminal (108) and a third terminal (110), The first terminal (106) and the third terminal (110) are formed on one main surface of the first chip (104), the second terminal (108) is formed on another opposite main surface of the first chip (104), the first terminal (106) is a source or emitter terminal, the second terminal (108) is a drain or collector terminal, and the third terminal (110) is a gate or base terminal; Attaching an at least partially electrically conductive conductive structure (103) to the second terminal (108); at least partially encapsulating the carrier (102), the first chip (104) and the conductive structure (103) by an encapsulation material (138); and Arranging an insulating layer (142) on a surface portion of the conductive structure (103) or the carrier (102), the surface portion being exposed outside the encapsulation material (138), the insulating layer (142) being thermally conductive and electrically insulating; wherein the package (100) further comprises a second chip (112) having an integrated transistor and comprising a fourth terminal (114), a sixth terminal (118) and a fifth terminal (116) attached to the carrier (102), the fourth terminal (114) and the sixth terminal (118) being formed on one main surface of the second chip (112), the fifth terminal (116) being formed on another opposite main surface of the second chip (112), the fourth terminal (114) being a source or emitter terminal, the fifth terminal (116) being a drain or collector terminal, and the sixth terminal (118) being a gate or base terminal; The conductive structure (103) is attached to the fourth terminal (114); The encapsulation material (138) encapsulates at least a portion of the second chip (112); At least a portion of the conductive structure (103) is exposed from the encapsulation material (138); The conductive structure (103) on which the insulating layer (142) is arranged is at at least one fixed potential (DC+, DC-) during operation of the package (100).

Images