Photon integrated circuit chip and silicon optical integration platform

Abstract

The invention discloses a photonic integrated circuit chip and a silicon optical integration platform, and aims to provide a specific waveguide structure on the photonic integrated circuit chip to realize efficient coupling with a common single-mode fiber, and meanwhile, a suspended structure is not introduced, so that the overall structure has relatively high mechanical stability. The method can pass high-temperature and high-humidity reliability test conditions of the photon integrated circuit chip, and is compatible with reflow soldering, silicon through hole and other processes.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technology, and in particular to a photonic integrated circuit chip and a silicon photonic integrated platform. Background Art

[0002] In recent years, photonic integrated circuit chips can effectively reduce the cost and power consumption of modules in optical communications, and are a key technology for achieving optical interconnection. The mode field of a typical single-mode silicon optical waveguide is in the order of hundreds of nanometers, while the mode field diameter (MFD) of an ordinary single-mode optical fiber that needs to be coupled and aligned with a photonic integrated circuit chip (such as a silicon optical chip) is 9-10μm. There is a large mode field mismatch between the two, and the direct coupling alignment tolerance is small, and there is a large optical coupling loss. Summary of the invention

[0003] The object of the present invention is to provide a photonic integrated circuit chip and a silicon photonic integrated platform, so as to improve the optical coupling efficiency between the photonic integrated circuit chip and an external optical fiber.

[0004] The purpose of the present invention is achieved by the following technical solutions:

[0005] According to one aspect of the present invention, there is provided a photonic integrated circuit chip, comprising: a supporting silicon, a first silicon oxide layer and a second silicon oxide layer which are stacked;

[0006] The photonic integrated circuit chip comprises an optical device arranged in the first silicon oxide layer and a device waveguide optically connected to the optical device, and the side of the photonic integrated circuit chip has an external end face coupled to the outside world;

[0007] At least one first metal layer is also provided in the first silicon oxide layer, and in the thickness direction of the supporting silicon, the at least one first metal layer is located between the optical device and the supporting silicon;

[0008] The photonic integrated circuit chip also includes a first waveguide, which is arranged in the first silicon oxide layer or the second silicon oxide layer. The first waveguide is optically coupled to the device waveguide. In a thickness direction perpendicular to the supporting silicon, the first waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface. The first waveguide is configured to have a first mode size on a side away from the outer end surface and a second mode size on a side close to the outer end surface, wherein the first mode size is larger than the second mode size.

[0009] Further, in the thickness direction of the supporting silicon, the spacing between the first waveguide and the supporting silicon is greater than half of the mode field diameter of an external optical fiber to be optically coupled with the photonic integrated circuit chip.

[0010] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

[0011] Optionally, the number of the first waveguides is 1 or more;

[0012] When there are multiple first waveguides, the multiple first waveguides are located in the same film layer and placed side by side, and at least one of the multiple first waveguides gradually becomes thinner toward the outer end surface.

[0013] Further, in the case where the first waveguide is arranged in the first silicon oxide layer, the photonic integrated circuit chip also includes a second waveguide, which is located in the second silicon oxide layer, optically coupled with the first waveguide, and spaced apart from the first waveguide in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the second waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface.

[0014] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the second waveguide is in an inverted wedge-shaped structure.

[0015] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the second waveguide is smaller than an extension length of the first waveguide, and an end of the second waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

[0016] Further, the number of the second waveguides is plural, and the number of the first waveguides is plural;

[0017] At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of first waveguides is arranged in a plurality of rows and / or a plurality of columns.

[0018] Furthermore, at a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of first waveguides are arranged in a staggered or irregular manner.

[0019] Further, at least one second waveguide among the plurality of second waveguides has a constant cross-sectional width directed from the inside of the photonic integrated circuit chip to the outer end surface.

[0020] Furthermore, the photonic integrated circuit chip also includes a third waveguide, which is located in the first silicon oxide layer, the third waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the third waveguide is spaced apart from the first waveguide and the second waveguide respectively in the thickness direction; in the thickness direction of the supporting silicon, the third waveguide is located between the first waveguide and the second waveguide; in the thickness direction perpendicular to the supporting silicon, the third waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface.

[0021] Furthermore, the third waveguide and the device waveguide are both located in the first silicon oxide layer.

[0022] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the third waveguide is greater than an extension length of the first waveguide, the third waveguide is optically connected to the device waveguide, and an end of the third waveguide close to the outer end face is flush with an end of the first waveguide close to the outer end face.

[0023] Further, in a cross-sectional direction close to the outer end surface, a plurality of first waveguides and a plurality of second waveguides surround the periphery of the third waveguide.

[0024] Furthermore, the photonic integrated circuit chip also includes a fourth waveguide, which is located in the second silicon oxide layer, the fourth waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the fourth waveguide is spaced apart from the first waveguide and the second waveguide in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the fourth waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface; in the thickness direction of the supporting silicon, the fourth waveguide is located on the side of the second waveguide away from the first waveguide.

[0025] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the fourth waveguide is in an inverted wedge-shaped structure.

[0026] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the fourth waveguide is smaller than an extension length of the first waveguide, and an end of the fourth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

[0027] Further, in the case where the first waveguide is arranged in the second silicon oxide layer, the photonic integrated circuit chip also includes a fifth waveguide, which is located in the second silicon oxide layer, optically coupled with the first waveguide, and spaced apart from the first waveguide in the thickness direction; in the thickness direction perpendicular to the supporting silicon, the fifth waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface; in the thickness direction of the supporting silicon, the fifth waveguide is located on the side of the first waveguide away from the first silicon oxide layer.

[0028] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the fifth waveguide is in an inverted wedge-shaped structure.

[0029] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the fifth waveguide is smaller than an extension length of the first waveguide, and an end of the fifth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

[0030] Further, the photonic integrated circuit chip further comprises a sixth waveguide, the sixth waveguide being located in the first silicon oxide layer, the sixth waveguide being optically coupled to the first waveguide, and being spaced apart from the first waveguide in a thickness direction;

[0031] In a direction perpendicular to the thickness of the supporting silicon, the sixth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

[0032] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface, a portion of the sixth waveguide is in an inverted wedge-shaped structure.

[0033] Further, in a direction perpendicular to the thickness of the supporting silicon, an extension length of the sixth waveguide is smaller than an extension length of the first waveguide, and an end of the sixth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

[0034] Furthermore, at least one second metal layer is provided in the second silicon oxide layer, and the at least one second metal layer is electrically connected to the at least one first metal layer through a metal through-hole.

[0035] Furthermore, the photonic integrated circuit chip further comprises a third silicon oxide layer,

[0036] Wherein, in the thickness direction of the supporting silicon, the third silicon oxide layer is arranged between the first silicon oxide layer and the supporting silicon.

[0037] Furthermore, the photonic integrated circuit chip further comprises a protective layer, wherein the protective layer covers a surface of the second silicon oxide layer on a side away from the first silicon oxide layer; wherein the material of the protective layer is silicon nitride.

[0038] Furthermore, the optical device includes one or a combination of a photodetector, a laser, a modulator and a wavelength division multiplexer.

[0039] According to another aspect of the present invention, there is also provided a silicon photonic integrated platform, comprising any of the aforementioned photonic integrated circuit chips;

[0040] An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core;

[0041] Wherein, the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

[0042] Furthermore, a groove is provided at a cross-sectional position of the supporting silicon close to the outer end surface, and the optical fiber is placed in the groove.

[0043] The present invention provides a solution for the optical interconnection between a photonic integrated circuit chip and an optical fiber, and aims to set a specific waveguide structure on the photonic integrated circuit chip to achieve efficient coupling with an ordinary single-mode optical fiber, while not introducing a suspended structure, so that the overall structure has strong mechanical stability, can pass the high temperature and high humidity reliability test conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through silicon vias.

[0044] Furthermore, the distance between the side coupler structure used for coupling during optical interconnection of photonic integrated circuits and the substrate can be optimized so that the light field does not leak into the substrate. The position and key dimensions of the single-layer waveguide and multi-layer waveguide in the side coupler structure can also be flexibly arranged as needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other implementation methods can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic structural diagram of a photonic integrated circuit chip provided in the first embodiment of the present application is shown.

[0047] Figure 2 Shows Figure 1 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1 and position 2.

[0048] Figure 3 A schematic diagram of the structure of manufacturing a photonic integrated circuit chip based on a semiconductor on an insulator according to an embodiment of the present application is shown.

[0049] Figure 4 A schematic structural diagram of a photonic integrated circuit chip provided in the second embodiment of the present application is shown.

[0050] Figure 5 Shows Figure 4 The cross-sectional schematic diagram example 1 of the side coupler structure of the photonic integrated circuit chip provided in the embodiment at position 1, position 2 and position 3.

[0051] Figure 6 Shows Figure 4 Example 2 of the cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0052] Figure 7 Shows Figure 4 Example 3 of the cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0053] Figure 8 Shows Figure 4 Example 4 of the cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0054] Fig. 9 Shows Figure 4 Example 5 of the cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1 and position 2.

[0055] Fig.10 A schematic structural diagram of a photonic integrated circuit chip provided in the third embodiment of the present application is shown.

[0056] Fig.11 Shows Fig.10 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3.

[0057] Fig.12 A schematic structural diagram of a photonic integrated circuit chip provided in the fourth embodiment of the present application is shown.

[0058] Fig.13A Shows Fig.12 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3.

[0059] Fig. 13B Shows Fig.12 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3.

[0060] Fig.14 A schematic structural diagram of a photonic integrated circuit chip provided in the fifth embodiment of the present application is shown.

[0061] Fig.15 A schematic structural diagram of a photonic integrated circuit chip provided in the sixth embodiment of the present application is shown.

[0062] Fig.16 A schematic structural diagram of a photonic integrated circuit chip provided in the seventh embodiment of the present application is shown.

[0063] Fig.17 Shows Fig.16 Another cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0064] Fig.18 A schematic structural diagram of a photonic integrated circuit chip provided in the eighth embodiment of the present application is shown.

[0065] Fig.19 Shows Fig.18 Another cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1.

[0066] Fig. 20 A structural schematic diagram of a silicon photonic integration platform provided in an embodiment of the present application is shown.

[0067] Fig.21 A cross-sectional schematic diagram of a silicon photonic integration platform provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0068] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows.

[0069] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. The meaning of chip in this article may include bare chips. When it comes to method steps, the sequence illustrated in this article represents an exemplary scheme, but does not represent a limitation on the sequence. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0070] The term "substrate" as used herein may refer to the substrate of a cut wafer, or may refer to the substrate of an uncut wafer. It should be understood that the term "film" includes layers and should not be interpreted as indicating vertical or horizontal thickness unless otherwise specified. It should be noted that the thickness of each material layer of the edge coupler structure shown in the figure is merely illustrative and does not represent the actual thickness.

[0071] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0072] In common technology, the photonic integrated circuit chip is based on the silicon waveguide made of the top silicon of the SOI (Silicon On Insulator) structure, where the thickness of the silicon oxide layer (BOX layer) between the bottom silicon and the top silicon is usually between 0.7μm-3μm, and the thickness of the silicon waveguide is usually between 150nm-340nm. To ensure effective coupling between the silicon waveguide and the SiN waveguide located on its upper side, the spacing between the silicon waveguide and the SiN waveguide is usually below 500nm. Therefore, in common technology, the vertical distance between the film layer where the SiN waveguide is located and the bottom silicon is usually less than 4μm. In order to ensure high-efficiency coupling between the photonic integrated circuit chip and ordinary single-mode optical fiber (the mode field spot is usually 9-10μm), the mode field diameter of the spot near the end face of the edge coupler also needs to be 9-10μm. Therefore, the light field will inevitably leak into the bottom silicon, introducing additional losses.

[0073] In addition, in the commonly used technology, in order to improve the coupling efficiency of the edge coupler, the underlying silicon below the corresponding area of ​​the key parts of some edge couplers is partially etched away to form a suspended structure. Although the loss of the light field leaking into the underlying silicon can be eliminated, the existence of the suspended structure will lead to low mechanical stability of the structure, which is easy to collapse in subsequent processes (for example, it is very easy to break during wafer dicing and chip packaging), making it difficult to pass the reliability test conditions required for photonic integrated circuit chips, and it is also incompatible with processes such as reflow soldering and through silicon vias of photonic integrated circuit chips, which increases the manufacturing cost.

[0074] In view of this, one aspect of the present invention provides a photonic integrated circuit chip to solve the problem of light field leakage to the underlying silicon of the photonic integrated circuit chip. The photonic integrated circuit chip comprises: a stacked supporting silicon, a first silicon oxide layer and a second silicon oxide layer; the photonic integrated circuit chip comprises an optical device arranged in the first silicon oxide layer and a device waveguide optically connected to the optical device, and the side of the photonic integrated circuit chip has an external end face coupled to the outside world; at least one first metal layer is also arranged in the first silicon oxide layer, and in the thickness direction of the supporting silicon, the at least one first metal layer is located between the optical device and the supporting silicon; the photonic integrated circuit chip also comprises a first waveguide, the first waveguide is arranged in the first silicon oxide layer or in the second silicon oxide layer, the first waveguide is optically coupled with the device waveguide, and in the thickness direction perpendicular to the supporting silicon, the first waveguide extends from the inside of the photonic integrated circuit chip to the external end face, and the first waveguide is configured to have a first mode size on the side away from the external end face and a second mode size on the side close to the external end face, wherein the first mode size is larger than the second mode size.

[0075] As can be seen from the above, the present application aims to achieve efficient coupling with ordinary single-mode optical fiber by setting a specific waveguide structure on a photonic integrated circuit chip (PIC chip), while not introducing a suspended structure, so that the overall structure has strong mechanical stability, can pass the high temperature and high humidity reliability test conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through silicon via.

[0076] Embodiment 1

[0077] Figure 1 The structure diagram of the photonic integrated circuit chip provided in the first embodiment of the present application is shown. Figure 2 Shows Figure 1 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1 and position 2.

[0078] like Figure 1 and Figure 2 As shown, the photonic integrated circuit chip 1000 provided in the first embodiment of the present application includes: a supporting silicon 100 , a first silicon oxide layer 110 and a second silicon oxide layer 120 which are stacked.

[0079] The photonic integrated circuit chip 1000 includes an optical device 210 disposed in the first silicon oxide layer 110 and a device waveguide 220 optically connected to the optical device 210. The photonic integrated circuit chip 1000 has an external end surface coupled to the outside world along a thickness direction perpendicular to the supporting silicon 100. That is, the side surface of the photonic integrated circuit chip 1000 is provided with an external end surface coupled to the outside world.

[0080] At least one first metal layer 310 is further disposed in the first silicon oxide layer 110. In the thickness direction of the supporting silicon 100, the at least one first metal layer 310 is located between the optical device 210 and the supporting silicon 100.

[0081] The photonic integrated circuit chip 1000 further includes a first waveguide 410, which is disposed in the first silicon oxide layer 110. The first waveguide 410 is optically coupled to the device waveguide 220. In a thickness direction perpendicular to the supporting silicon 100, the first waveguide 410 extends from the inside of the photonic integrated circuit chip to the outer end surface. The first waveguide 410 is configured to have a first mode size on a side away from the outer end surface and a second mode size on a side close to the outer end surface. The first mode size is larger than the second mode size.

[0082] Further, in the thickness direction of the supporting silicon 100 , the distance between the first waveguide 410 and the supporting silicon 100 is greater than half of the mode field diameter of an external optical fiber optically coupled to the photonic integrated circuit chip.

[0083] In the embodiment of the present invention, the spacing between the first waveguide 410 and the supporting silicon 100 in the photonic integrated circuit chip 1000 is designed to be greater than half of the mode field diameter of the external optical fiber optically coupled thereto, that is, through the technical solution provided by the embodiment of the present invention, the spacing between the first waveguide 410 and the supporting silicon 100 can be greater than 4.5-5 μm, thereby solving the problem of leakage of the light field on the photonic integrated circuit chip to the supporting silicon (substrate), and at the same time, no suspended structure is introduced, so that the overall structure has strong mechanical stability, which is beneficial for the photonic integrated circuit chip to pass reliability tests such as high temperature and high humidity, and is compatible with reflow soldering and through silicon via processes.

[0084] In this embodiment, the device waveguide 220, the optical device 210 and the first waveguide 410 in the photonic integrated circuit chip can be manufactured based on a semiconductor on an insulator, and the semiconductor on an insulator can be, for example, SOI (Silicon-On-Insulator). Figure 3 As shown, the semiconductor on insulator may include: an insulating layer 602, a semiconductor layer 603 formed on the insulating layer 602, and a substrate layer 601 located below the insulating layer 602. The substrate layer 601 is also called a back substrate (or back substrate layer), and the semiconductor layer 603 may be silicon, also called top silicon. The semiconductor layer 603 may be patterned, deposited, doped, and other processes to form a part of the photonic integrated circuit chip 1000. Specifically, the device waveguide 220 is formed based on etching a part of the semiconductor layer 603, and the optical device 210 may include one or a combination of a photodetector, a laser, a modulator, and a wavelength division multiplexer. For example, the photodetector includes a light absorption layer (for example, a germanium layer). In the thickness direction of the substrate layer 601, the light absorption layer is arranged on the side of the device waveguide 220 away from the substrate layer 601. The insulating layer 602 is, for example, a silicon oxide buried layer. The optical device 210 includes a part of the device waveguide 220 and a light absorption layer.

[0085] For example, in combination Figure 1-Figure 3As shown, a device waveguide 220, an optical device 210, a first silicon oxide layer 110, at least one first metal layer 310 in the first silicon oxide layer 110, and a first waveguide 410 are respectively manufactured on a substrate layer 601 (eg, bottom silicon of an SOI structure). After completion, an oxide layer 130 (for example, a SiO2 film layer) can be deposited or bonded on the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601 to flatten the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601, and then the supporting silicon 100 is bonded to the above-mentioned oxide layer on the surface of the first silicon oxide layer 110 on the side away from the substrate layer 601, and then the structure having both the substrate layer 601 and the supporting silicon 100 is turned upside down as a whole, so that the supporting silicon 100 is at the bottom and the substrate layer 601 is at the top, and then the substrate layer 601 is removed to obtain the first silicon oxide layer 110 located above the supporting silicon 100, and at least one first metal layer 310, optical device 210, device waveguide 220 and first waveguide 410 located in the first silicon oxide layer 110. At this time, the distance between the first waveguide 410 and the supporting silicon 100 is far enough. By designing the number or film thickness of at least one first metal layer 310 in the first silicon oxide layer 110, the distance between the first waveguide 410 and the supporting silicon 100 can be easily designed to be larger than half of the mode field diameter of the external optical fiber optically coupled to the photonic integrated circuit chip (the mode field diameter of an ordinary single-mode optical fiber is 9-10 μm) to prevent the optical field of the photonic integrated circuit chip from leaking into the supporting silicon 100.

[0086] For example, in this embodiment, the device waveguide 220 is a silicon waveguide, and the first waveguide 410 is a silicon nitride waveguide or a silicon oxynitride waveguide. Since silicon material generally has a higher refractive index, the actual mode size that can be achieved by the silicon waveguide is about 2-5 μm, and silicon nitride or silicon oxynitride material has a lower refractive index than silicon material, so the silicon nitride waveguide or silicon oxynitride waveguide (first waveguide) can achieve a larger mode size than the silicon waveguide (device waveguide).

[0087] In some embodiments, Figure 1 and Figure 2 As shown, from the direction pointing from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the first waveguide 410 is in an inverted wedge-shaped structure.

[0088] Optionally, the number of the first waveguides 410 is one or more; when the number of the first waveguides 410 is more than one, the multiple first waveguides 410 are located in the same film layer and are placed side by side. At this time, the edge coupler structure for mode spot conversion is composed of multiple parallel first waveguides 410, and at least one of the multiple first waveguides 410 gradually tapers toward the direction of the outer end face, so that the light field mode spot can gradually expand from the inside of the photonic integrated circuit chip 1000 to the direction of the outer end face.

[0089] In some embodiments, when the at least one first metal layer 310 includes multiple first metal layers 310, a metal through hole is further provided between two adjacent first metal layers 310 in the first silicon oxide layer 110 in the thickness direction of the supporting silicon 100, and the multiple first metal layers 310 realize electrical connection between each first metal layer 310 or other devices through the metal through hole.

[0090] Furthermore, at least one second metal layer 320 is further disposed in the second silicon oxide layer 120 , and the at least one second metal layer 320 is electrically connected to the at least one first metal layer 310 via a metal through hole.

[0091] Embodiment 2

[0092] Figure 4 A schematic structural diagram of a photonic integrated circuit chip provided in the second embodiment of the present application is shown. Figure 5 Shows Figure 4 The cross-sectional schematic diagram example 1 of the side coupler structure of the photonic integrated circuit chip provided in the embodiment at position 1, position 2 and position 3.

[0093] like Figure 4 and Figure 5 As shown, in the second embodiment of the present application, when the first waveguide 410 is arranged in the first silicon oxide layer 110, the photonic integrated circuit chip 1000 also includes a second waveguide 420, the second waveguide 420 is located in the second silicon oxide layer 120, the second waveguide 420 is optically coupled with the first waveguide 410, and is spaced apart from the first waveguide 410 in the thickness direction; in the thickness direction perpendicular to the supporting silicon 100, the second waveguide 420 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface.

[0094] In the second embodiment, compared with the first embodiment, on the basis of providing a single-layer first waveguide 410, a second waveguide 420 is additionally provided in a different layer from the first waveguide 410, and in the thickness direction of the supporting silicon 100, the distance between the second waveguide 420 and the first waveguide 410 is less than or equal to a preset distance (for example, 500 nm), so that the second waveguide 420 is optically coupled with the first waveguide 410. At this time, the photonic integrated circuit chip 1000 has a multi-layer waveguide. Since the mode field diameter of a single-layer waveguide is usually more sensitive to the morphology or size of the single-layer waveguide itself, it will cause the size of the light field mode spot at the cross-sectional position 1 actually close to the outer end face of the photonic integrated circuit chip to be too large or too small, which is not conducive to adjustment; by using a multi-layer waveguide, the multi-layer waveguides jointly participate in the mode spot conversion of the light field, which can reduce the sensitivity of the morphology or size of the single-layer waveguide itself to the mode field diameter of the single-layer waveguide on the basis of ensuring the coupling efficiency.

[0095] Specifically, the second waveguide 420 is located in the second silicon oxide layer 120, that is, the second waveguide 420 is also supported and covered by the SiO2 film layer. The light coupled from the first waveguide 410 is expanded to the silicon oxide around the second waveguide 420 after the mode spot conversion by the second waveguide 420, and the size of the light field mode spot is adjusted by the first waveguide 410 and the second waveguide 420, and finally matches the mode field of the external optical fiber.

[0096] Optionally, the number of the second waveguide 420 is one or more.

[0097] Optionally, in a direction pointing from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the second waveguide 420 is in an inverted wedge-shaped structure.

[0098] Further, in a thickness direction perpendicular to the supporting silicon 100 , an extension length of the second waveguide 420 is less than an extension length of the first waveguide 410 , and an end of the second waveguide 420 close to the outer end surface is flush with an end of the first waveguide 410 close to the outer end surface.

[0099] In some embodiments, there are multiple second waveguides 420 and multiple first waveguides 410; at a cross-sectional position close to the plane where the outer end surface is located, the combination of the multiple second waveguides 420 and the multiple first waveguides 410 is arranged in multiple rows and / or multiple columns. In this embodiment, the first waveguide 410 and the second waveguide 420 are configured to transmit the light coupled from the device waveguide 220 to the external optical fiber after performing a spot conversion (e.g., expanding the spot size of the light), or perform a spot conversion (e.g., shrinking the spot size of the light) on the light input from the external optical fiber, and couple the spot-converted light to the device waveguide 220.

[0100] In some embodiments, at least one of the plurality of second waveguides 420 has a constant cross-sectional width from the inside of the photonic integrated circuit chip 1000 to the outer end surface. Figure 5 As shown, at a cross-sectional position 2 of the photonic integrated circuit chip 1000 far from the outer end surface and at a cross-sectional position 1 of the photonic integrated circuit chip 1000 close to the outer end surface, the two second waveguides 420 have a constant cross-sectional width.

[0101] Optionally, the second waveguide 420 is a silicon nitride waveguide or a silicon oxynitride waveguide.

[0102] For example, Figure 5 As shown, at the cross-sectional position 3 far from the edge of the photonic integrated circuit chip 1000, there is only one first waveguide 410 in the lower layer, the cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 far from the edge of the photonic integrated circuit chip 1000, there are two first waveguides 410 and two second waveguides 420 at the same time. Among them, the cross-sectional size of the first waveguide 410 located on the left side of the lower layer is relatively large, the cross-sectional size of the other first waveguide 410 is relatively small, and the cross-sectional sizes of the two second waveguides 420 located on the upper layer are also relatively small, and the light field is mainly confined in the first waveguide 410 on the left side of the lower layer. At the cross-sectional position 1 close to the outer end face of the photonic integrated circuit chip 1000, the sizes of the two first waveguides 410 located on the lower layer and the two second waveguides 420 located on the upper layer are both small, and the light field is confined by the two first waveguides 410 in the lower layer, the two second waveguides 420 in the upper layer, and the surrounding silicon oxide. The upper and lower waveguide layers jointly participate in adjusting the size of the light field mode spot, which reduces the sensitivity of the shape or size of the single-layer waveguide itself to the mode field diameter of the single-layer waveguide while ensuring the coupling efficiency.

[0103] In the process of the first waveguide 410 located on the left side of the lower layer changing from the cross-sectional position 3 to the cross-sectional position 1, the cross-sectional size of the first waveguide 410 can change linearly or nonlinearly. In the process of the first waveguide 410 located on the left side of the lower layer changing from the cross-sectional position 3 to the cross-sectional position 1, the cross-sectional size of the first waveguide 410 located on the right side of the lower layer and the two second waveguides 420 located on the upper layer can change or remain unchanged ... lower layer changing from the cross-sectional position 3 to the cross-sectional position 1, the cross-sectional size of the first waveguide 410 located on the right side of the lower layer and the two second waveguides 420 located on the upper layer can have the same height or different heights; in the process of the first waveguide 410 located on the lower layer changing from the cross-sectional position 3 to the cross-sectional position 1, the cross-sectional size of the first waveguide 410 located on the right side of the lower layer and the two second waveguides 420 located on the upper layer can have the same height or different heights.

[0104] Figure 6 Shows Figure 4 Example 2 of the cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0105] As Figure 6 As shown, compared to Figure 5 In this example, from the cross-sectional position 2 to the cross-sectional position 1, the two first waveguides 410 located at the lower layer in the photonic integrated circuit chip gradually become thinner toward the outer end surface, while the cross-sectional dimensions of the two second waveguides 420 located at the upper layer toward the outer end surface remain unchanged. At this time, the mode spot conversion is simultaneously achieved by the changes of the two first waveguides 410 located at the lower layer.

[0106] Figure 7 Shows Figure 4 Example 3 of the cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0107] like Figure 7 As shown, compared to Figure 5 and Figure 6 Exemplarily, the number of the first waveguides 410 located in the lower layer is greater than two, for example, there are three, and the number of the second waveguides 420 located in the upper layer is also greater than two, for example, there are three.

[0108] Exemplarily, at the cross-sectional position 3 of the photonic integrated circuit chip away from the outer end face, there is only one first waveguide 410 in the middle of the lower layer. The cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there are three first waveguides 410 and three second waveguides 420 at the same time. Among them, the cross-sectional size of the first waveguide 410 located in the middle of the lower layer is relatively large, and the cross-sectional sizes of the other two first waveguides 410 and the three second waveguides 420 located in the upper layer are relatively small. The light field is mainly confined in the first waveguide 410 in the middle of the lower layer. At the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the sizes of the three first waveguides 410 located in the lower layer and the three second waveguides 420 located in the upper layer are relatively small, and the light field is confined by the three first waveguides 410 in the lower layer, the three second waveguides 420 in the upper layer and the surrounding silicon oxide.

[0109] Figure 8 Shows Figure 3 Example 4 of the cross-sectional schematic diagram of the edge coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0110] like Figure 8 As shown, compared to Figure 5 , Figure 6 and Figure 7 , the number of the first waveguides 410 located at the lower layer is two, and the number of the second waveguides 420 located at the upper layer is three.

[0111] Exemplarily, at the cross-sectional position 3 of the photonic integrated circuit chip away from the outer end face, there are only two first waveguides 410 in the lower layer. The cross-sectional dimensions of the two first waveguides 410 are relatively large, and the light field is mainly confined in the first waveguides 410. At the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there are two first waveguides 410 and three second waveguides 420 at the same time. Among them, the cross-sectional dimensions of the two first waveguides 410 located in the lower layer are relatively large, and the cross-sectional dimensions of the three second waveguides 420 located in the upper layer are relatively small, and the light field is mainly confined in the two first waveguides 410 in the lower layer. At the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the dimensions of the two first waveguides 410 in the lower layer and the three second waveguides 420 in the upper layer are both small. The light field is confined by the two first waveguides 410 in the lower layer, the three second waveguides 420 in the upper layer, and the surrounding silicon oxide.

[0112] Fig. 9 Shows Figure 4 Example 5 of the cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1 and position 2.

[0113] like Fig. 9 As shown, compared to Figure 5 , Figure 6 , Figure 7 and Figure 8 , the number of the first waveguides 410 located at the lower layer is one, and the number of the second waveguides 420 located at the upper layer is two.

[0114] Exemplarily, at the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there are a first waveguide 410 and two second waveguides 420. Among them, the cross-sectional size of the first waveguide 410 located in the lower layer is relatively large, and the cross-sectional sizes of the two second waveguides 420 located in the upper layer are relatively small, and the light field is mainly confined in the first waveguide 410 in the lower layer. At the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the sizes of the first waveguide 410 in the lower layer and the two second waveguides 420 in the upper layer are both small. The light field is confined by the first waveguide 410 in the lower layer, the two second waveguides 420 in the upper layer, and the surrounding silicon oxide.

[0115] Embodiment 3

[0116] Fig.10 A schematic structural diagram of a photonic integrated circuit chip provided in the third embodiment of the present application is shown. Fig.11 Shows Fig.10 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3.

[0117] like Fig.10 and Fig.11 As shown, in the third embodiment of the present application, the photonic integrated circuit chip 1000 further includes a third waveguide 430. The third waveguide 430 is located in the first silicon oxide layer 110. The third waveguide 430 is optically connected to the device waveguide 220. The third waveguide 430 is a silicon waveguide, and the third waveguide 430 is optically coupled with the first waveguide 410 and the second waveguide 420, respectively. And the third waveguide 430 is spaced apart from the first waveguide 410 and the second waveguide 420 in the thickness direction, respectively. In the thickness direction of the supporting silicon 100, the third waveguide 430 is located between the first waveguide 410 and the second waveguide 420. In the thickness direction perpendicular to the supporting silicon 100, the third waveguide 430 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface.

[0118] Furthermore, in some implementations, the third waveguide 430 and the device waveguide 220 are both located in the first silicon oxide layer 110 .

[0119] Further, in a direction perpendicular to the thickness of the supporting silicon 100, the extension length of the third waveguide 430 is greater than the extension length of the first waveguide 410, and the third waveguide 430 is optically connected to the device waveguide 220, so that the light field leaving the device waveguide 220 can be directly converted to the third waveguide 430 to avoid unnecessary loss of light energy. And the end of the third waveguide 430 close to the outer end surface is flush with the end of the first waveguide 410 close to the outer end surface.

[0120] Optionally, the number of the third waveguide 430 is 1 or more.

[0121] Further, in the cross-sectional direction close to the outer end surface, the plurality of first waveguides 410 and the plurality of second waveguides 420 surround the third waveguide 430 .

[0122] For example, Fig.11 As shown, at the cross-sectional position 3 of the photonic integrated circuit chip far from the outer end face, there is only one third waveguide 430 in the middle layer, the cross-sectional size of the third waveguide 430 is relatively large, and the light field is mainly confined in the third waveguide 430. At the cross-sectional position 2 of the photonic integrated circuit chip far from the outer end face, there are two first waveguides 410, two second waveguides 420 and one third waveguide 430, and the light field is still mainly confined in the third waveguide 430 located in the middle. At the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the sizes of the two first waveguides 410 in the lower layer, the two second waveguides 420 in the upper layer, and the third waveguide 430 in the middle layer are all relatively small, and the light field is confined by the two first waveguides 410 in the lower layer, the two second waveguides 420 in the upper layer, the third waveguide 430 in the middle layer, and the surrounding silicon oxide.

[0123] Embodiment 4

[0124] Fig.12 A schematic structural diagram of a photonic integrated circuit chip provided in the fourth embodiment of the present application is shown. Fig.13A Shows Fig.12 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3. Fig. 13B Shows Fig.12 A schematic cross-sectional view of the side coupler structure of the photonic integrated circuit chip provided in FIG. 1 at position 1, position 2 and position 3.

[0125] like Fig.12As shown, in the fourth embodiment of the present application, the photonic integrated circuit chip 1000 further includes a fourth waveguide 440. The fourth waveguide 440 is located in the second silicon oxide layer 120, and the fourth waveguide 440 is optically coupled with the first waveguide 410 and the second waveguide 420 respectively. And the fourth waveguide 440 is spaced apart from the first waveguide 410 and the second waveguide 420 in the thickness direction. In the thickness direction perpendicular to the supporting silicon 100, the fourth waveguide 440 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface. In the thickness direction of the supporting silicon 100, the fourth waveguide 440 is located on the side of the second waveguide 420 away from the first waveguide 410.

[0126] Optionally, in a direction pointing from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the fourth waveguide 440 is in an inverted wedge-shaped structure.

[0127] Further, in a thickness direction perpendicular to the supporting silicon 100 , an extension length of the fourth waveguide 440 is less than an extension length of the first waveguide 410 , and an end of the fourth waveguide 440 close to the outer end surface is flush with an end of the first waveguide 410 close to the outer end surface.

[0128] Specifically, Fig.13A and Fig. 13B As shown, the fourth embodiment of the present application relates to a process in which three layers of silicon nitride waveguides or silicon oxynitride waveguides participate in edge coupling, wherein the first waveguide 410 located at the bottom layer extends from the cross-sectional position 1 to the cross-sectional position 3.

[0129] For example, Fig.13AAs shown, at the cross-sectional position 3 of the photonic integrated circuit chip away from the outer end face, there is only one first waveguide 410 in the lower layer. The cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there are three first waveguides 410, three second waveguides 420 and three fourth waveguides 440. Among them, the cross-sectional size of the first waveguide 410 located in the middle of the lower layer is relatively large, and the cross-sectional sizes of the three fourth waveguides 440 located in the upper layer and the three second waveguides 420 located in the middle layer are relatively small, and the light field is mainly confined in the first waveguide 410 in the middle of the lower layer. At the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the cross-sectional sizes of the two first waveguides 410 located in the lower layer, the three second waveguides 420 located in the middle layer and the three fourth waveguides 440 located in the upper layer are all small. The light field is confined by the three first waveguides 410 at the bottom, the three second waveguides 420 at the middle, the three fourth waveguides 440 at the top and the surrounding silicon oxide. At this time, the light coupled in from outside the photonic integrated circuit chip 1000 is finally coupled into the first waveguide 410 at the bottom.

[0130] For example, Fig. 13B As shown, at the cross-sectional position 3 of the photonic integrated circuit chip away from the outer end face, there is only one first waveguide 410 in the lower layer. The cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 of the photonic integrated circuit chip away from the outer end face, there are two first waveguides 410, one second waveguide 420 and two fourth waveguides 440. Among them, the cross-sectional size of the first waveguide 410 located on the left side of the lower layer is relatively large, and the cross-sectional sizes of the two fourth waveguides 440 located on the upper layer and the second waveguide 420 located in the middle layer are relatively small. The light field is mainly confined in the first waveguide 410 on the left side of the lower layer. At the cross-sectional position 1 near the outer end face of the photonic integrated circuit chip, the sizes of the two first waveguides 410 at the lower layer, the two fourth waveguides 440 at the upper layer, and the second waveguide 420 at the middle layer are relatively small, and the light field is confined by the two first waveguides 410 at the lower layer, the second waveguide 420 at the middle layer, the two fourth waveguides 440 at the upper layer, and the surrounding silicon oxide. At this time, the light coupled in from the outside of the photonic integrated circuit chip 1000 is finally coupled into the first waveguide 410 at the lowest layer.

[0131] Embodiment 5

[0132] Fig.14 A schematic structural diagram of a photonic integrated circuit chip provided in the fifth embodiment of the present application is shown.

[0133] like Fig.14 As shown, in the fifth embodiment of the present application, the first waveguide 410 is arranged in the second silicon oxide layer 120. At this time, after the front-end process of the device waveguide 220 of the photonic integrated circuit chip (including the production of at least one corresponding functional layer on the device waveguide 220) is completed, the first waveguide 410 is produced on the side of the device waveguide 220 away from the supporting silicon 100. Since the back metal layer of the device waveguide 220 is relatively small, the degree of freedom of the position of the first waveguide 410 is relatively high.

[0134] Embodiment 6

[0135] Fig.15 A schematic structural diagram of a photonic integrated circuit chip provided in the sixth embodiment of the present application is shown.

[0136] like Fig.15 As shown, in the sixth embodiment of the present application, in the case where the first waveguide 410 is arranged in the second silicon oxide layer 120, the photonic integrated circuit chip 1000 further includes a fifth waveguide 450, the fifth waveguide 450 is located in the second silicon oxide layer 120, the fifth waveguide 450 is optically coupled with the first waveguide 410, and is spaced apart from the first waveguide 410 in the thickness direction; in the thickness direction perpendicular to the supporting silicon 100, the fifth waveguide 450 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface; in the thickness direction of the supporting silicon 100, the fifth waveguide 450 is located on the side of the first waveguide 410 away from the first silicon oxide layer 110.

[0137] Optionally, the number of the fifth waveguide 450 is 1 or more.

[0138] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the fifth waveguide 450 is in an inverted wedge-shaped structure.

[0139] Further, in a direction perpendicular to the thickness of the supporting silicon 100 , an extension length of the fifth waveguide 450 is less than an extension length of the first waveguide 410 , and an end of the fifth waveguide 450 close to the outer end surface is flush with an end of the first waveguide 410 close to the outer end surface.

[0140] Embodiment 7

[0141] Fig.16 A schematic structural diagram of a photonic integrated circuit chip provided in the seventh embodiment of the present application is shown. Fig.17 Shows Fig.16Another cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1, position 2 and position 3.

[0142] like Figure 16-Figure 17 As shown, in the seventh embodiment of the present application, on the basis of the sixth embodiment, the photonic integrated circuit chip 1000 further includes a sixth waveguide 460, the sixth waveguide 460 is located in the first silicon oxide layer 110, the sixth waveguide 460 is optically coupled with the first waveguide 410, and is spaced apart from the first waveguide 410 in the thickness direction; in the thickness direction perpendicular to the supporting silicon 100, the sixth waveguide 460 extends from the inside of the photonic integrated circuit chip 1000 to the outer end surface.

[0143] Optionally, the number of the sixth waveguide 460 is 1 or more.

[0144] Furthermore, in a direction pointing from the inside of the photonic integrated circuit chip 1000 to the outer end surface, a portion of the sixth waveguide 460 is in an inverted wedge-shaped structure.

[0145] For example, Fig.17 As shown, at the cross-sectional position 3 of the photonic integrated circuit chip far from the outer end surface, there is only one first waveguide 410 in the middle layer, the cross-sectional size of the first waveguide 410 is relatively large, and the light field is mainly confined in the first waveguide 410. At the cross-sectional position 2 of the photonic integrated circuit chip far from the outer end surface, there are one first waveguide 410, two fifth waveguides 450 and two sixth waveguides 460 at the same time, wherein the cross-sectional size of the first waveguide 410 located in the middle layer is relatively large, and the cross-sectional size of the two fifth waveguides 450 located in the upper layer is relatively large. 50 and the cross-sectional size of the sixth waveguide 460 located in the lower layer are relatively small, and the light field is mainly confined in the first waveguide 410 in the middle layer; at the cross-sectional position 1 of the photonic integrated circuit chip close to the outer end face, the sizes of the two sixth waveguides 460 located in the lower layer, the first waveguide 410 located in the middle layer, and the fifth waveguide 450 located in the upper layer are all small, and the light field is confined by the two sixth waveguides 460 in the lower layer, the first waveguide 410 in the middle layer, the two fifth waveguides 450 in the upper layer, and the surrounding silicon oxide. At this time, the light coupled in from the outside of the photonic integrated circuit chip 1000 is finally coupled into the first waveguide 410 in the middlemost layer.

[0146] Embodiment 8

[0147] Fig.18 A schematic structural diagram of a photonic integrated circuit chip provided in the eighth embodiment of the present application is shown. Fig.19 Shows Fig.18Another cross-sectional schematic diagram of the side coupler structure of the photonic integrated circuit chip provided in position 1.

[0148] like Fig.18 and Fig.19 As shown, in the seventh embodiment of the present application, compared with the second embodiment, in order to prevent water vapor from entering the upper silicon oxide of the photonic integrated circuit chip during long-term use, thereby causing the performance of the side waveguide to deteriorate, and to prevent the surface of the photonic integrated circuit chip from being easily affected by various dirt in process engineering such as bump and TSV, the photonic integrated circuit chip also includes a protective layer 500. The protective layer 500 covers the surface of the second silicon oxide layer 120 away from the first silicon oxide layer 110. The material of the protective layer 500 is silicon nitride.

[0149] Furthermore, the protective layer is also beneficial to improving the scratch resistance of the surface of the photonic integrated circuit chip.

[0150] According to another aspect of the present invention, there is also provided a silicon photonic integrated platform, comprising the photonic integrated circuit chip described in any of the aforementioned embodiments; an optical fiber, wherein the optical fiber comprises an optical fiber core and an optical fiber cladding covering the optical fiber core; wherein the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip for optical coupling.

[0151] Fig. 20 A structural schematic diagram of a silicon photonic integration platform provided in an embodiment of the present application is shown.

[0152] For example, Fig. 20 As shown, after the optical fiber and the photonic integrated circuit chip are coupled and aligned by active alignment, they are fixed to the outer end of the side coupler structure of the photonic integrated circuit chip by glue.

[0153] Fig.21 A cross-sectional schematic diagram of a silicon photonic integration platform provided in an embodiment of the present application is shown.

[0154] For example, Fig.21 As shown, in order to limit the position movement of the optical fiber, a groove 101 is provided at the cross-sectional position of the supporting silicon close to the outer end surface. The optical fiber is placed in the groove 101 .

[0155] Exemplarily, the groove 101 is a V-shaped groove, so that the optical fiber core and the optical fiber cladding are placed exactly in the V-shaped groove, and then glue is used to fix the optical fiber.

[0156] It should be noted that the “first”, “second”, “third”, “fourth”, “fifth” and “sixth” in this article are intended to distinguish different objects, rather than to sort the objects or limit the number of objects.

[0157] The embodiments of the present invention provide a solution for the optical interconnection between a photonic integrated circuit chip and an optical fiber, and aim to set a specific waveguide structure on the photonic integrated circuit chip to achieve efficient coupling with an ordinary single-mode optical fiber, while not introducing a suspended structure, so that the overall structure has strong mechanical stability, can pass the high temperature and high humidity reliability test conditions of the photonic integrated circuit chip, and is compatible with processes such as reflow soldering and through silicon vias.

[0158] Furthermore, the distance between the side coupler structure used for coupling during optical interconnection of photonic integrated circuits and the substrate can be optimized so that the light field does not leak into the substrate. The position and key dimensions of the single-layer waveguide and multi-layer waveguide in the side coupler structure can also be flexibly arranged as needed.

[0159] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications to the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A photonic integrated circuit chip, characterized in that: include: A supporting silicon, a first silicon oxide layer and a second silicon oxide layer are stacked; The photonic integrated circuit chip comprises an optical device arranged in the first silicon oxide layer and a device waveguide optically connected to the optical device, and the side of the photonic integrated circuit chip has an external end face coupled to the outside world; At least one first metal layer is also provided in the first silicon oxide layer, and in the thickness direction of the supporting silicon, the at least one first metal layer is located between the optical device and the supporting silicon; The photonic integrated circuit chip also includes a first waveguide, which is arranged in the first silicon oxide layer or the second silicon oxide layer. The first waveguide is optically coupled to the device waveguide. In a thickness direction perpendicular to the supporting silicon, the first waveguide extends from the inside of the photonic integrated circuit chip to the outer end surface. The first waveguide is configured to have a first mode size on a side away from the outer end surface and a second mode size on a side close to the outer end surface, wherein the first mode size is larger than the second mode size.

2. The photonic integrated circuit chip according to claim 1, characterized in that: In the thickness direction of the supporting silicon, the spacing between the first waveguide and the supporting silicon is larger than half of the mode field diameter of an external optical fiber to be optically coupled with the photonic integrated circuit chip.

3. The photonic integrated circuit chip according to claim 2, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the first waveguide is in an inverted wedge-shaped structure.

4. The photonic integrated circuit chip according to claim 2, characterized in that: The number of the first waveguides is 1 or more; When there are multiple first waveguides, the multiple first waveguides are located in the same film layer and placed side by side, and at least one of the multiple first waveguides gradually becomes thinner toward the outer end surface.

5. The photonic integrated circuit chip according to claim 2, characterized in that: In the case where the first waveguide is arranged in the first silicon oxide layer, the photonic integrated circuit chip further comprises a second waveguide, the second waveguide is arranged in the second silicon oxide layer, the second waveguide is optically coupled with the first waveguide, and is spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the second waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

6. The photonic integrated circuit chip according to claim 5, characterized in that: A portion of the second waveguide is in a reverse wedge-shaped structure in a direction pointing from the inside of the photonic integrated circuit chip to the outer end surface.

7. The photonic integrated circuit chip according to claim 5, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the second waveguide is smaller than an extension length of the first waveguide, and an end of the second waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

8. The photonic integrated circuit chip according to claim 7, characterized in that: The number of the second waveguides is plural, and the number of the first waveguides is plural; At a cross-sectional position close to the plane where the outer end surface is located, the combination of the plurality of second waveguides and the plurality of first waveguides is arranged in a plurality of rows and / or a plurality of columns.

9. The photonic integrated circuit chip according to claim 8, characterized in that: At a cross-sectional position close to the plane where the outer end surface is located, between adjacent rows and / or columns, the plurality of second waveguides and the plurality of first waveguides are arranged in a staggered or irregular manner.

10. The photonic integrated circuit chip according to claim 7, characterized in that: At least one second waveguide among the plurality of second waveguides has a constant cross-sectional width directed from the inside of the photonic integrated circuit chip to the outer end surface.

11. The photonic integrated circuit chip according to claim 5, characterized in that: The photonic integrated circuit chip further includes a third waveguide, the third waveguide is located in the first silicon oxide layer, the third waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the third waveguide is spaced apart from the first waveguide and the second waveguide respectively in a thickness direction; In the thickness direction of the supporting silicon, the third waveguide is located between the first waveguide and the second waveguide; In a direction perpendicular to the thickness of the supporting silicon, the third waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

12. The photonic integrated circuit chip according to claim 11, characterized in that: The third waveguide and the device waveguide are both located in the first silicon oxide layer.

13. The photonic integrated circuit chip according to claim 11, characterized in that: In a thickness direction perpendicular to the supporting silicon, the extension length of the third waveguide is greater than that of the first waveguide, the third waveguide is optically connected to the device waveguide, and an end of the third waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

14. The photonic integrated circuit chip according to claim 13, characterized in that: In a cross-sectional direction close to the outer end surface, a plurality of first waveguides and a plurality of second waveguides surround the periphery of the third waveguide.

15. The photonic integrated circuit chip according to claim 5, characterized in that: The photonic integrated circuit chip further includes a fourth waveguide, the fourth waveguide is located in the second silicon oxide layer, the fourth waveguide is optically coupled with the first waveguide and the second waveguide respectively, and the fourth waveguide is spaced apart from the first waveguide and the second waveguide respectively in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the fourth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface; In a thickness direction of the supporting silicon, the fourth waveguide is located on a side of the second waveguide facing away from the first waveguide.

16. The photonic integrated circuit chip according to claim 15, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the fourth waveguide is in an inverted wedge-shaped structure.

17. The photonic integrated circuit chip according to claim 16, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the fourth waveguide is smaller than an extension length of the first waveguide, and an end of the fourth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

18. The photonic integrated circuit chip according to claim 1, characterized in that: In the case where the first waveguide is arranged in the second silicon oxide layer, the photonic integrated circuit chip further comprises a fifth waveguide, the fifth waveguide is arranged in the second silicon oxide layer, the fifth waveguide is optically coupled with the first waveguide, and is spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the fifth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface; In the thickness direction of the supporting silicon, the fifth waveguide is located on a side of the first waveguide away from the first silicon oxide layer.

19. The photonic integrated circuit chip according to claim 18, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the fifth waveguide is in an inverted wedge-shaped structure.

20. The photonic integrated circuit chip according to claim 19, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the fifth waveguide is shorter than an extension length of the first waveguide, and an end of the fifth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

21. The photonic integrated circuit chip according to claim 18, characterized in that: The photonic integrated circuit chip further includes a sixth waveguide, the sixth waveguide being located in the first silicon oxide layer, the sixth waveguide being optically coupled to the first waveguide, and being spaced apart from the first waveguide in a thickness direction; In a direction perpendicular to the thickness of the supporting silicon, the sixth waveguide extends from the interior of the photonic integrated circuit chip to the outer end surface.

22. The photonic integrated circuit chip according to claim 21, characterized in that: From the inside of the photonic integrated circuit chip to the direction of the outer end surface, a portion of the sixth waveguide is in an inverted wedge-shaped structure.

23. The photonic integrated circuit chip according to claim 22, characterized in that: In a direction perpendicular to the thickness of the supporting silicon, an extension length of the sixth waveguide is smaller than an extension length of the first waveguide, and an end of the sixth waveguide close to the outer end surface is flush with an end of the first waveguide close to the outer end surface.

24. The photonic integrated circuit chip according to claim 1, characterized in that: At least one second metal layer is also disposed in the second silicon oxide layer, and the at least one second metal layer is electrically connected to the at least one first metal layer through a metal through hole.

25. The photonic integrated circuit chip according to claim 1, characterized in that: The photonic integrated circuit chip further comprises a third silicon oxide layer, Wherein, in the thickness direction of the supporting silicon, the third silicon oxide layer is arranged between the first silicon oxide layer and the supporting silicon.

26. The photonic integrated circuit chip according to claim 1, characterized in that: The photonic integrated circuit chip further comprises a protective layer, wherein the protective layer covers a surface of the second silicon oxide layer on a side away from the first silicon oxide layer; Wherein, the material of the protective layer is silicon nitride.

27. The photonic integrated circuit chip according to claim 1, characterized in that: The optical device includes one or a combination of a photodetector, a laser, a modulator and a wavelength division multiplexer.

28. A silicon photonic integration platform, characterized in that: A photonic integrated circuit chip comprising any one of claims 1 to 27; An optical fiber, comprising an optical fiber core and an optical fiber cladding covering the optical fiber core; Wherein, the optical fiber is aligned with the outer end surface of the photonic integrated circuit chip to perform optical coupling.

29. The silicon photonic integrated platform according to claim 28, characterized in that: A groove is arranged at a cross-sectional position of the supporting silicon close to the outer end surface, and the optical fiber is placed in the groove.

Images