Dual-redundancy power supply CPU architecture and operation method thereof

Abstract

The invention discloses a dual-redundancy power supply CPU architecture and an operation method thereof, and relates to the technical field of aviation power distribution. In the design of the dual-redundancy power supply CPU board, the power supply sources of the main CPU board and the standby CPU board do not depend on the combination of dual-redundancy power supply frameworks in a single power supply board, but come from the output of the power supply in the board card of the main CPU board and the standby CPU board, so that the power supply safety of the CPU board components is achieved; a two-way contactor is designed for the important key load, a dual-redundancy output circuit is designed in a main and standby power supply CPU board, and each redundancy can control the two-way important key load contactor so as to achieve the safety of the important key load control capability; if the main board fails, the main board is automatically switched to the standby board by means of mechanisms such as whether a key load can be controlled or not and communication self-checking, so that the safety of the dual-redundancy architecture is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of aviation power distribution systems, and in particular relates to a dual-redundancy power supply CPU architecture and an operating method thereof. Background Art

[0002] In the design of the main / standby CPU unit architecture in the field of electrical technology, the following design situations usually occur:

[0003] 1) When a single power board is used to power both the main CPU board and the standby CPU board, a single-point power supply situation will occur. When the power board fails, the main / standby CPU boards will fail at the same time;

[0004] 2) When dual power boards are used to power the main CPU board and the standby CPU board at the same time, a single-point power supply situation will also occur. When a short circuit occurs at the power supply point of the main / standby CPU board, it will cause a power supply short circuit failure on power board 1 / 2, which will cause the standby / main CPU board to fail;

[0005] 3) For the driving of critical and important loads, using a separate output board for drive control may also cause the critical load to be uncontrollable due to a single point failure. Summary of the invention

[0006] In order to solve the deficiencies in the above-mentioned prior art, the present invention designs a dual-redundancy power supply CPU architecture in order to reduce the occurrence of single-point hidden dangers in the design of the main / standby CPU board architecture. The power supplies of the main / standby CPU boards are not combined, and the power supply of the CPU board comes from the power output of this board; key load output controls are all reflected in the main / standby CPU boards.

[0007] In view of this, according to one aspect of an embodiment of the present invention, a dual-redundancy power supply CPU architecture is provided, including: a main core board, a spare core board, a first key load contactor drive control circuit and a second key load contactor drive control circuit;

[0008] The main core board is composed of a first power supply unit and a main CPU unit. The first power supply unit is used to supply power to the main CPU unit. The first main control chip in the main CPU unit outputs an on-off signal to the first MOS tube drive circuit to control the on-off of the MOS tube. The first discrete quantity acquisition circuit collects the on-off state of the MOS tube and transmits it to the first main control chip.

[0009] The standby core board is composed of a second power supply unit and a standby CPU unit. The second power supply unit is used to supply power to the standby CPU unit. The second main control chip in the standby CPU unit outputs a connection signal to the second MOS tube drive circuit to control the on and off of the MOS tube. The second discrete quantity acquisition circuit collects the on and off state of the MOS tube and transmits it to the second main control chip.

[0010] The key load contactor is designed with dual redundancy, and the rear-end equipment of its main contact can be reliably connected to the grid. A dual redundancy output circuit is designed in the main / backup power supply CPU board, and each redundancy controls two important key load contactors.

[0011] The first key load contactor drive control circuit is a drive signal A output by the main CPU unit in the main core board and a drive signal C output by the standby CPU unit in the standby core board to jointly control the positive end of the first key load contactor coil;

[0012] The second key load contactor drive control circuit is a drive signal B output by the main CPU unit in the main core board and a drive signal D output by the standby CPU unit in the standby core board to jointly control the second key load contactor coil positive end;

[0013] The main CPU unit and the standby CPU unit are connected by a bus for communication.

[0014] Optionally, the power supply source of the main CPU unit and the standby CPU unit comes from the output of the power supply in their own boards.

[0015] Optionally, the MOS tube power input of the first MOS tube output drive circuit in the main CPU unit is provided by the 28V DC power of the main core board, and the MOS tube power input of the second MOS tube output drive circuit in the standby CPU unit is provided by the 28V DC power of the standby core board.

[0016] Optionally, the 28V direct current on the main core board and the standby core board is respectively taken from different positions of the 28V bus bar through a plurality of wires and crimping terminals.

[0017] Optionally, the negative ends of the first and second critical load contactor coils are respectively connected to two power-taking points of the ground bus bar through two wires and two independent crimping terminals.

[0018] According to another aspect of an embodiment of the present invention, there is also provided an operation method of a dual-redundancy power supply CPU architecture, using any of the described architectures, including: when the CPU unit of the main core board fails, the CPU unit of the standby core board sends a reset signal to the CPU unit of the main core board, and then switches to the standby core board to control the first critical load contactor drive control circuit and the second critical load contactor drive control circuit; if the standby core board CPU unit is currently performing output control, the main core board CPU unit performs hot backup. When the standby core board CPU unit fails, the CPU unit of the main core board sends a reset signal to the CPU unit of the standby core board, and then switches to the main core board to control the first critical load contactor drive control circuit and the second critical load contactor drive control circuit.

[0019] Optionally, when the main core board outputs drive control signals A and B, the standby core board does not output drive control signals C and D, and performs hot backup. When the board is switched to the standby core board, drive control signals C and D are output.

[0020] Optionally, it also includes a main core board and a spare core board switching component: when any of the following two situations occur, it can be determined that the main core board CPU unit or the spare core board CPU unit has failed and switching is performed: 1) the main core board or the spare core board cannot control the on / off of the first critical load contactor and the second critical load contactor; 2) an abnormality occurs in the communication between the main CPU unit and the spare CPU unit.

[0021] In summary, the present invention can reduce the hidden dangers of single-point power supply and single-point critical load control, improve the security of the main / standby CPU architecture, and has high reliability and strong practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a principle block diagram of the dual-redundancy power supply CPU architecture provided by the present invention.

[0023] Figure 2 It is a specific implementation principle diagram of the dual-redundancy power supply CPU architecture provided by the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] According to one aspect of an embodiment of the present invention, a dual-redundancy power supply CPU architecture is provided, which mainly includes: a main core board, a spare core board, a first key load contactor drive control circuit and a second key load contactor drive control circuit;

[0026] The main core board is composed of a first power supply unit and a main CPU unit. The first power supply unit is used to supply power to the main CPU unit. The first main control chip in the main CPU unit outputs an on-off signal to the first MOS tube drive circuit to control the on-off of the MOS tube. The first discrete quantity acquisition circuit collects the on-off state of the MOS tube and transmits it to the first main control chip.

[0027] The standby core board is composed of a second power supply unit and a standby CPU unit. The second power supply unit is used to supply power to the standby CPU unit. The second main control chip in the standby CPU unit outputs a connection signal to the second MOS tube drive circuit to control the on and off of the MOS tube. The second discrete quantity acquisition circuit collects the on and off state of the MOS tube and transmits it to the second main control chip.

[0028] The key load contactor is designed with dual redundancy, and the rear-end equipment of its main contact can be reliably connected to the grid. A dual redundancy output circuit is designed in the main / backup power supply CPU board, and each redundancy controls two important key load contactors.

[0029] The first key load contactor drive control circuit is a drive signal A output by the main CPU unit in the main core board and a drive signal C output by the standby CPU unit in the standby core board to jointly control the positive end of the first key load contactor coil;

[0030] The second key load contactor drive control circuit is a drive signal B output by the main CPU unit in the main core board and a drive signal D output by the standby CPU unit in the standby core board to jointly control the second key load contactor coil positive end;

[0031] The main CPU unit and the standby CPU unit are connected by a bus for communication.

[0032] Furthermore, the power supply source of the main CPU unit and the standby CPU unit comes from the output of the power supply in their own boards.

[0033] Furthermore, the MOS tube power input of the first MOS tube output drive circuit in the main CPU unit is provided by the 28V DC power of the main core board, and the MOS tube power input of the second MOS tube output drive circuit in the standby CPU unit is provided by the 28V DC power of the standby core board.

[0034] Furthermore, the 28V DC power on the main core board and the standby core board is taken from different positions of the 28V bus bar through multiple wires and crimping terminals. Different power supply positions can reduce single-point hidden dangers and reflect the safety of the architecture design.

[0035] Furthermore, the negative ends of the first and second critical load contactor coils are connected to two power points of the ground bus bar through two wires and two independent crimping terminals, respectively, to avoid single point failures caused by single line and terminal failures, reflecting the safety of the architecture design.

[0036] According to another aspect of an embodiment of the present invention, there is also provided an operation method of a dual-redundancy power supply CPU architecture, using any of the described architectures, including: when the CPU unit of the main core board fails, the CPU unit of the standby core board sends a reset signal to the CPU unit of the main core board, and then switches to the standby core board to control the first critical load contactor drive control circuit and the second critical load contactor drive control circuit; if the standby core board CPU unit is currently performing output control, the main core board CPU unit performs hot backup. When the standby core board CPU unit fails, the CPU unit of the main core board sends a reset signal to the CPU unit of the standby core board, and then switches to the main core board to control the first critical load contactor drive control circuit and the second critical load contactor drive control circuit.

[0037] Furthermore, when the main core board outputs drive control signals A and B, the standby core board does not output drive control signals C and D, and performs hot backup. When the board is switched to the standby core board, drive control signals C and D are output.

[0038] Furthermore, it also includes a main core board and a spare core board switching component: when any of the following two situations occur, it can be determined that the main core board CPU unit or the spare core board CPU unit has failed and switching is performed: 1) the main core board or the spare core board cannot control the on / off of the first key load contactor and the second key load contactor; 2) an abnormality occurs in the communication between the main CPU unit and the spare CPU unit.

[0039] Example

[0040] like Figure 1-2 As shown, the dual-redundancy CPU architecture includes a main core board, a spare core board, a first key load contactor drive control circuit, and a second key load contactor drive control circuit.

[0041] The 28V to 5V circuit in the main core board converts the 28V_A signal input by the external bus bar into 5V_A to power the main CPU. The OP_A1 and OP_A2 of the main CPU are respectively connected to the MOS tube A1 and MOS tube A2 to control their on and off. The MOS tube output drive circuit outputs OUT_A1 and OUT_A2 signals to control the positive ends of the first and second key load contactor coils respectively. At the same time, the OB_A1 and OB_A2 pins in the discrete quantity acquisition circuit collect the OUT_A1 and OUT_A2 signals to obtain the on and off / status of the MOS tube A1 and MOS tube A2. The HC_A1 and HC_A2 pins in the discrete quantity acquisition circuit are connected to the IP_A1 and IP_A2 of the main CPU to report the status of the MOS tube.

[0042] The 28V to 5V circuit in the standby core board converts the 28V_B signal input by the external bus bar into 5V_B to power the standby CPU. The OP_B1 and OP_B2 of the standby CPU are respectively connected to the MOS tube B1 and MOS tube B2 to control their on and off. The MOS tube output drive circuit outputs OUT_B1 and OUT_B2 signals to control the positive ends of the first and second key load contactor coils respectively. At the same time, the OB_B1 and OB_B2 pins in the discrete quantity acquisition circuit collect the OUT_B1 and OUT_B2 signals to obtain the on and off / status of the MOS tube B1 and MOS tube B2. The HC_B1 and HC_B2 pins in the discrete quantity acquisition circuit are connected to the IP_B1 and IP_B2 of the standby CPU to report the status of the MOS tube.

[0043] The WDI_A pin of the main CPU is connected to the RES_B pin of the standby CPU so that when the standby core board fails, the standby CPU can be reset and switched to the main core board; the WDI_B pin of the standby CPU is connected to the RES_A pin of the main CPU so that when the main core board fails, the main CPU can be reset and switched to the standby core board. The negative ends of the first and second key load contactor coils are respectively connected to the two power points of the ground bus bar.

[0044] First, the main core board controls the first and second key load contactors. When the communication sent by the main CPU unit to the standby CPU unit is abnormal or the first and second key load contactors cannot be turned on / off, the main core board is determined to be failed, and the WDI_B pin of the standby CPU sends a reset signal to the WDI_A pin of the main CPU. At this time, the standby core board controls the first and second key load contactors. When both the main and standby CPU boards are working normally, the two communicate through the RS422 bus.

[0045] Example 2

[0046] A dual-redundancy power supply CPU architecture operation method for reducing single-point hidden dangers, comprising:

[0047] Main core board, spare core board, first key load contactor drive control circuit, second key load contactor drive control circuit;

[0048] The main core board in the dual-redundancy power supply CPU architecture is composed of a first power supply unit and a main CPU unit. The 28V DC on the 28V bus bar enters the main core board, and the 28V DC is converted into 5V DC through a 28V to 5V circuit in the power board, and then used for 5V power supply of the main CPU board. The main CPU board includes a main control chip, a discrete quantity acquisition circuit, and a MOS tube output drive circuit, wherein the MOS tube power input signal in the MOS tube output drive circuit is derived from the 28V DC of the main core board, and the main control chip in the main CPU board controls the MOS tube to be turned on, so that the MOS tube output drive circuit outputs the main CPU board output drive signal A and the main CPU board output drive signal B, and at the same time, the discrete quantity acquisition circuit collects the on-off state of the MOS tube and transmits it to the main control chip.

[0049] The standby core board in the dual-redundancy power supply CPU architecture is composed of a second power supply unit and a standby CPU unit. The 28V DC on the 28V bus bar enters the standby core board, and the 28V DC is converted into 5V DC through a 28V to 5V circuit in the power board, and then used for 5V power supply of the standby CPU board. The standby CPU board includes a main control chip, a discrete quantity acquisition circuit, and a MOS tube output drive circuit, wherein the MOS tube power input signal in the MOS tube output drive circuit is derived from the 28V DC of the standby core board, and the main control chip in the standby CPU board controls the MOS tube to be turned on, so that the MOS tube output drive circuit outputs the standby CPU board output drive signal C and the standby CPU board output drive signal D, and at the same time, the discrete quantity acquisition circuit collects the on-off state of the MOS tube and transmits it to the main control chip.

[0050] The control method of the first key load contactor driving control circuit in the dual-redundancy power supply CPU architecture is as follows: the main CPU board output driving signal A output by the main CPU board in the main core board and the standby CPU board output driving signal C output by the standby CPU board in the standby core board jointly control the positive end of the first key load contactor coil, and the negative end of the first key load contactor coil is connected to the ground bus bar, so as to ensure the control reliability of the first key load contactor.

[0051] The control method of the second key load contactor driving control circuit in the dual-redundancy power supply CPU architecture is as follows: the main CPU board output driving signal B output by the main CPU board in the main core board and the standby CPU board output driving signal D output by the standby CPU board in the standby core board jointly control the positive end of the second key load contactor coil, and the negative end of the second key load contactor coil is connected to the ground bus bar, so as to ensure the control reliability of the second key load contactor.

[0052] In the dual-redundancy power supply CPU architecture, the 28V DC power on the main core board and the standby core board is obtained from two different positions of the 28V bus bar to reduce the hidden dangers of single-point power supply; the power supply of the main CPU board and the standby CPU board is not combined, that is, the main CPU board is powered by the first power supply unit, and the standby CPU board is powered by the second power supply unit. The purpose of this architecture design is to eliminate the coupling relationship between the main / standby CPU boards, reduce the hidden dangers of single-point power supply, ensure that when the main core board and the standby core board fail, they will not affect each other, and ensure the power supply safety of the architecture.

[0053] The MOS tube power input of the MOS tube output drive circuit in the main CPU board is provided by the 28V DC power of the main core board, and the MOS tube power input of the MOS tube output drive circuit in the standby CPU board is provided by the 28V DC power of the standby core board, so as to ensure that both the main and standby CPUs can output drive control signals without coupling relationship, thereby reducing single-point hidden dangers; and the positive terminals of the coils of the first and second key load contactors are connected to the output drive control signals issued by the main and standby CPUs for control, and the negative terminals of the coils are respectively connected to the two power supply points of the ground bus through two wires and two independent terminals, thereby avoiding single-point failure caused by single line and terminal failure, thereby reducing the risk of the first and second key load contactors failing at the same time and causing power supply failure of the entire machine, thereby ensuring the control safety of the key load contactors.

[0054] When the main core board cannot control the first and second key load contactors or the main CPU board communication self-test is abnormal, the main core board is judged to be failed, and then the standby CPU board sends a reset signal to the main CPU board, switching to the standby core board to control the first and second key load contactors; when the standby core board cannot control the first and second key load contactors or the standby CPU board communication self-test is abnormal, the standby core board is judged to be failed, and then the main CPU board sends a reset signal to the standby CPU board, switching to the main core board to control the first and second key load contactors. The main and standby core board switching mechanism reflects the system security and ensures the redundancy of key load contactor control.

[0055] The above is only a specific embodiment of the present invention, and the present invention is described in detail. The unexplained part is a conventional technology. However, the protection scope of the present invention is not limited to this. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A dual-redundant power supply CPU architecture, characterized in that: include: A main core board, a standby core board, a first key load contactor drive control circuit, and a second key load contactor drive control circuit; The main core board is composed of a first power supply unit and a main CPU unit. The first power supply unit is used to supply power to the main CPU unit. The first main control chip in the main CPU unit outputs an on-off signal to the first MOS tube drive circuit to control the on-off of the MOS tube. The first discrete quantity acquisition circuit collects the on-off state of the MOS tube and transmits it to the first main control chip. The standby core board is composed of a second power supply unit and a standby CPU unit. The second power supply unit is used to supply power to the standby CPU unit. The second main control chip in the standby CPU unit outputs a connection signal to the second MOS tube drive circuit to control the on and off of the MOS tube. The second discrete quantity acquisition circuit collects the on and off state of the MOS tube and transmits it to the second main control chip. The key load contactor is designed with dual redundancy, and the rear-end equipment of its main contact can be reliably connected to the grid. A dual redundancy output circuit is designed in the main / backup power supply CPU board, and each redundancy controls two important key load contactors. The first key load contactor drive control circuit is a drive signal A output by the main CPU unit in the main core board and a drive signal C output by the standby CPU unit in the standby core board to jointly control the positive end of the first key load contactor coil; The second key load contactor drive control circuit is a drive signal B output by the main CPU unit in the main core board and a drive signal D output by the standby CPU unit in the standby core board to jointly control the second key load contactor coil positive end; The main CPU unit and the standby CPU unit are connected by a bus for communication.

2. The dual-redundant power supply CPU architecture according to claim 1, characterized in that: The power supply source of the main CPU unit and the standby CPU unit comes from the output of the power supply in their own boards.

3. The dual-redundant power supply CPU architecture according to claim 1, characterized in that: The MOS tube power input of the first MOS tube output drive circuit in the main CPU unit is provided by the 28V DC power of the main core board, and the MOS tube power input of the second MOS tube output drive circuit in the standby CPU unit is provided by the 28V DC power of the standby core board.

4. The dual-redundant power supply CPU architecture according to claim 1, characterized in that: The 28V DC power on the main core board and the standby core board is taken from different positions of the 28V bus bar through multiple wires and crimping terminals.

5. The dual-redundant power supply CPU architecture according to claim 1, characterized in that: The negative ends of the first and second key load contactor coils are connected to two power-taking points of the ground bus bar through two wires and two independent crimping terminals.

6. A method for operating a dual-redundant power supply CPU architecture, characterized in that: Using any of the architectures described in claims 1-5, including: when the CPU unit of the main core board fails, the CPU unit of the standby core board sends a reset signal to the CPU unit of the main core board, and then switches to the standby core board to control the first critical load contactor drive control circuit and the second critical load contactor drive control circuit; if the standby core board CPU unit is currently performing output control, the main core board CPU unit performs hot backup. When the CPU unit of the standby core board fails, the CPU unit of the main core board sends a reset signal to the CPU unit of the standby core board, and then switches to the main core board to control the first key load contactor drive control circuit and the second key load contactor drive control circuit.

7. The method according to claim 6, characterized in that When the main core board outputs drive control signals A and B, the standby core board does not output drive control signals C and D, and performs hot backup. When the board is switched to the standby core board, drive control signals C and D are output.

8. The method according to claim 6, characterized in that It also includes a main core board and a spare core board switching component: when any of the following two situations occur, it can be determined that the main core board CPU unit or the spare core board CPU unit has failed and switching is performed: 1) the main core board or the spare core board cannot control the on / off of the first key load contactor and the second key load contactor; 2) an abnormality occurs in the communication between the main CPU unit and the spare CPU unit.

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