Adaptive slew rate enhanced input stage circuit

Abstract

The invention relates to the field of integrated circuit design. In order to enable an operational amplifier to quickly drive a large capacitive load, the invention provides a self-adaptive slew rate enhanced input stage circuit. The circuit has relatively low power consumption during small-signal working, but provides relatively high conversion current during large-signal conversion, so that the slew rate is remarkably improved. Therefore, the slew rate is obviously enhanced on the premise that the static power consumption is not increased.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to an adaptive slew rate enhanced input stage circuit. Background Art

[0002] Operational amplifiers are an important part of analog circuits and are widely used in circuits such as analog-to-digital converters, digital-to-analog converters, and high-speed interfaces. In high-speed circuits that process large signals, the conversion process of operational amplifiers is an undesirable phenomenon. During the conversion process, the speed at which the current charges and discharges the main capacitors in the circuit will affect the speed of the large signal, that is, the slew rate will limit the speed of the large signal. If the slew rate is too small, it will cause output distortion. Therefore, it is necessary to increase the slew rate of the operational amplifier.

[0003] The common method to improve the slew rate is to increase the bias current. The disadvantage of this method is that it increases the power consumption of the op amp. If only the current for charging and discharging the capacitor during the conversion period is increased, low power consumption and enhanced slew rate can be achieved. Summary of the invention

[0004] The object of the present invention is to provide an input stage circuit for improving the slew rate of an operational amplifier, so as to solve the problem that the slew rate of the operational amplifier is too low.

[0005] To achieve the above-mentioned purpose, the present invention provides an adaptive slew rate enhancement input stage circuit, which includes a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a fifth NPN transistor, a sixth NPN transistor, a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a tenth NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first current source, a second current source, a first input terminal, a second input terminal, a first output terminal, a second output terminal, a positive power supply and a negative power supply.

[0006] The emitter of the first PNP transistor is connected to the emitter of the fifth NPN transistor; the base of the first PNP transistor and the base of the second PNP transistor are both connected to the first input terminal IN1; the collector of the first PNP transistor, the emitter of the ninth NPN transistor, the emitter of the tenth NPN transistor and the collector of the fourth PNP transistor are all connected to a negative power supply; the base and collector of the fifth NPN transistor, the base of the sixth NPN transistor and the left end of the fourth resistor are all connected to the lower end of the first current source; the upper end of the first current source, the upper end of the first resistor, the upper end of the second resistor and the upper end of the second current source are all connected to a positive power supply; the collector of the sixth NPN transistor is connected to the lower end of the first resistor; the emitter of the sixth NPN transistor is connected to the seventh NPN transistor; The emitters of the transistors are all connected to the upper end of the third resistor; the emitters of the second PNP transistor and the emitters of the third PNP transistor are all connected to the lower end of the third resistor; the collector of the second PNP transistor, the base and the collector of the ninth NPN transistor are all connected to the second output end; the collector of the seventh NPN transistor is connected to the lower end of the second resistor; the base of the seventh NPN transistor, the base and the collector of the eighth NPN transistor, and the right end of the fourth resistor are all connected to the lower end of the second current source; the emitter of the eighth NPN transistor is connected to the emitter of the fourth PNP transistor; the base of the fourth PNP transistor and the base of the third PNP transistor are all connected to the second input end; the collector of the third PNP transistor and the base and the collector of the tenth NPN transistor are all connected to the first output end.

[0007] Furthermore, the adaptive slew rate enhanced input stage circuit is characterized in that the first resistor and the second resistor have the same resistance value; the second PNP transistor and the third PNP transistor have the same size; the first PNP transistor and the fourth PNP transistor have the same size; the sixth NPN transistor and the seventh NPN transistor have the same size; the fifth NPN transistor and the eighth NPN transistor have the same size; the ninth NPN transistor and the tenth NPN transistor have the same size; the current value of the first current source is equal to that of the second current source; the size ratio of the first PNP transistor and the second PNP transistor is m:1; the size ratio of the fifth NPN transistor and the sixth NPN transistor is n:1.

[0008] Furthermore, the adaptive slew rate enhanced input stage circuit is characterized in that, when the circuit is in a static state, the current in the third resistor is set by a loop consisting of the first PNP transistor, the fifth NPN transistor, the sixth NPN transistor, the third resistor and the second PNP transistor, or a loop consisting of the fourth PNP transistor, the eighth NPN transistor, the seventh NPN transistor, the third resistor and the third PNP transistor; when the circuit is in a small signal working state, point G and point H are approximately virtually shorted, and a smaller small signal current flows through the third resistor; when the circuit is in a large signal working state, most of the difference between the first input terminal signal and the second input terminal signal falls on the third resistor, that is, the current flowing through the third resistor during the large signal conversion is larger than that in the static state, thereby enhancing the slew rate; the function of the fourth resistor is to limit the maximum current flowing through the third resistor.

[0009] The advantages of the present invention are: when the circuit is in a static or small signal working state, the power consumption is low; when the circuit is in a large signal working state, the conversion current increases adaptively, thereby enhancing the slew rate. That is, the slew rate is enhanced without increasing the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is the schematic diagram of the adaptive slew rate enhanced input stage circuit.

[0011] Description of reference numerals: Q 1 To Q 4 Respectively represent the first PNP transistor to the fourth PNP transistor; Q 5 To Q 10 Respectively represent the fifth NPN transistor to the tenth NPN transistor; R 1 To R 4 Respectively represent the first resistor to the fourth resistor; I 1 with I 2 Respectively represent the first current source and the second current source; IN 1 with IN 2 Respectively represent the first input terminal and the second input terminal; V O1 With V O2 Respectively represent the first output terminal and the second output terminal; V CC With V EE Represent the positive power supply and the negative power supply respectively; A to F represent the names of the nodes in the figure respectively. DETAILED DESCRIPTION

[0012] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art.

[0013] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0014] like Figure 1 As shown, this embodiment provides an adaptive slew rate enhanced input stage circuit, which includes:

[0015] The first PNP transistor Q 1 , the second PNP transistor Q 2 、The third PNP transistor Q 3 、The fourth PNP transistor Q 4 、The fifth NPN transistor Q 5 、The sixth NPN transistor Q 6 、The seventh NPN transistor Q 7 、The eighth NPN transistor Q 8 、The ninth NPN transistor Q 9 、The tenth NPN transistor Q 10 , the first resistor R 1 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the first current source I 1 , the second current source I 2 , the first input terminal IN 1 , the second input terminal IN 2 , the first output terminal V O1 , the second output terminal V O2 , Positive power supply V CC And the negative power supply V EE .

[0016] The first PNP transistor Q 1 The emitter of the fifth NPN transistor Q 5 The emitter of the first PNP transistor Q 1The base of the second PNP transistor Q 2 The bases of the two terminals are connected to the first input terminal IN 1 ; The first PNP transistor Q 1 The collector of the ninth NPN transistor Q 9 The emitter of the tenth NPN transistor Q 10 The emitter of the fourth PNP transistor Q 4 The collectors are connected to the negative power supply V EE ; The fifth NPN transistor Q 5 The base and collector of the sixth NPN transistor Q 6 The base and the fourth resistor R 4 The left end of each is connected to the first current source I 1 The lower end of the first current source I 1 The upper end of the first resistor R 1 The upper end of the second resistor R 2 The upper end of the second current source I 2 The upper end of the positive power supply V CC Connection: The sixth NPN transistor Q 6 The collector and the first resistor R 1 The lower end of the sixth NPN transistor Q 6 The emitter of the seventh NPN transistor Q 7 The emitter of the third resistor R 3 The upper end of the second PNP transistor Q 2 The emitter of the third PNP transistor Q 3 The emitter of the third resistor R 3 The lower end of the second PNP transistor Q 2 The collector of the ninth NPN transistor Q 9 The base and collector of the O2 ; The seventh NPN transistor Q 7 The collector and the second resistor R 2 The lower end of the seventh NPN transistor Q 7 The base of the eighth NPN transistor Q 8 The base and collector of the fourth resistor R 4 The right end of each of the eighth NPN transistor Q 8 The emitter of the fourth PNP transistor Q 4 The emitter of the fourth PNP transistor Q 4 The base of the third PNP transistor Q 3 The base of both are connected to the second input terminal IN 2 ; The third PNP transistor Q 3The collector of the tenth NPN transistor Q 10 The base and collector of the O1 .

[0017] As an optional implementation, the first resistor R 1 and the second resistor R 2 The resistance value is the same; the second PNP transistor Q 2 The third PNP transistor Q 3 Same size; the first PNP transistor Q 1 With the fourth PNP transistor Q 4 Same size; the sixth NPN transistor Q 6 With the seventh NPN transistor Q 7 Same size; the fifth NPN transistor Q 5 With the eighth NPN transistor Q 8 Same size; Ninth NPN transistor Q 9 With the tenth NPN transistor Q 10 The same size; the first current source I 1 With the second current source I 2 The current value of the first PNP transistor Q 1 The second PNP transistor Q 2 The size ratio is 1:1; the fifth NPN transistor Q 5 With the sixth NPN transistor Q 6 The size ratio is 1:1.

[0018] As an optional implementation, when the circuit is in a static state, the third resistor R 3 The current in the first PNP transistor Q 1 、The fifth NPN transistor Q 5 、The sixth NPN transistor Q 6 , the third resistor R 3 And the second PNP transistor Q 2 The ring or the fourth PNP transistor Q 4 、The eighth NPN transistor Q 8 、The seventh NPN transistor Q 7 , the third resistor R 3 And the third PNP transistor Q 3 The loop setting is composed of: when the circuit is in the small signal working state, point G and point H are approximately virtual short, and the third resistor R 3 A smaller small signal current flows through it; when the circuit is in a large signal working state, the first input terminal IN 1 Signal and the second input terminal IN 2 Most of the signal difference falls on the third resistor R3 During the large signal conversion period, the third resistor R 3 The current is larger than that in static state, thus enhancing the slew rate; the fourth resistor R 4 Its function is to limit the maximum current flowing through the third resistor.

[0019] When the circuit is in static state, the Q 1 , Q 2 , R 3 , Q 6 and Q 5 The KVL equations that make up the loop, VBEQ1+VEBQ5BEQ+IR3R3+VEBQ20(1)

[0020] The solution is to flow through R 3 The quiescent current is:

[0021] When the circuit is in a large signal working state, for example, at the first input terminal IN 1 Apply a rising step signal Vi n / 2, at the second input IN 2 Apply a decreasing step signal -Vi n / 2, the applied signal makes Q 2 Deadline, Q 1 Not yet expired, IN 1 with IN 2 The voltage difference between the two ends is

[0022] It can be solved that during the large signal conversion period, the current flowing through R 3 The current is:

[0023] Comparing equation (2) with equation (4), we can see that under the large signal working state, the current flowing through R 3 The current is significantly greater than the current under static operation, that is, the current charging and discharging the capacitor during the conversion period increases, thereby enhancing the slew rate.

[0024] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An adaptive slew rate enhanced input stage circuit, characterized in that: The adaptive slew rate enhancement input stage circuit includes a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a fifth NPN transistor, a sixth NPN transistor, a seventh NPN transistor, an eighth NPN transistor, a ninth NPN transistor, a tenth NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first current source, a second current source, a first input terminal IN1, a second input terminal, a first output terminal, a second output terminal, a positive power supply and a negative power supply, wherein: The emitter of the first PNP transistor is connected to the emitter of the fifth NPN transistor; the base of the first PNP transistor and the base of the second PNP transistor are both connected to the first input terminal; the collector of the first PNP transistor, the emitter of the ninth NPN transistor, the emitter of the tenth NPN transistor and the collector of the fourth PNP transistor are all connected to the negative power supply; the base and collector of the fifth NPN transistor, the base of the sixth NPN transistor and the left end of the fourth resistor are all connected to the lower end of the first current source; the upper end of the first current source, the upper end of the first resistor, the upper end of the second resistor and the upper end of the second current source are all connected to the positive power supply; the collector of the sixth NPN transistor is connected to the lower end of the first resistor; the emitter of the sixth NPN transistor is connected to the seventh NPN transistor; The emitters of the transistors are connected to the upper end of the third resistor; the emitters of the second PNP transistor and the emitters of the third PNP transistor are connected to the lower end of the third resistor; the collector of the second PNP transistor, the base and the collector of the ninth NPN transistor are connected to the second output terminal; the collector of the seventh NPN transistor is connected to the lower end of the second resistor; the base of the seventh NPN transistor, the base and the collector of the eighth NPN transistor, and the right end of the fourth resistor are connected to the lower end of the second current source; the emitter of the eighth NPN transistor is connected to the emitter of the fourth PNP transistor; the base of the fourth PNP transistor and the base of the third PNP transistor are connected to the second input terminal; the collector of the third PNP transistor and the base and the collector of the tenth NPN transistor are connected to the first output terminal.

2. The adaptive slew rate enhanced input stage circuit according to claim 1, characterized in that: The first resistor and the second resistor have the same resistance value; the second PNP transistor and the third PNP transistor have the same size; the first PNP transistor and the fourth PNP transistor have the same size; the sixth NPN transistor and the seventh NPN transistor have the same size; the fifth NPN transistor and the eighth NPN transistor have the same size; the ninth NPN transistor and the tenth NPN transistor have the same size; the current value of the first current source is equal to that of the second current source; the size ratio of the first PNP transistor and the second PNP transistor is m:1; the size ratio of the fifth NPN transistor and the sixth NPN transistor is n:

1.

3. The adaptive slew rate enhanced input stage circuit according to claim 1, characterized in that: When the circuit is in a static state, the current in the third resistor is set by a loop consisting of the first PNP transistor, the fifth NPN transistor, the sixth NPN transistor, the third resistor and the second PNP transistor or a loop consisting of the fourth PNP transistor, the eighth NPN transistor, the seventh NPN transistor, the third resistor and the third PNP transistor; when the circuit is in a small signal working state, point G and point H are approximately virtually shorted, and a smaller small signal current flows through the third resistor; when the circuit is in a large signal working state, most of the difference between the first input terminal signal and the second input terminal signal falls on the third resistor, that is, the current flowing through the third resistor during the large signal conversion period is larger than that in the static state, thereby enhancing the slew rate; the function of the fourth resistor is to limit the maximum current flowing through the third resistor.

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