Final polishing method for wafer and polished wafer

Abstract

The invention relates to a final polishing method for a wafer and a polished wafer. In the final polishing method for the wafer, the wafer comprises a first to-be-removed layer and a second to-be-removed layer, the first to-be-removed layer and the second to-be-removed layer are adjacent to each other and are made of different materials, and the final polishing method comprises the following steps: performing first polishing on the wafer to remove a part of the first to-be-removed layer; and performing second polishing on the wafer after the first polishing to remove the remaining part of the first to-be-removed layer and the second to-be-removed layer, the material removal rate of the second polishing being smaller than the material removal rate of the first polishing. By means of the final polishing method for the wafer, flatness deterioration of the wafer in the final polishing process stage can be avoided or relieved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a final polishing method for a wafer and a polished wafer. Background Art

[0002] As a common technology in the semiconductor wafer manufacturing process, the back-sealing process mainly uses the vapor deposition method to form a back-sealing film, such as a polysilicon film, on the back of the wafer to improve the quality of the wafer. The back-sealing process is particularly suitable for heavily doped wafers. The polysilicon film has good impurity absorption ability and can effectively prevent the dopant from diffusing outward. When the back-sealing process is actually carried out, some equipment may not be able to ensure that a film is formed only on the back of the wafer due to design or technical limitations, but may also form a film on the front of the wafer.

[0003] The final polishing of the wafer is a key process stage in the wafer surface treatment. Its purpose is to remove the damage layer and surface unevenness on the front of the wafer introduced by the previous processing technology to ensure that the wafer surface reaches the required smoothness and flatness. With the development of semiconductor technology, the diameter of the wafer continues to increase. In order to meet the needs of higher performance device manufacturing, the final polishing process of the wafer needs to meet more stringent flatness standards.

[0004] For wafers that have formed a thin film layer on the front damaged layer due to the back-sealing process, when the wafer is subjected to the final polishing process, the thin film layer outside the damaged layer needs to be removed before removing the damaged layer. In this case, the conventional polishing process for directly removing the damaged layer has poor controllability for the surface morphology of such wafers, resulting in a tendency for the flatness of the wafer to deteriorate during the final polishing process, especially causing the nanotopography of the wafer to deteriorate. Summary of the invention

[0005] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0006] An object of the present disclosure is to provide a final polishing method for a wafer, which can avoid or reduce the flatness degradation of the wafer in the final polishing process stage.

[0007] In order to achieve the above object, according to a first aspect of the present disclosure, a final polishing method for a wafer is provided, wherein the wafer comprises a first layer to be removed and a second layer to be removed, the first layer to be removed and the second layer to be removed are adjacent to each other and made of different materials, and the final polishing method for the wafer comprises: performing a first polishing on the wafer to remove a portion of the first layer to be removed; and The wafer that has undergone the first polishing is subjected to a second polishing to remove a remaining portion of the first layer to be removed and a second layer to be removed, wherein a material removal rate of the second polishing is lower than a material removal rate of the first polishing.

[0008] In some embodiments, the final polishing method for the wafer may further include performing a third polishing on the wafer that has undergone the second polishing, wherein a material removal rate of the third polishing is lower than a material removal rate of the second polishing.

[0009] In some embodiments, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the second target removal thickness may be greater than the third target removal thickness.

[0010] In some embodiments, a ratio of the single crystal silicon removal thickness in the second target removal thickness to the third target removal thickness may be 6:1 to 4:1.

[0011] In some embodiments, the sum of the single crystal silicon removal thickness and the third target removal thickness in the second target removal thickness may be greater than or equal to 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

[0012] In some embodiments, the first polishing may use a first polishing solution containing an alkaline additive, and the second polishing may use a second polishing solution containing an alkaline additive. The addition ratio of the alkaline additive in the second polishing solution may be smaller than that in the first polishing solution.

[0013] In some embodiments, the first polishing may use a first polishing liquid containing an alkaline additive, the second polishing may use a second polishing liquid containing an alkaline additive, and the third polishing may use a third polishing liquid not containing an alkaline additive, wherein the addition ratio of the alkaline additive in the second polishing liquid may be smaller than the addition ratio of the alkaline additive in the first polishing liquid.

[0014] In some embodiments, the thickness of the portion of the first layer to be removed may be 85% to 95% of the total thickness of the first layer to be removed.

[0015] In some embodiments, the material of the first layer to be removed may be polycrystalline silicon, and the material of the second layer to be removed may be single crystal silicon.

[0016] According to a second aspect of the present disclosure, a polished wafer is provided. The polished wafer is obtained using the final polishing method for a wafer according to the first aspect of the present disclosure, and Nano 2mm×2mm of the polished wafer is less than 15nm.

[0017] According to the above technical solution, for a wafer having a first layer to be removed and a second layer to be removed which are adjacent to each other and have different materials, two polishing steps with different intensity levels are successively implemented for the first layer to be removed. Specifically, by switching to the second polishing step with a lower material removal rate before the first polishing step with a higher material removal rate is implemented to the interface between the first layer to be removed and the second layer to be removed of the wafer, the remaining portion of the first layer to be removed including the interface can be removed in a relatively gentler manner, thereby avoiding or reducing the deterioration of the flatness of the wafer in the final polishing process stage, so that the polished wafer obtained after the final polishing has good surface flatness, for example, good nanomorphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The features and advantages of the embodiments of the present disclosure will become more easily understood through the following description with reference to the accompanying drawings. The drawings are not drawn to scale and some features may be enlarged or reduced to show details of specific components. In the drawings: Figure 1 is a flow chart of a final polishing method for a wafer according to an embodiment of the present disclosure.

[0019] Figure 2 It is a schematic structural diagram of the final polishing equipment according to an embodiment of the present disclosure.

[0020] Figure 3 is a schematic diagram of a wafer to be final-polished using a final-polishing method for a wafer according to an embodiment of the present disclosure.

[0021] Figure 4 The test results of nanotopography values ​​obtained by taking different removal thickness percentages in the first polishing using the final polishing method for wafers according to an embodiment of the present disclosure within a size of 2 mm×2 mm are shown.

[0022] Figure 5 Shows Figure 4 The test results of the nano-topography value of the polished wafer within the size of 2mm×2mm obtained by taking 85% to 95% of the removal thickness percentage in the first polishing.

[0023] In the drawings, the same or corresponding technical features or components are represented by the same or corresponding reference numerals. DETAILED DESCRIPTION

[0024] The present disclosure is described in detail below with reference to the accompanying drawings by means of exemplary embodiments. It should be noted that the following detailed description of the present disclosure is only for illustrative purposes and is by no means a limitation of the present disclosure.

[0025] Before the final polishing process stage, the wafer is generally obtained through the following process: First, a single crystal silicon rod is pulled out using a crystal pulling furnace using the CZ pulling method. Then, the single crystal silicon rod is cut into multiple single crystal silicon rod segments. Subsequently, each single crystal silicon rod segment is cut into thin wafers, for example, by multi-wire cutting. After that, the wafer is subjected to other processing techniques such as edge polishing, double-sided grinding, and back sealing as needed. These process treatments may introduce damage to the surface of the wafer, such as mechanical damage such as micro scratches or cracks introduced by double-sided grinding. In this regard, the final polishing is usually used to remove the surface damage layer of the wafer to achieve the desired wafer surface quality.

[0026] When the wafer to be final polished is a wafer that has not undergone the back-sealing process, the surface material layer of the wafer to be removed by the final polishing is only the previous process damage layer of the single-crystalline silicon material. When the wafer to be final polished is a wafer that has undergone the back-sealing process, as mentioned above, after the back-sealing process, the wafer not only forms a back-sealing film on its back side, but also may form a thin film on its front side. In this case, the surface material layer to be removed by the final polishing includes not only the previous process damage layer of the single-crystalline silicon material, but may also include a thin film layer covering the previous process damage layer, such as a polysilicon thin film layer.

[0027] In the case of wafers that have a thin film layer formed on the damaged layer on the front side due to the back-sealing process, the conventional final polishing process for directly removing the damaged layer has a poor control effect on the surface morphology of such wafers. Specifically, on the one hand, the formation of a thin film layer covering the damaged layer of the previous process increases the amount of material to be removed, resulting in a tendency for the wafer surface flatness to deteriorate during the final polishing. On the other hand, for example, there are differences in crystal structure and physical properties between single crystal silicon grown by the CZ pulling method and polycrystalline silicon layers grown by chemical vapor deposition. Therefore, the conventional final polishing process menu commonly used, such as for non-back-sealed wafers, is not suitable for the final polishing of such wafers, and may increase the tendency for the wafer surface flatness to deteriorate, especially the deterioration of the nano-morphology.

[0028] To solve the above problems, refer to Figure 1 According to an embodiment of the present disclosure, a final polishing method for a wafer is provided, wherein the wafer comprises a first layer to be removed and a second layer to be removed, the first layer to be removed and the second layer to be removed are adjacent to each other and are made of different materials, and the final polishing method comprises: S100: performing a first polishing on the wafer to remove a portion of a first layer to be removed; and S200: performing a second polishing on the wafer after the first polishing to remove the remaining portion of the first layer to be removed and the second layer to be removed, The material removal rate of the second polishing is lower than that of the first polishing.

[0029] It should be understood that the final polishing referred to in the present disclosure refers to the single-sided final polishing of the front side of the wafer, rather than double-sided grinding or double-sided polishing of the wafer, nor is it local polishing of the wafer such as edge polishing.

[0030] In order to facilitate the understanding of the technical solution, Figure 2 The final polishing device 1 is shown as an example. Figure 2 As shown, the final polishing device 1 includes a polishing head 2, a polishing table 3 and a polishing liquid supply line 4. The polishing head 2 includes an adsorption pad 5, which is used to contact the back side of the wafer W to be finally polished and hold the wafer W in an adsorption manner. A polishing pad 6 is provided on the upper surface of the polishing table 3, which is used to contact the front side of the wafer W. The final polishing device 1 also includes a rotary drive 7 for driving the polishing head 2 to rotate and a rotary drive 8 for driving the polishing table 3 to rotate. The polishing liquid supply line 4 is used to provide the polishing liquid to the polishing pad 6, so as to achieve the final polishing of the front side of the wafer W through the relative rotational movement of the polishing head 2 and the polishing table 3 when the polishing pad 6 is in contact with the wafer W.

[0031] Figure 3 The wafer W to be final polished is shown as an example. Figure 3 In FIG. 1 , the front side of the wafer W is shown as the upper surface, and the back side of the wafer W is shown as the lower surface. The wafer W includes a first layer to be removed L1 and a second layer to be removed L2 on one side of the front side thereof.

[0032] Wafer W is a wafer that has undergone a back coating process before. The back coating process may include a thin film growth process on the back of the wafer, such as a back sealing process. The first layer to be removed L1 is formed when wafer W is subjected to the coating process. For example, wafer W undergoes a back sealing process to form a back film layer L0 on its back and simultaneously forms a first layer to be removed L1 on its front, specifically on the outside of the second layer to be removed L2. It is understandable that the material of the back film layer L0 is the same as that of the first layer to be removed L1. The material of the first layer to be removed L1 is, for example, polysilicon, but is not limited thereto, and may also be, for example, silicon dioxide, silicon nitride, or the like.

[0033] The second layer to be removed L2 is a material layer that already exists on the front side of the wafer W before the back side coating process is performed on the wafer W. This material layer is a surface damage layer caused by the processing process (hereinafter referred to as the preceding process) before the final polishing of the wafer W, specifically before the back side coating process. The second layer to be removed L2 is part of the wafer W itself, and its material is the same as that of the wafer W itself, both of which are single crystal silicon.

[0034] The first layer to be removed L1 and the second layer to be removed L2 are adjacent to each other and form an interface A therebetween. The first layer to be removed L1 is located outside the second layer to be removed L2, and during the final polishing, the first layer to be removed L1 will be polished first, more specifically, the side of the first layer to be removed L1 away from the interface A will be polished first.

[0035] In step S100 (also referred to as the first polishing step), the first polishing is performed on the front surface to be polished of the wafer W to remove a portion of the first layer to be removed L1. That is, the first polishing step is designed not to completely remove the first layer to be removed L1, but to leave a certain thickness near the interface A, so as to ensure that the first polishing is completed before the interface A is touched.

[0036] The material removal rate of the first polishing is relatively large, so as to shorten the time of the first polishing, shorten the overall processing time of the equipment, and improve the equipment's production capacity per unit time.

[0037] In step S200 (also called the second polishing step), the wafer W that has undergone the first polishing is subjected to a second polishing to remove the remaining portion of the first layer to be removed L1 and the second layer to be removed L2 , thereby the interface A will be removed during the second polishing process.

[0038] Compared with the first polishing, the second polishing adopts a lower material removal rate to achieve a gentler polishing process. This not only helps to reduce the damage caused by this process, but also enables the surface material to be removed under relatively milder and more delicate working conditions near the interface A, thereby reducing the flatness deterioration that may be caused when polishing the critical thickness area where the interface A is located.

[0039] Through the above technical solution, for a wafer having a first layer to be removed and a second layer to be removed which are adjacent to each other and have different materials, two polishing steps with different intensity levels are successively implemented for the first layer to be removed. Specifically, by switching to the second polishing step with a lower material removal rate before the first polishing step with a higher material removal rate is implemented at the interface between the first layer to be removed and the second layer to be removed of the wafer, the remaining portion of the first layer to be removed including the interface can be removed in a relatively gentler manner.

[0040] Compared with the situation where the entire first layer to be removed is removed in one step at a higher polishing rate, the final polishing method for wafers disclosed in the present invention can avoid or reduce the deterioration of the flatness of the wafer in the final polishing process stage, and achieves effective control of possible deterioration of the wafer flatness (especially deterioration of nanomorphology), so that the polished wafer obtained after the final polishing has better surface flatness, for example, better nanomorphology.

[0041] In the present disclosure, the numerical results of the nanotopography value within the size of 2mm×2mm are used to evaluate the flatness level of the wafer, referred to as Nano 2mm×2mm. Specifically, after the wafer surface is divided into analysis areas according to a set size (for example, 2mm×2mm), the peak and valley values ​​in the filtered measurement data at each sampling point in each analysis area are arranged in ascending order, and the value of the corresponding position in the ascending order is selected according to the set percentile (for example, 99.5%) as the nanotopography value of the wafer. It can be understood that the smaller the Nano 2mm×2mm, the better the nanotopography of the wafer and the better the flatness of the wafer.

[0042] In some embodiments, the final polishing method for a wafer may further include step S300: performing a third polishing on the wafer W that has undergone the second polishing. The third polishing is used to repair damage caused by the previous polishing steps, especially the second polishing, to obtain a highly flat and smooth surface, and to achieve mirroring of the wafer surface.

[0043] The material removal rate of the third polishing is lower than that of the second polishing, so as to provide milder operating conditions than those of the second polishing, thereby avoiding an overly rough polishing effect caused by an excessively fast material removal rate, and facilitating a finer surface treatment than the second polishing, thereby further improving the nano-morphology characteristics of the wafer surface.

[0044] For example, for a wafer in which the thickness of the previous process damage layer is 200nm and the thickness of the polycrystalline silicon thin film layer covering the previous process damage layer is 400nm, when the processing time of the first polishing, the second polishing and the third polishing are all 400s, and the removal thickness of the single crystal silicon in the second polishing and the third polishing is 150% of the thickness of the previous process damage layer, the material removal rate of the first polishing can be 0.8nm / s to 1.1nm / s, the material removal rate of the second polishing can be 0.5nm / s to 0.8nm / s, and the material removal rate of the third polishing can be 0.08nm / s to 0.2nm / s.

[0045] In some embodiments, the thickness of the portion of the first layer to be removed may be 85% to 95% of the total thickness of the first layer to be removed.

[0046] As mentioned above, using a second polishing with a relatively low material removal rate to remove the thickness region including the interface can help improve the flatness level. In this case, the thickness of the portion of the first layer to be removed removed by the first polishing can be made as close as possible to the total thickness of the first layer to be removed, thereby shortening the processing time of the second polishing with a relatively low material removal rate as much as possible, and thereby improving the overall efficiency of the final polishing process.

[0047] However, if the thickness of the portion removed by the first polishing accounts for more than 95% of the total thickness of the first layer to be removed, the position where the first polishing ends or the second polishing begins will be too close to the interface, which may easily lead to deterioration of flatness, especially deterioration of nano-morphology.

[0048] Depend on Figure 4 and Figure 5 It can be seen from the test results that when the percentage is greater than 95%, the nanomorphology value of the polished wafer obtained is higher overall and tends to increase compared to the range of 65% to 95%, which means that the flatness level of the polished wafer is relatively worse and tends to gradually deteriorate.

[0049] On the other hand, due to the limitation of equipment accuracy, the redundancy of this percentage is set to a minimum of 85% (i.e., greater than or equal to 85%), so that even if the percentage does not reach 95% due to equipment accuracy, as long as it is above 85%, it can ensure the removal efficiency without deteriorating the nanomorphology when the material removal rate of the first polishing is between 0.8nm / s and 1.1nm / s, the material removal rate of the second polishing is between 0.5nm / s and 0.8nm / s, and the material removal rate of the third polishing is between 0.08nm / s and 0.2nm / s.

[0050] The thickness of the first layer to be removed may be, for example, 2000 Å to 10000 Å. However, it is understood that this thickness range is only exemplary, and the thickness of the first layer to be removed will be determined according to the needs of the desired wafer product.

[0051] In some embodiments, the first polishing may be performed with a first target removal thickness. The first target removal thickness may be predetermined according to the needs or specifications of a back-end customer.

[0052] In some embodiments, the second polishing may be performed at a second target removal thickness, and the third polishing may be performed at a third target removal thickness, wherein the second target removal thickness may be greater than the third target removal thickness.

[0053] In this case, the second polishing and the third polishing can remove the wafer surface material in a manner of gradually decreasing the target workload. In this way, the target workloads of the second polishing and the third polishing can be adapted to the magnitude of their respective material removal rates, for example, a relatively large material removal rate is matched with a relatively large target removal thickness, thereby optimizing the entire final polishing process and improving the overall efficiency of the final polishing process.

[0054] In some embodiments, a ratio of the single crystal silicon removal thickness in the second target removal thickness to the third target removal thickness may be 6:1 to 4:1.

[0055] As mentioned before, the portion removed by the second polishing includes the remaining portion of the first layer to be removed and the second layer to be removed. That is, the material removed by the second polishing includes the thin film material corresponding to the remaining portion (e.g., polycrystalline silicon) and the material corresponding to the second layer to be removed (i.e., single crystal silicon). In this case, in fact, the second target removal thickness is composed of the thin film material removal thickness and the single crystal silicon removal thickness.

[0056] By making the ratio of the single crystal silicon removal thickness in the second target removal thickness to the third target removal thickness reach 6:1 to 4:1, it is possible to make the removal of the damaged layer more thorough while ensuring that no excessive loss of single crystal silicon material is achieved.

[0057] In some embodiments, the sum of the single crystal silicon removal thickness in the second target removal thickness and the third target removal thickness may be greater than or equal to 150% of the thickness of the damaged layer of the wafer to be first polished. In this way, sufficient removal of the damage in the previous process can be ensured to the greatest extent.

[0058] It should be noted that the damaged layer here refers to the damaged layer that already exists on the surface to be polished of the wafer when the wafer is to be final polished or when the first polish is about to be performed. The damaged layer is the area where the damage introduced on the wafer surface due to the previous process before the first polish is located.

[0059] It is understood that the thickness of the damaged layer refers to the depth of the damage relative to the surface of the wafer in a direction perpendicular to the surface. The thickness of the damaged layer may be, for example, 50 nm to 1000 nm. However, it is understood that this thickness range is only exemplary, and the thickness of the damaged layer may vary depending on the damage situation.

[0060] It is conceivable that the material removal rate of the first polishing, the material removal rate of the second polishing and / or the material removal rate of the third polishing can be configured by adjusting the polishing process parameters. The aforementioned polishing process parameters include but are not limited to: the composition of the polishing liquid, the operating pressure, the rotation speed, etc.

[0061] Exemplarily, the components of the polishing liquid include an alkaline additive. In some embodiments, the first polishing may use a first polishing liquid containing an alkaline additive, and the second polishing may use a second polishing liquid containing an alkaline additive. The addition ratio of the alkaline additive in the second polishing liquid may be less than the addition ratio of the alkaline additive in the first polishing liquid, so that the alkaline concentration of the second polishing liquid is lower than the alkaline concentration of the first polishing liquid. Thus, the chemical corrosion effect of the second polishing is weaker than the chemical corrosion effect of the first polishing, so that the material removal rate of the second polishing is lower than the material removal rate of the first polishing.

[0062] In an embodiment including the third polishing, the first polishing may use a first polishing liquid containing an alkaline additive, the second polishing may use a second polishing liquid containing an alkaline additive, and the addition ratio of the alkaline additive in the second polishing liquid may be smaller than the addition ratio of the alkaline additive in the first polishing liquid. The third polishing may use a third polishing liquid that does not contain an alkaline additive, so that the material removal rate of the third polishing is smaller than the material removal rate of the second polishing.

[0063] By using the third polishing liquid without the alkaline additive, it is possible to avoid the deterioration of the flatness of the wafer surface which may be caused by chemical corrosion during the third polishing.

[0064] Exemplarily, the alkaline additive may be an organic base or an inorganic base. For example, the alkaline additive may include KOH, NaOH or NH4OH, etc.

[0065] In addition, the components of the above-mentioned polishing liquid also include abrasive particles, which are used to remove surface materials by physically grinding the surface of the wafer. The material removal rate can also be configured by the particle size and uniformity of the abrasive particles in the polishing liquid. For example, compared with the second polishing, the third polishing can use abrasive particles with a smaller particle size and more uniformity to achieve the mirror surface of the wafer to a greater extent.

[0066] In addition, the operating pressure and rotation speed used in the first polishing may be greater than those used in the second polishing. When the third polishing is included, the operating pressure and rotation speed used in the second polishing may be greater than those used in the third polishing.

[0067] Combination Figure 2 It is understood that the operating pressure refers to the pressure applied to the wafer W being polished, for example, the pressure applied by the polishing head 2. The rotation speed refers to the rotation speed of the polishing head 2, that is, the rotation speed of the wafer W, the rotation speed of the polishing table 3, that is, the rotation speed of the polishing pad 6, or the relative rotation speed of the wafer W and the polishing pad 6.

[0068] It is understandable that the aforementioned polishing process parameters can be configured through reasonable matching and adjustment to obtain the material removal rate required for each polishing step, thereby achieving fine control over the entire final polishing process.

[0069] According to an embodiment of the present disclosure, a polished wafer is also provided. The polished wafer is obtained using the final polishing method for a wafer according to an embodiment of the present disclosure, and Nano 2mm×2mm of the polished wafer is less than 15nm.

[0070] Reference Figure 4 and Figure 5, the Nano 2mm×2mm of the polished wafer obtained by the final polishing method for the wafer according to the embodiment of the present disclosure is less than 15nm. Specifically, when the thickness of the portion of the first layer to be removed is 85% to 95% of the total thickness of the first layer to be removed, the Nano 2mm×2mm is specifically less than 10nm.

[0071] This indicates that the polished wafer obtained by the final polishing method for the wafer according to the embodiment of the present disclosure can obtain a better nano-morphology, that is, the polished wafer has a better flatness characteristic.

[0072] Unless otherwise defined, technical or scientific terms used in the present disclosure shall have the common meanings understood by those skilled in the art to which the present disclosure belongs. The terms "include" and "comprising" are open ended, i.e., systems, devices, articles, compositions, preparations or methods that include elements other than those listed after such terms in a claim are still considered to fall within the scope of the claim.

[0073] Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that the present disclosure is not limited to the specific embodiments described and shown in detail herein. Various changes may be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of the present disclosure.

[0074] The features mentioned and / or shown in the above description of the exemplary embodiments of the present disclosure may be combined in the same or similar manner into one or more other embodiments, combined with features in other embodiments or substituted for corresponding features in other embodiments. The technical solutions obtained by these combinations or substitutions shall also be deemed to be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A final polishing method for a wafer, wherein the wafer comprises a first layer to be removed and a second layer to be removed, wherein the first layer to be removed and the second layer to be removed are adjacent to each other and are made of different materials, wherein: The final polishing method comprises: performing a first polishing on the wafer to remove a portion of the first layer to be removed; and A second polishing is performed on the wafer after the first polishing to remove the remaining portion of the first layer to be removed and the second layer to be removed, wherein a material removal rate of the second polishing is lower than a material removal rate of the first polishing.

2. The final polishing method for a wafer according to claim 1, characterized in that: The method also includes performing a third polishing on the wafer after the second polishing, wherein a material removal rate of the third polishing is lower than a material removal rate of the second polishing.

3. The final polishing method for a wafer according to claim 2, characterized in that: The second polishing is performed at a second target removal thickness, and the third polishing is performed at a third target removal thickness, wherein the second target removal thickness is greater than the third target removal thickness.

4. The final polishing method for a wafer according to claim 3, characterized in that: A ratio of a single crystal silicon removal thickness in the second target removal thickness to the third target removal thickness is 6:1 to 4:

1.

5. The final polishing method for wafers according to claim 3 or 4, characterized in that: The sum of the single crystal silicon removal thickness in the second target removal thickness and the third target removal thickness is greater than or equal to 150% of the thickness of the damaged layer of the wafer to be subjected to the first polishing.

6. The final polishing method for a wafer according to claim 1, characterized in that: The first polishing uses a first polishing liquid containing an alkaline additive, and the second polishing uses a second polishing liquid containing an alkaline additive. The addition ratio of the alkaline additive in the second polishing liquid is smaller than the addition ratio of the alkaline additive in the first polishing liquid.

7. The final polishing method for a wafer according to claim 2, characterized in that: The first polishing uses a first polishing liquid containing an alkaline additive, the second polishing uses a second polishing liquid containing an alkaline additive, and the third polishing uses a third polishing liquid without an alkaline additive, wherein the addition ratio of the alkaline additive in the second polishing liquid is smaller than the addition ratio of the alkaline additive in the first polishing liquid.

8. The final polishing method for a wafer according to claim 1, characterized in that: The thickness of the portion of the first layer to be removed is 85% to 95% of the total thickness of the first layer to be removed.

9. The final polishing method for a wafer according to claim 1, characterized in that: The material of the first layer to be removed is polycrystalline silicon, and the material of the second layer to be removed is single crystal silicon.

10. A polished wafer, characterized in that: The polished wafer is obtained using the final polishing method for wafers according to any one of claims 1 to 9, and Nano 2mm×2mm of the polished wafer is smaller than 15nm.

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