Preparation method of semiconductor structure and semiconductor structure
The described method addresses the challenge of reducing line width in semiconductor fabrication by using a sequence of silicon-based layer deposition and etching processes, enabling precise control over pattern formation and increasing device density in semiconductor structures.
Patent Information
- Application Number
- CN202411741193.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-03-14
AI Technical Summary
Current multi-patterned semiconductor fabrication techniques face challenges in further reducing line width, leading to lower device density due to limitations in pattern formation.
A method involving a sequence of silicon-based layer deposition and etching processes, including forming a target layer with alternating silicon oxide and polysilicon layers, followed by multiple etching steps to create and refine patterns on the substrate, allowing for precise control of sidewall formation and gap sizes between polysilicon layers, ultimately enabling the reduction of line width and increasing device density.
This method allows for the further miniaturization of semiconductor structures, enhancing device density by precisely controlling the dimensions and spacing of features within the semiconductor structure.
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Figure CN119626900A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] In the process of manufacturing semiconductor structures, it is often necessary to form certain patterns, for example, etching trenches in a substrate to define active areas. As the size of patterns shrinks, multiple patterning processes are usually used to form the above patterns.
[0003] However, it is difficult to further reduce the line width of the pattern in the existing multiple patterning process, resulting in a low device density of the semiconductor structure. Summary of the invention
[0004] The embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure.
[0005] A first aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:
[0006] Providing a substrate, and sequentially forming a target layer to be etched and a first patterned layer on the substrate, wherein the target layer to be etched comprises a first silicide layer, a first polysilicon layer, and a second silicide layer stacked in sequence, and the first patterned layer comprises a plurality of first patterns;
[0007] Using the first patterned layer as a mask, etching the target layer to be etched to pattern the target layer to be etched to obtain a second patterned layer, wherein the second patterned layer includes a plurality of second patterns;
[0008] forming sidewalls and a second polysilicon layer, wherein the sidewalls cover the sidewalls of each of the second patterns, and the second polysilicon layer fills the gaps between the sidewalls;
[0009] removing the film layer structure above the first polysilicon layer to expose the first polysilicon layer;
[0010] The sidewalls between the first polysilicon layer and the second polysilicon layer are removed, and the substrate is etched using the etched first polysilicon layer and the second polysilicon layer as masks to obtain the semiconductor structure.
[0011] In some possible examples, forming the spacer and the second polysilicon layer further includes:
[0012] Depositing a third silicide layer, wherein the third silicide layer covers the sidewalls and top wall of the second pattern and the area exposed by the second pattern, and the second silicide layer located on the sidewalls of the second pattern forms the sidewall;
[0013] Depositing a second polysilicon layer, wherein the second polysilicon layer is filled between the sidewalls, and a top surface of the second polysilicon layer is higher than a top surface of the third silicide layer or is flush with a top surface of the third silicide layer;
[0014] The film layer structure includes the first silicide layer and the third silicide layer located above the first polysilicon layer.
[0015] In some possible examples, an etching process is used to remove the film layer structure, and the etching process has the same etching rate for the second polysilicon layer, the second silicide, and the sidewall.
[0016] In some possible examples, removing the film layer structure located above the first polysilicon layer further includes:
[0017] Removing the second polysilicon layer above the third silicide layer by a first etching process;
[0018] A second etching process is used to remove the second silicide layer, the third silicide layer on the side and top surface of the second silicide layer, and a portion of the second polysilicon layer until the top surface of the remaining second polysilicon layer is flush with the top surface of the first polysilicon layer.
[0019] In some possible examples, the second etching process has the same etching rate on the second polysilicon layer, the second silicide layer, and the third silicide layer.
[0020] In some possible examples, a thickness of the third silicide layer located in a region exposed by the second pattern is the same as a thickness of the first silicide layer.
[0021] In some possible examples, the first silicide layer and the second silicide layer are made of the same material, wherein the material of the first silicide layer includes silicon oxide or silicon nitride.
[0022] In some possible examples, the third silicide layer is made of the same material as the first silicide layer and the second silicide layer, and the material of the third silicide layer includes silicon oxide or silicon nitride.
[0023] In some possible examples, a width of the second pattern is the same as a width of a gap between the sidewalls.
[0024] In some possible examples, an advanced pattern film layer is further formed between the substrate and the target layer to be etched, and etching the substrate to obtain the semiconductor structure further includes:
[0025] Using the remaining first polysilicon layer and the second polysilicon layer as masks, etching the advanced pattern film layer;
[0026] removing the first polysilicon layer, the first silicide layer, the second polysilicon layer and the third silicide layer located on the advanced pattern film layer, and etching the substrate using the etched advanced pattern film layer as a mask;
[0027] The advanced graphic film layer is removed to obtain the semiconductor structure.
[0028] A second aspect of an embodiment of the present disclosure provides a semiconductor structure, which is prepared by the preparation method described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0030] Figure 1 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;
[0031] Figure 2 A schematic diagram after forming a first patterned layer according to an embodiment of the present disclosure;
[0032] Figure 3 A schematic diagram after forming a plurality of second patterns according to an embodiment of the present disclosure;
[0033] Figure 4 A schematic diagram of a sidewall after forming the sidewall provided in an embodiment of the present disclosure;
[0034] Figure 5 A schematic diagram after forming a second polysilicon layer provided in an embodiment of the present disclosure;
[0035] Figure 6 Another schematic diagram after forming a second polysilicon layer provided in an embodiment of the present disclosure;
[0036] Figure 7 Another schematic diagram after forming a second polysilicon layer provided in an embodiment of the present disclosure;
[0037] Figure 8 A schematic diagram after performing a first etching process according to an embodiment of the present disclosure;
[0038] Fig. 9 A schematic diagram after performing a second etching process provided in an embodiment of the present disclosure;
[0039] Fig.10A schematic diagram of an embodiment of the present disclosure after a portion of the side wall is removed;
[0040] Fig.11 A schematic diagram of an embodiment of the present disclosure after a portion of the advanced graphic film layer is removed;
[0041] Fig.12 A schematic diagram of removing a film layer above an advanced graphic film layer provided in an embodiment of the present disclosure;
[0042] Fig.13 This is a schematic diagram of an embodiment of the present disclosure after removing the advanced graphic film layer.
[0043] Reference numerals:
[0044] 10-substrate;
[0045] 20-target layer to be etched;
[0046] 21- a first silicide layer;
[0047] 22-a first polysilicon layer;
[0048] 23- a second silicide layer;
[0049] 24-second groove;
[0050] 30-first patterned layer;
[0051] 31- first groove;
[0052] 40- a third silicide layer;
[0053] 41-third groove;
[0054] 50-a second polysilicon layer;
[0055] 60-Advanced Graphics Coating. DETAILED DESCRIPTION
[0056] The disclosed embodiment provides a method for preparing a semiconductor structure, wherein a target layer to be etched and a first patterned layer having a plurality of first patterns are sequentially formed on a substrate, and the target layer to be etched is etched using the first patterned layer as a mask, thereby obtaining a second patterned layer having a plurality of second patterns, wherein the target layer to be etched includes a first silicide layer, a first polysilicon layer, and a second silicide layer stacked in sequence. After forming a sidewall covering the sidewalls of each second pattern and a second polysilicon layer filled between the sidewalls, the film layer structure above the first polysilicon layer and the sidewall between the first polysilicon layer and the second polysilicon layer are removed, so that the remaining first polysilicon layer and the second polysilicon layer are spaced apart. By controlling the formation parameters of the sidewall, the size of the gap between the adjacent first polysilicon layer and the second polysilicon layer can be controlled, so that the gap between the first polysilicon layer and the second polysilicon layer can be further reduced. In this way, after the substrate is etched using the etched first polysilicon layer and the second polysilicon layer as a mask to obtain the semiconductor structure, the line width of the semiconductor structure can be further reduced, thereby improving the device density of the semiconductor structure.
[0057] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.
[0058] See also Figure 1 The present disclosure provides a method for preparing a semiconductor structure, the method comprising the following steps:
[0059] Step S100: providing a substrate, and sequentially forming a target layer to be etched and a first patterned layer on the substrate, wherein the target layer to be etched comprises a first silicide layer, a first polysilicon layer, and a second silicide layer stacked in sequence, and the first patterned layer comprises a plurality of first patterns.
[0060] See also Figure 2 The substrate 10 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate.
[0061] The target layer to be etched 20 is formed on the substrate 10, and the target layer to be etched 20 includes a first silicide layer 21, a first polysilicon layer 22, and a second silicide layer 23 which are stacked in sequence, wherein the first silicide layer 21 is located on a side adjacent to the substrate 10. The first silicide layer 21 and the second silicide layer 23 are made of the same material, and the material of the first silicide layer 21 includes silicon oxide or silicon nitride. In this way, the structure of the target layer to be etched 20 is a sandwich structure, which can facilitate the deposition of the target layer to be etched 20 and facilitate preparation. On the other hand, the first silicide layer 21 and the second silicide layer 23 can block the invasion of oxygen and prevent the first polysilicon layer 22 from being oxidized.
[0062] In some possible examples, the first silicide layer 21 and the second silicide layer 23 are made of the same material, and both are silicon oxide, that is, the target layer to be etched 20 is a sandwich structure of silicon oxide-polysilicon-silicon oxide. In other possible examples, the first silicide layer 21 and the second silicide layer 23 are made of the same material, and both are silicon nitride, that is, the target layer to be etched 20 is a sandwich structure of silicon nitride-polysilicon-silicon nitride.
[0063] The first silicide layer 21, the first polysilicon layer 22 and the second silicide layer 23 may be formed by a deposition process, wherein the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).
[0064] It is understandable that the thickness of each film layer in the target layer to be etched 20 can be selected in a variety of ways, that is, the thickness of the first silicide layer 21, the first polysilicon layer 22, and the second silicide layer 23 can be the same or different. As an example, the thickness of the first polysilicon layer 22 is greater than the thickness of the first silicide layer 21, and greater than the thickness of the second silicide layer 23. The thickness of the first silicide layer 21 and the second silicide layer 23 are the same or different. As another example, the thickness of the first silicide layer 21 is greater than the thickness of the second silicide layer 23, and greater than the thickness of the first polysilicon layer 22; or the thickness of the second silicide layer 23 is greater than the thickness of the first silicide layer 21, and greater than the thickness of the first polysilicon layer 22.
[0065] The first patterned layer 30 is formed on the target layer to be etched, and includes a plurality of first patterns, the plurality of first patterns are arranged at intervals, and a first groove 31 is enclosed between two adjacent first patterns. For example, the plurality of first patterns are arranged at intervals along a first direction, and the first direction is as follows: Figure 1The first patterned layer 30 is used as a mask of the target layer to be etched, and the multiple first patterns thereon are subsequently transferred to the target layer to be etched to achieve patterning of the target layer to be etched.
[0066] Step S200: using the first patterned layer as a mask, etching the target layer to be etched, and patterning the target layer to be etched to obtain a second patterned layer, wherein the second patterned layer includes a plurality of second patterns.
[0067] See also Figure 3 , using the first patterned layer as a mask, etching the target layer 20 to be etched, retaining a portion of the target layer 20 to be etched covered by the multiple first patterns, and removing the target layer 20 to be etched that is not covered by the first patterns. After etching (i.e., after patterning), the target layer 20 to be etched forms a second patterned layer, and the second patterned layer includes a plurality of second patterns, the plurality of second patterns are arranged at intervals, and a second groove 24 is enclosed between two adjacent second patterns. Exemplarily, the plurality of second patterns are arranged at intervals along the first direction, each second pattern is located on a side of the corresponding first pattern close to the substrate 10, the plurality of second patterns correspond to the plurality of first patterns one by one, and the first pattern and the second pattern overlap in their orthographic projections on the substrate 10.
[0068] It can be understood that the plurality of second patterns are all stacked structures, and each second pattern includes a first layer, a second layer, and a third layer stacked in sequence. The first layer is the retained first silicide layer 21, the second layer is the retained first polysilicon layer 22, and the third layer is the retained second silicide layer 23.
[0069] Step S300: forming sidewall spacers and a second polysilicon layer, wherein the sidewall spacers cover the sidewalls of each second pattern, and the second polysilicon layer fills the gaps between the sidewall spacers.
[0070] See also Figures 4 to 7 A sidewall is formed on the sidewall of each second pattern, and a gap 41 is formed between two adjacent sidewalls, and the gap 41 is filled with a second polysilicon layer.
[0071] Specifically, the step of forming the sidewall includes: depositing a third silicide layer 40, the third silicide layer 40 covers the sidewalls and top walls of the second pattern, and the area exposed by the second pattern (i.e., the advanced graphic film layer 60 exposed by the second pattern), and the third silicide layer 40 located on the sidewall of the second pattern forms a sidewall, and there is no need to remove the third silicide layer 40 formed at other positions, which can simplify the preparation process.
[0072] The third silicide layer 40 and the second silicide layer 23 are made of the same material. In this way, the third silicide layer 40 and the second silicide layer 23 can be integrated, and when the film layers above the first polysilicon layer 22 are subsequently removed, the same removal process can be used without changing the process, thereby maintaining the same etching rate of the third silicide layer 40 and the second silicide layer 23, so as to achieve alignment of the top surface of the remaining sidewall with the top surface of the first polysilicon layer 22.
[0073] In some possible examples, when forming the sidewalls, the film layers formed together with the sidewalls at other positions may be removed, and only the sidewalls are retained, and then the second polysilicon layer is filled in the gaps between the sidewalls.
[0074] The second polysilicon layer 50 may fill or not fill the third trench 41. Figure 5 As shown in FIG. 1 , the top surface of the second polysilicon layer 50 is flush with the top surface of the first polysilicon layer 22. Alternatively, as shown in FIG. Figure 6 As shown, the top surface of the second polysilicon layer 50 is higher than the top surface of the first polysilicon layer 22, and even Figure 7 As shown, the second polysilicon layer 50 is higher than the top surface of the second silicide layer 23 , that is, the second polysilicon layer 50 fills the third trench 41 and covers the third silicide layer 40 .
[0075] In the above example, the top surface refers to the surface facing away from the substrate 10. The second polysilicon layer 50 is made of the same material as the first polysilicon layer 22, so that when the second polysilicon layer 50 and the first polysilicon layer 22 are subsequently etched away, the second polysilicon layer 50 and the first polysilicon layer 22 have the same etching rate.
[0076] The third silicide layer 40 is made of the same material as the first silicide layer 21. In this way, the stacked structure formed by the second polysilicon layer 50 and the third silicide layer 40 located at the position of the groove 41 is the same as the stacked structure formed by the first polysilicon layer 22 and the first silicide layer 21, and the second polysilicon layer 50 and the first polysilicon layer 22 can be removed synchronously, and the third silicide layer 40 and the first silicide layer 21 can be removed synchronously.
[0077] In some possible implementations, the third silicide layer 40 is located in the area exposed by the second pattern and has the same thickness as the first silicide layer 21, so that the surface of the second polysilicon layer 50 close to the substrate 10 is flush with the surface of the first polysilicon layer 22 close to the substrate, which facilitates the subsequent acquisition of the first polysilicon layer 22 and the second polysilicon layer 50 of the same height.
[0078] Step S400: removing the film layer structure above the first polysilicon layer to expose the first polysilicon layer.
[0079] See also Figure 8 and Fig. 9, remove the film structure on the side of the first polysilicon layer 22 facing away from the substrate 10, the film structure including the second silicide layer 23 and the third silicide layer located above and on the sidewall of the second silicide layer 23, and remove the film structure until the top surface of the first polysilicon layer 22 is exposed. The film structure above the first polysilicon layer 22 can be removed by etching to expose the first polysilicon layer 22.
[0080] It can be understood that when removing the membrane layer structure above the first polysilicon layer 22, it also includes removing the third silicide layer 40 located above and on the side wall of the second silicide layer 23. The third silicide layer 40 located on the side wall of the second silicide layer 23 is a partial side wall, and the top surface of the remaining side wall is flush with the top surface of the first polysilicon layer 22. At this time, since there is no need to remove the second polysilicon layer 50, a process can be used that has the same etching rate for the second silicide layer 23 and the side wall and does not etch the second polysilicon layer 50. When the top surface of the second polysilicon layer 50 is higher than the top surface of the first polysilicon layer 22, the film layers above the first polysilicon layer 22 are removed, and the second polysilicon layer 50 above the first polysilicon layer 22 is also removed, so that the top surface of the second polysilicon layer 50 is flush with the top surface of the first polysilicon layer 22. Therefore, the second silicide layer 23, the side wall and the second polysilicon layer 50 can be etched using a process with the same etching rate.
[0081] Step S500: removing the sidewall spacer between the first polysilicon layer and the second polysilicon layer.
[0082] See also Fig. 9 and Fig.10 The sidewalls can be removed by etching, and an etching process with a high selectivity between the sidewalls and the first polysilicon layer 22 or the second polysilicon layer 50 can be used to reduce the impact on the first polysilicon layer 22 and the second polysilicon layer 50 during the removal of the sidewalls. After removing the sidewalls, the remaining first polysilicon layers 22 and the second polysilicon layers 50 are alternately arranged in sequence, and there are gaps between adjacent first polysilicon layers 22 and second polysilicon layers 50. The gaps between adjacent first polysilicon layers 22 and second polysilicon layers 50 are the thickness of the sidewalls.
[0083] Step S600: using the etched first polysilicon layer and the second polysilicon layer as masks, etching the substrate to obtain a semiconductor structure.
[0084] See also Figures 11 to 13, using the etched first polysilicon layer 22 and the second polysilicon layer 50 as a mask, the film layer exposed between the first polysilicon layer 22 and the second polysilicon layer 50 is etched away until the substrate 10 is exposed to form a semiconductor structure. By controlling the thickness of the sidewall, the line width of the formed semiconductor structure can be controlled, so that the line width of the semiconductor structure can be further reduced, for example, the line width can be less than 20nm, thereby improving the device density of the semiconductor structure. At the same time, the gap between the first polysilicon layer 22 and the second polysilicon layer 50 can be evenly distributed by controlling the thickness of the sidewall.
[0085] It can be understood that, in the process of etching the substrate 10 using the etched first polysilicon layer 22 and the second polysilicon layer 50 as masks, the first polysilicon layer 22 and the second polysilicon layer 50 will also be simultaneously eliminated, and even the second silicide layer 23 under the first polysilicon layer 22 and the third silicide layer 40 under the second polysilicon layer 50 will be eliminated.
[0086] In some possible examples, an advanced patterning film layer 60 (APF for short) is also formed between the substrate 10 and the target layer to be etched 20, and the substrate 10 is etched using the etched first polysilicon layer 22 and the second polysilicon layer 50 as a mask to obtain a semiconductor structure, including: etching the advanced patterning film layer 60 using the etched first polysilicon layer 22 and the second polysilicon layer 50 as a mask; removing the first polysilicon layer 22, the first silicide layer 21, the second polysilicon layer 50 and the third silicide layer 40 located on the advanced patterning film layer 60, and etching the substrate 10 using the etched advanced patterning film layer 60 as a mask; removing the advanced patterning film layer 60 to obtain a semiconductor structure.
[0087] The material of the advanced pattern film layer 60 may be amorphous carbon, which has a relatively high hardness, so as to ensure the accuracy of the formed third pattern and the subsequent formation of the semiconductor structure. Fig.11 As shown, the advanced pattern film layer 60 exposed between the first polysilicon layer 22 and the second polysilicon layer 50 is etched away using the etched first polysilicon layer 22 and the second polysilicon layer 50 as masks.
[0088] After etching the advanced pattern film layer 60, the first silicide layer 21, the first polysilicon layer 22, the third silicide layer 40, and the second polysilicon layer 50 located on the advanced pattern film layer 60 are removed. For another example, in the process of etching the advanced pattern film layer 60 using the remaining first polysilicon layer 22 and the second polysilicon layer 50 as masks, the first polysilicon layer 22 and the second polysilicon layer 50 are completely consumed, the advanced pattern film layer 60 has the first silicide layer 21 and the third silicide layer 40, and removing the film layer located on the advanced pattern film layer 60 includes removing the first silicide layer 21 and the third silicide layer 40.
[0089] like Fig.12 As shown, the etched advanced pattern film layer 60 is used as a mask to etch the substrate 10, and the pattern is transferred into the substrate 10. The hardness of the advanced pattern film layer 60 is usually relatively large. In the process of etching the substrate 10 using the third pattern as a mask, the advanced pattern film layer 60 usually has a residual, such as Fig.13 As shown, this portion of the advanced pattern film layer 60 is removed to obtain a semiconductor structure.
[0090] In summary, in the method for preparing a semiconductor structure in the embodiment of the present disclosure, a target layer to be etched 20 and a first patterned layer 30 are sequentially formed on a substrate 10, the target layer to be etched 20 includes a first silicide layer 21, a first polysilicon layer 22 and a second silicide layer 23 stacked in sequence, and the first patterned layer 30 includes a plurality of first patterns; the target layer to be etched 20 is etched using the first patterned layer 30 as a mask to obtain a second patterned layer, and the second patterned layer includes a plurality of second patterns. By forming a sidewall and a second polysilicon layer 50, the sidewall covers the sidewalls of each second pattern, the second polysilicon layer 50 fills the gap between the sidewalls, and by removing the film layer structure above the first polysilicon layer 22 and the sidewall between the first polysilicon layer 22 and the second polysilicon layer 50, the remaining first polysilicon layer 22 and the second polysilicon layer 50 are spaced apart. By controlling the formation parameters of the sidewalls, such as the deposition thickness of the sidewalls, the gap between the adjacent first polysilicon layer 22 and the second polysilicon layer 50 can be controlled, so that the gap between the first polysilicon layer 22 and the second polysilicon layer 50 can be further reduced. In this way, after etching the substrate 10 with the remaining first polysilicon layer 22 and the second polysilicon layer 50 as masks to obtain the semiconductor structure, the line width of the semiconductor structure can be further reduced, thereby improving the device density of the semiconductor structure.
[0091] In some possible implementations, forming the sidewall spacer and the second polysilicon layer 50 (step S300) further includes:
[0092] Step S301 : depositing a third silicide layer 40 , wherein the third silicide layer 40 covers the sidewalls and top walls of the second patterns, and the film layer exposed between the first patterns.
[0093] like Figure 4 As shown, the third silicide layer 40 covers the side of the remaining first silicide layer 21, the side of the first polysilicon layer 22, the side and top of the second silicide layer 23, and the area exposed by the second pattern (such as the substrate 10, the advanced graphic film layer 60 or the layer to be patterned), wherein the third silicide layer 40 located on the sidewall of the second pattern is a sidewall. In this way, the third silicide layer 40 covers the second pattern and covers the sidewall and bottom wall of the second trench 24, and the third silicide layer 40 encloses and forms a third trench 41.
[0094] Step S302 : depositing a second polysilicon layer 50 , wherein the second polysilicon layer 50 is filled between the sidewalls, and the top surface of the second polysilicon layer 50 is higher than the top surface of the third silicide layer.
[0095] like Figure 7 As shown, a second polysilicon layer 50 is deposited on the third silicide layer 40 located at the position of the trench 41 , the second polysilicon layer 50 covers the third silicide layer 40 , and the top surface of the second polysilicon layer 50 is higher than the top surface of the third silicide layer 40 .
[0096] Based on the above implementation, the film layer structure above the first polysilicon layer 22 is removed to expose the first polysilicon layer 22 , including: using an etching process to remove the film layer structure above the first polysilicon layer 22 until the first polysilicon layer 22 is exposed.
[0097] The first polysilicon layer 22 is covered with the second silicide layer 23, the second silicide layer 23 is covered with the third silicide layer 40, and the third silicide layer 40 is covered with the second polysilicon layer 50. The film layer structure above the first polysilicon layer 22 includes the second silicide layer 23, the third silicide layer 40, and the second polysilicon layer 50 located above the first polysilicon layer 22.
[0098] In some possible examples, the process parameters of the etching process are reasonably adjusted to achieve the same etching rate of the second polysilicon layer 50, the second silicide layer 23 and the third silicide layer 40, that is, the etching selectivity ratio of the second polysilicon layer 50, the second silicide layer 23 and the third silicide layer 40 is equal to 1:1:1. In this way, the second silicide layer 23, the third silicide layer 40 and the second polysilicon layer 50 can be etched synchronously by the etching process. After removing the second silicide layer 23, the third silicide layer 40 and the second polysilicon layer 50 above the first polysilicon layer 22, the top surface of the remaining sidewall is flush with the top surface of the first polysilicon layer 22 and the top surface of the remaining second polysilicon layer 50, and the etching process is simple without adding additional steps.
[0099] like Figure 8 As shown, the second polysilicon layer 50 is etched by the first etching process, and the second polysilicon layer 50 located above the third silicide layer 40 is exposed to expose the third silicide layer 40, and the top surface of the remaining second polysilicon layer 50 is flush with the top surface of the third silicide layer 40. In this process, the first etching process etches only the second polysilicon layer 50.
[0100] like Fig. 9As shown, the second polysilicon layer 50, the third silicide layer 40 and the second silicide layer 23 are etched by a second etching process to remove the third silicide layer 40, the second silicide layer 23 and the second polysilicon layer 50 above the first polysilicon layer 22. That is, the second silicide layer 23 is removed, and the third silicide layer 40 located on the top surface and the side surface of the second silicide layer 23, and the part of the second polysilicon layer 50 that exceeds the top surface of the first polysilicon layer 22 are removed, until the top surface of the remaining second polysilicon layer 50 is flush with the top surface of the first polysilicon layer 22.
[0101] By reasonably adjusting the process parameters of the second etching process, the second etching process can achieve the same etching rate for the second polysilicon layer 50, the second silicide layer 23 and the third silicide layer 40. That is, in the process of adopting the second etching process, the etching selection ratio of the second etching process for the second polysilicon layer 50, the second silicide and the third silicide layer 40 is equal to 1:1:1, so that the top surface of the remaining second polysilicon layer 50 is flush with the top surface of the first polysilicon layer 22, and the top surface of the remaining sidewall is flush with the first two.
[0102] In some possible examples, a substrate 10 is provided, and a target layer to be etched 20 and a first patterned layer 30 are sequentially formed on the substrate 10, wherein the target layer to be etched 20 includes a first silicide layer 21, a first polysilicon layer 22, and a second silicide layer 23 stacked in sequence, and the first patterned layer 30 includes a plurality of first patterns (step S100), which may specifically include:
[0103] S101: providing a substrate 10.
[0104] S102 : forming a target to-be-etched layer 20 and an initial first patterned layer 30 which are stacked in sequence on the substrate 10 .
[0105] like Figure 2 As shown, a first silicide layer 21, a first polysilicon layer 22, a second silicide layer 23 and an initial first patterned layer 30 are sequentially formed, and the first silicide layer 21, the first polysilicon layer 22, the second silicide layer 23 and the initial first patterned layer 30 are sequentially stacked in a direction away from the substrate 10, and the first silicide layer 21, the first polysilicon layer 22 and the second silicide layer 23 form a target to-be-etched layer 20. The first silicide layer 21, the first polysilicon layer 22 and the second silicide layer 23 may be formed by a deposition process, and the initial first patterned layer 30 may include a photoresist layer, and the photoresist layer may be formed by a spin coating process.
[0106] S103 : patterning the initial first patterned layer 30 to form a plurality of openings arranged along the intervals, and the remaining initial first patterned layer 30 forms the first patterned layer 30 .
[0107] The initial first patterned layer 30 may include a photoresist layer, and the photoresist layer is exposed using a mask plate (not shown) having a mask pattern to transfer the mask pattern on the mask plate to the photoresist layer. Subsequently, the photoresist layer is developed to remove a portion of the photoresist layer to form a plurality of openings in the photoresist layer to form the first patterned layer 30. The plurality of openings are arranged at intervals along a first direction, and the first direction may be Figure 2 In the X direction shown, the plurality of openings form a plurality of first grooves 31 .
[0108] In some possible examples, the initial first patterned layer 30 may further include an anti-reflection layer under the photoresist layer, that is, the photoresist layer is formed on the surface of the anti-reflection layer away from the second silicide layer 23. After the photoresist layer is exposed and developed, the anti-reflection layer is etched with the photoresist layer as a mask so that a plurality of openings extend to the anti-reflection layer, and the remaining photoresist layer and the anti-reflection layer form the first patterned layer 30.
[0109] By providing an anti-reflective layer, the standing wave effect of the photoresist layer can be alleviated or eliminated, thereby increasing the accuracy of the mask pattern transferred from the mask to the photoresist layer, thereby improving the accuracy of the pattern transfer process. In addition, the material of the anti-reflective layer does not contain nitrogen, which can prevent nitrogen ions from forming ammonia radicals with hydrogen ions in the photoresist layer, thereby preventing ammonia radicals from adhering to the surface of the photoresist layer, thereby reducing the difficulty of ablating the remaining photoresist layer.
[0110] The disclosed embodiment also provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure described in any of the above embodiments. Therefore, the semiconductor structure has the beneficial effects described above, and this embodiment will not be described in detail here. It should be noted that the semiconductor structure in this embodiment may include a dynamic random access memory (DRAM), but is not limited to this.
[0111] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0112] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.
[0113] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, and sequentially forming a target layer to be etched and a first patterned layer on the substrate, wherein the target layer to be etched comprises a first silicide layer, a first polysilicon layer, and a second silicide layer stacked in sequence, and the first patterned layer comprises a plurality of first patterns; Using the first patterned layer as a mask, etching the target layer to be etched to pattern the target layer to be etched to obtain a second patterned layer, wherein the second patterned layer includes a plurality of second patterns; forming a sidewall spacer and a second polysilicon layer, wherein the sidewall spacer covers the sidewalls of the plurality of second patterns, and the second polysilicon layer fills the gaps between the sidewall spacers; removing the film layer structure located above the first polysilicon layer to expose the first polysilicon layer; removing the sidewall spacer between the first polysilicon layer and the second polysilicon layer; The substrate is etched using the etched first polysilicon layer and the second polysilicon layer as masks to obtain the semiconductor structure.
2. The preparation method according to claim 1, characterized in that: The forming of the sidewall spacer and the second polysilicon layer further comprises: Depositing a third silicide layer, wherein the third silicide layer covers the sidewalls and top wall of the second pattern and the area exposed by the second pattern, and the second silicide layer located on the sidewalls of the second pattern forms the sidewall; Depositing a second polysilicon layer, wherein the second polysilicon layer is filled between the sidewalls, and a top surface of the second polysilicon layer is higher than a top surface of the third silicide layer or is flush with a top surface of the third silicide layer; The film layer structure includes the first silicide layer and the third silicide layer located above the first polysilicon layer.
3. The preparation method according to claim 2, characterized in that: The film layer structure is removed by an etching process, and the etching rate of the second polysilicon layer, the second silicide layer and the third silicide layer is the same.
4. The preparation method according to claim 2, characterized in that: The removing of the film layer structure located above the first polysilicon layer further comprises: Using a first etching process to remove the second polysilicon layer until the top surface of the remaining second polysilicon layer is flush with the top surface of the third silicide layer; A second etching process is used to remove the second silicide layer, the third silicide layer on the side and top surface of the second silicide layer, and a portion of the second polysilicon layer until the top surface of the remaining second polysilicon layer is flush with the top surface of the first polysilicon layer.
5. The preparation method according to claim 4, characterized in that: The second etching process has the same etching rate for the second polysilicon layer, the second silicide layer and the sidewall.
6. The preparation method according to any one of claims 2 to 5, characterized in that: The thickness of the third silicide layer at the region exposed by the second pattern is the same as the thickness of the first silicide layer.
7. The preparation method according to any one of claims 1 to 5, characterized in that: The first silicide layer and the second silicide layer are made of the same material, wherein the first silicide layer is made of silicon oxide or silicon nitride.
8. The preparation method according to claim 2, characterized in that: The third silicide layer is made of the same material as the first silicide layer and the second silicide layer, and the material of the third silicide layer includes silicon oxide or silicon nitride.
9. The preparation method according to any one of claims 2 to 5, characterized in that: The width of the second pattern is the same as the width of the gap between the sidewalls.
10. The preparation method according to any one of claims 2 to 5, characterized in that: An advanced pattern film layer is also formed between the substrate and the target layer to be etched, and etching the substrate to obtain the semiconductor structure further includes: Using the remaining first polysilicon layer and the second polysilicon layer as masks, etching the advanced pattern film layer; removing the first polysilicon layer, the first silicide layer, the second polysilicon layer and the third silicide layer located on the advanced pattern film layer, and etching the substrate using the etched advanced pattern film layer as a mask; The advanced graphic film layer is removed to obtain the semiconductor structure.
11. A semiconductor structure, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 10.
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Substrate etching method and semiconductor process equipment
CN120600629A