Low-temperature bonding method of chip

Abstract

The invention relates to the technical field of semiconductors, in particular to a low-temperature bonding method of a chip, which comprises the following steps of: preparing an upper chip with a micro bump which comprises a low-temperature material containing Sn; preparing a lower chip with a copper column, and reducing the roughness of the bonding surface of the copper column; and enabling the bonding surfaces of the micro bumps and the copper columns to be opposite, and carrying out bonding in a vacuum environment under the conditions that the temperature is 50-150 DEG C, the pressure is 10-40MPa and the pulse voltage is 2-6V. According to the low-temperature bonding method of the chip, low-temperature bonding can be realized, the bonding stability is improved, thermal damage caused by bonding is reduced, and the problem of warping of substrates of the upper chip and the lower chip after bonding is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low-temperature bonding method for a chip. Background Art

[0002] With the rapid development of the semiconductor industry, integrated circuit electronic packaging is rapidly developing in the direction of miniaturization, high performance, high density, and multi-chip. The development of miniaturized and multifunctional electronic products makes the devices prone to thermal damage and substrate warping during the packaging and assembly process.

[0003] In view of this, the present invention is proposed. Summary of the invention

[0004] The object of the present invention is to provide a low-temperature bonding method for chips, wherein the micro-bumps of the upper chip include a low-temperature material containing Sn, and the bonding surface of the copper column of the lower chip is roughened, and after the micro-bumps of the upper chip and the bonding surfaces of the copper column of the lower chip are aligned, bonding is performed by spark plasma sintering to achieve the purpose of bonding at low temperature, improve the stability of bonding, reduce the thermal damage caused by bonding, and improve the warping problem of the substrates of the upper chip and the lower chip after bonding.

[0005] The embodiment of the present invention is achieved as follows: The present invention provides a low-temperature bonding method for a chip, comprising: preparing an upper chip with micro-bumps, wherein the micro-bumps include a low-temperature material containing Sn; preparing a lower chip with a copper pillar and reducing the roughness of the bonding surface of the copper pillar; The bonding surfaces of the micro-bump and the copper pillar are placed opposite each other and bonded in a vacuum environment at a temperature of 50-150°C, a pressure of 10-40MPa, and a pulse voltage of 2-6V.

[0006] In an optional embodiment, the vacuum degree of the vacuum environment is less than 10Pa.

[0007] In an optional embodiment, the bonding step specifically includes: heating the temperature to 50-150° C. at a heating rate of 45-50° C. / min for bonding.

[0008] In an optional embodiment, the bonding time is 30-60 minutes.

[0009] In an optional embodiment, the roughness of the bonding surface of the copper pillar is less than 0.5 nm, and the flatness of the bonding surface of the copper pillar is less than 5%.

[0010] In an alternative embodiment, the cooling after bonding is furnace cooling.

[0011] In an optional embodiment, the low-temperature material containing Sn includes: Sn-In material, Sn-Bi material and Sn-Zn material.

[0012] In an optional embodiment, the bonding step specifically includes: assembling the upper chip and the lower chip on a bonding mold respectively, and then using the bonding mold to make the bonding surfaces of the micro-bumps and the copper pillars face each other.

[0013] In an optional embodiment, the bonding mold includes two clamping members, each of which is provided with a recess, and the two clamping members are spliced ​​with each other, and the recesses of the two clamping members are spliced ​​to form a groove, and the groove is used to place the upper chip or the lower chip.

[0014] In an optional embodiment, the flatness of the bottom of the groove is less than 1 nm, and the depth of the groove is less than the thickness of the upper chip and less than the thickness of the lower chip.

[0015] The beneficial effects of the low-temperature bonding method of the chip of the embodiment of the present invention include: the low-temperature bonding method of the chip provided by the embodiment of the present invention prepares micro-bumps including a low-temperature material containing Sn on the upper chip, and the low-temperature material containing Sn has a low melting point, which is conducive to reducing the temperature required for bonding during subsequent bonding; the bonding surface of the copper column of the lower chip is roughened to reduce the roughness of the bonding surface, which is conducive to improving the strength and stability after bonding, especially when bonding at a lower temperature, it is also helpful to ensure the stability and strength of the bonding; the discharge plasma sintering method is used during bonding, and bonding pressure and pulse current are applied at the same time, so as to reduce the temperature during bonding and ensure stable and reliable low-temperature bonding. In this way, the thermal damage caused by bonding can be effectively reduced by low-temperature bonding, and the warping problem of the substrates of the upper chip and the lower chip after bonding can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a cross-sectional view of an upper chip in an embodiment of the present invention; Figure 2 is a cross-sectional view of a lower chip in an embodiment of the present invention; Figure 3 Schematic diagram of bonding an upper chip and a lower chip in an embodiment of the present invention; Figure 4 It is a structural schematic diagram of a bonding mold in an embodiment of the present invention; Figure 5Schematic diagram of the structure of the clamping member in an embodiment of the present invention.

[0018] Icon: 010-bonding mold; 100-clamping piece; 110-base; 120-pressing head; 121-depression; 122-groove; 123-blocking piece; 200-upper chip; 210-micro bump; 300-lower chip; 310-copper pillar. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0020] Please refer to Figure 1 , Figure 2 and Figure 3 The present disclosure provides a low-temperature bonding method for a chip, which comprises: Prepare an upper chip 200 having micro bumps 210, wherein the micro bumps 210 include a low-temperature material containing Sn; Prepare a lower chip 300 having a copper pillar 310, and reduce the roughness of the bonding surface of the copper pillar 310; The bonding surfaces of the micro-bump 210 and the copper pillar 310 are placed opposite to each other, and bonding is performed in a vacuum environment at a temperature of 50-150°C (for example, 50°C, 70°C, 90°C, 110°C, 130°C, 150°C, etc., not specifically limited here), a pressure of 10-40MPa (for example, 10MPa, 20MPa, 30MPa, 40MPa, etc., not specifically limited here), and a pulse voltage of 2-6V (for example, 2V, 3V, 4V, 5V, 6V, etc., not specifically limited here).

[0021] Micro bumps 210 made of a low-temperature material containing Sn are prepared on the upper chip 200. The low-temperature material containing Sn has a low melting point, which is conducive to reducing the temperature required for bonding during subsequent bonding. The bonding surface of the copper pillar 310 of the lower chip 300 is roughened to reduce the roughness of the bonding surface, which is conducive to improving the strength and stability after bonding, especially when bonding at a lower temperature, it is also helpful to ensure the stability and strength of the bonding. During bonding, a discharge plasma sintering method is adopted, and bonding pressure and pulse current are applied at the same time to reduce the temperature during bonding and ensure stable and reliable low-temperature bonding. In this way, the thermal damage caused by bonding can be effectively reduced by low-temperature bonding, and the warping problem of the substrates of the upper chip 200 and the lower chip 300 after bonding can be improved.

[0022] It should be noted that spark plasma sintering uses pulsed current, which will generate discharge plasma at the moment of power-on, generate Joule heat inside the sintered body and activate the surface, that is, it can activate the surfaces of the micro-bumps 210 and copper pillars 310 that need to be bonded, so that the bonding surfaces of the micro-bumps 210 and copper pillars 310 can be reliably bonded, thereby playing a role in lowering the bonding temperature, that is, there is no need to activate the bonding surfaces of the micro-bumps 210 and copper pillars 310 by high temperature; on the other hand, the pulsed current can promote atomic diffusion and make the bonding strength more stable, that is, the pulsed current can cause the atoms of the micro-bumps 210 and the atoms of the copper pillars 310 to diffuse with each other to improve the strength and stability of the bond between the two.

[0023] It should also be noted that the low-temperature bonding method of the chip disclosed in the present invention can further ensure the stability of low-temperature bonding and fully improve the heat loss caused by bonding and the warping of the chip substrate by combining the low-temperature material of the micro-bump 210 and the spark plasma sintering method.

[0024] Optionally, bonding can be performed in a vacuum furnace, wherein the vacuum degree of the vacuum environment is less than 10Pa, for example, 9.5Pa, 9Pa, 8.5Pa, 8Pa, etc., which are not specifically limited here. Optimizing the vacuum degree of the vacuum furnace can ensure stable and reliable bonding at a lower temperature, and can effectively improve the problem of damage and warping of the substrate of the upper chip 200 and the substrate of the lower chip 300.

[0025] Optionally, during bonding, the temperature can be heated from room temperature to 50-150°C at a heating rate of 45-50°C / min (for example, 45°C / min, 46°C / min, 47°C / min, 48°C / min, 49°C / min, 50°C / min, etc., not specifically limited herein) for bonding. Optimizing the heating rate during bonding can, on the one hand, play a certain preheating role during bonding, which is conducive to uniform activation of atoms on the bonding surface of the micro-bump 210 and the copper pillar 310, so as to ensure uniform diffusion of atoms during bonding, thereby ensuring the stability and strength of bonding at low temperatures, and on the other hand, ensuring the controllability of the bonding temperature, improving the thermal damage caused by the rapid increase in the bonding temperature, and improving the warping problem of the substrate of the upper chip 200 and the lower chip 300.

[0026] Optionally, the bonding time is 30-60 minutes, for example, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc., which is not specifically limited here. Optimizing the bonding time can ensure the strength and stability of the bonding and improve chip damage, warping and other problems caused by bonding.

[0027] Optionally, after bonding in a vacuum furnace, the cooling method is to cool to room temperature in the furnace. In this way, the cooling rate can be slowed down. On the one hand, the residual temperature in the furnace can be used to further ensure the atomic diffusion between the bonding surfaces of the micro-bump 210 and the copper pillar 310 to improve the strength and stability of the bonding. On the other hand, it can avoid the problem of large stress generated by the bonded chip due to the large temperature difference in a short time, thereby improving the problem of cracks in the bonding position and ensuring the strength and stability of the bonding.

[0028] Optionally, the roughness of the bonding surface of the copper pillar 310 is less than 0.5 nm (for example, 0.45 nm, 0.4 nm, 0.35 nm, 0.3 nm, etc., which are not specifically limited here), and the flatness of the bonding surface of the copper pillar 310 is less than 5% (for example, 4.5%, 4%, 3.5%, 3%, etc., which are not specifically limited here). Reducing the roughness of the bonding surface of the copper pillar 310 can, on the one hand, reduce the roughness to make atoms diffuse faster to improve the stability of the bonding, and on the other hand, improve the stability of the bonding and ensure the bonding strength by improving the problem of oxidation of the bonding surface, that is, avoid the reduction of the stability and strength of the bonding due to oxidation of the bonding surface.

[0029] The preparation method of the lower chip 300 with the copper pillar 310 is similar to the related technology, for example: the lower chip 300 with the copper pillar 310 is prepared by sputtering, coating, exposure, development, dry stripping, electroplating, stripping, etching, reflow thinning and dicing process, and the specific process will not be repeated here.

[0030] The method of pre-treating the bonding surface of the copper pillar 310 is similar to related technologies, such as chemical mechanical polishing (CMP), plasma surface activation, surface wet chemical treatment and self-assembled molecular layer, etc. The specific process will not be repeated here.

[0031] It should be noted that after reducing the roughness of the copper pillar 310, the lower chip 300 can also be cleaned by blowing or the like to ensure that there are no particles with a particle size of about 1 μm on the surface of the lower chip 300 and its copper pillar 310, thereby improving the cleanliness and improving the problem of particulate impurities on the surface of the copper pillar 310, which leads to reduced bonding stability.

[0032] Optionally, the preparation method of the upper chip 200 with micro-bumps 210 is similar to the related technology, for example: the upper chip 200 with micro-bumps 210 is prepared by sputtering, coating, exposure, development, dry stripping, electroplating, stripping, etching, reflow thinning and scribing process, and the specific process will not be repeated here.

[0033] Optionally, the Sn-containing low-temperature material includes: Sn-In material, Sn-Bi material and Sn-Zn material; these materials have a melting point below 200°C, good wettability, good mechanical properties, and are not easily oxidized. By selecting the material, the strength and stability of the bonding between the micro-bump 210 and the copper pillar 310 can also be improved.

[0034] Furthermore, Sn-In material may refer to: Sn-52In with a mass percentage of indium of 52%, etc., which is not specifically limited here; Sn-Bi material may refer to: Sn-58Bi with a mass percentage of bismuth of 58%, etc., which is not specifically limited here; Sn-Zn material may refer to: Sn-8.9Zn with a mass percentage of zinc of 8.9%, etc., which is not specifically limited here.

[0035] Please refer to Figure 3 Optionally, during bonding, the upper chip 200 and the lower chip 300 are respectively assembled on the bonding mold 010, and then the bonding mold 010 is used to make the bonding surfaces of the micro-bumps 210 and the copper pillars 310 face each other, and the bonding mold 010 provides pressure during bonding, that is, the upper chip 200 is assembled on one bonding mold 010, and the micro-bumps 210 are exposed, and the lower chip 300 is assembled on another bonding mold 010, and the copper pillars 310 are exposed, and the two bonding molds 010 are opposed to each other so that the micro-bumps 210 and the copper pillars 310 are aligned, and the bonding mold 010 is used to apply pressure to press the micro-bumps 210 and the copper pillars 310 together.

[0036] For further information, please refer to Figure 4 The bonding mold 010 includes two clamping members 100, each of which is provided with a recess 121. The two clamping members 100 are spliced ​​with each other, and the recesses 121 of the two clamping members 100 are spliced ​​to form a groove 122, and the groove 122 is used to place the upper chip 200 or the lower chip 300. Such a configuration can ensure the stability and ease of operation of the chip assembly on the bonding mold 010.

[0037] Optionally, see Figure 4 and Figure 5 The groove 122 formed by the splicing of the two clamping members 100 is located in the middle of the splicing structure of the two clamping members 100. In this way, the accuracy of the alignment between the micro bumps 210 provided on the upper chip 200 and the copper pillars 310 provided on the lower chip 300 can be ensured by the two bonding molds 010.

[0038] Optionally, the clamp 100 includes a base 110 and a pressing head 120 detachably mounted on the base 110, and the pressing head 120 is provided with a recess 121; the detachable connection method between the pressing head 120 and the base 110 includes but is not limited to threaded connection, clamping, plug-in connection, etc. By configuring the pressing head 120 to be detachably connected to the base 110, different pressing heads 120 can be replaced as needed, for example, replacing a pressing head 120 with a different size of recess 121 according to the size of the chip, or replacing a new pressing head 120 when the pressing head 120 is damaged.

[0039] Furthermore, the pressing head 120 is also connected to a blocking member 123, which is located at the recess 121 to prevent the chip set in the groove 122 formed by the two pressing heads 120 from escaping from the groove 122. That is, when the pressing heads 120 of the two clamping members 100 are spliced, the blocking member 123 is located at the notch of the groove 122 to prevent the chip set in the groove 122 from escaping from the groove 122.

[0040] Optionally, the flatness of the bottom of the groove 122 is less than 1 nm, and the depth of the groove 122 is less than the thickness of the upper chip 200 and less than the thickness of the lower chip 300. By optimizing the flatness, it is possible to ensure that the upper chip 200 and the lower chip 300 remain parallel during the bonding process, thereby improving the bonding yield rate.

[0041] The present invention is further described in detail below in conjunction with embodiments.

[0042] Example 1 An upper chip with micro-bumps is prepared, wherein the micro-bumps are made of Sn-52In low-temperature material.

[0043] A lower chip with a copper pillar was prepared, and the bonding surface of the copper pillar had a roughness of 0.45 nm and a flatness of 4.5%.

[0044] The bonding surfaces of the micro-bump and the copper pillar are made to face each other; in a vacuum environment with a vacuum degree of 9 MPa, the temperature is increased to 50°C at a heating rate of 45°C / min, and the bonding pressure is controlled to be 40 MPa, while the pulse voltage is 4V, and the bonding is performed for 50 minutes; after bonding, the furnace is cooled.

[0045] Example 2 An upper chip with micro-bumps is prepared, wherein the micro-bumps are made of Sn-58Bi low-temperature material.

[0046] A lower chip with a copper pillar was prepared, and the bonding surface of the copper pillar had a roughness of 0.40 nm and a flatness of 4.0%.

[0047] The bonding surfaces of the micro-bump and the copper pillar are made to face each other; in a vacuum environment with a vacuum degree of 9.5 MPa, the temperature is increased to 150°C at a heating rate of 50°C / min, and the bonding pressure is controlled to be 10 MPa, while the pulse voltage is 2V, and the bonding is performed for 30 minutes; after bonding, the temperature is cooled in the furnace.

[0048] Example 3 An upper chip with micro-bumps is prepared, wherein the micro-bumps are made of Sn-8.9Zn low-temperature material.

[0049] A lower chip with a copper pillar was prepared, and the bonding surface of the copper pillar had a roughness of 0.42 nm and a flatness of 3%.

[0050] The bonding surfaces of the micro-bump and the copper pillar are made to face each other; in a vacuum environment with a vacuum degree of 8MPa, the temperature is increased to 80°C at a heating rate of 47°C / min, and the bonding pressure is controlled to be 20MPa. At the same time, the pulse voltage is 6V and the bonding is performed for 60min; after bonding, the furnace is cooled.

[0051] Example 4 The difference between Example 4 and Example 1 is that the roughness of the bonding surface of the copper column is 0.1 nm, and other process parameters refer to Example 1.

[0052] Comparative Example 1 The difference between Comparative Example 1 and Example 1 is that the material of the micro-bumps of the upper chip is copper, and the temperature during bonding is 400° C.; other process parameters refer to Example 1.

[0053] Comparative Example 2 The difference between Comparative Example 2 and Example 1 is that the bonding temperature is 160° C.; other process parameters refer to Example 1.

[0054] Comparative Example 3 The difference between Comparative Example 3 and Example 1 is that the pulse voltage during bonding is 1V; other process parameters refer to Example 1.

[0055] Comparative Example 4 The difference between Comparative Example 4 and Example 1 is that the bonding temperature is 40° C. and the pulse voltage is 8 V; other process parameters refer to Example 1.

[0056] Comparative Example 5 The difference between Comparative Example 5 and Example 1 is that the vacuum degree during bonding is 10 Pa, the temperature during bonding is 40° C., the pressure is 5 MPa, and the pulse voltage is 8 V; other process parameters refer to Example 1.

[0057] Comparative Example 6 The difference between Comparative Example 6 and Example 1 is that the bonding method is not spark plasma sintering, that is, during bonding, the temperature, pressure and time are controlled in the manner of Example 1, but no pulse current is provided; other process parameters refer to Example 1.

[0058] The bonded chip structures provided in Examples 1 to 4 and Comparative Example 1 were subjected to substrate warpage detection of the upper chip 200 and the lower chip 300. The warpage detection was performed using a wafer-level warpage tester. The detection results are shown in Table 1.

[0059] Table 1

[0060] The bonding strength of the bonded chip structures provided in Examples 1 to 4 and Comparative Examples 1 to 6 was tested. The test results are shown in Table 2.

[0061] Table 2

[0062] According to Table 1 and Table 2, by comparing Examples 1 to 4 and Comparative Example 1, it can be seen that although high temperature bonding can greatly improve the pull-out strength, the warpage is greatly increased, resulting in a decrease in the qualified rate of the chips after bonding.

[0063] According to Table 2 comparing Examples 1 to 4 and Comparative Example 2, it can be seen that an appropriate bonding temperature can effectively improve the pull-out strength of the chip after bonding. When the bonding temperature is too high, the bonding solder will melt and extrude, thereby reducing the bonding strength.

[0064] According to Table 2, by comparing Examples 1 to 4 with Comparative Example 3, it can be seen that the use of a suitable pulse voltage can effectively improve the pull-out strength of the chip after bonding.

[0065] According to Table 2, comparing Examples 1 to 4 and Comparative Example 4, it can be seen that the bonding temperature and the pulse voltage can synergistically improve the pull-out strength of the chip after bonding.

[0066] According to Table 2, comparing Examples 1 to 4 and Comparative Example 5, it can be seen that the vacuum degree, temperature, pressure and pulse voltage during bonding can synergistically improve the pull-out strength of the chip after bonding.

[0067] According to Table 2, by comparing Examples 1 to 4 with Comparative Example 6, it can be seen that the use of spark plasma sintering can improve the pull-out strength of the chip after bonding.

[0068] In summary, the low-temperature bonding method of the chip of the present invention can achieve low-temperature bonding, improve the bonding stability and pulling strength, reduce the thermal damage caused by bonding, and improve the warping problem of the substrate of the upper chip 200 and the lower chip 300 after bonding.

[0069] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A low temperature bonding method for a chip, characterized in that: include: Preparing an upper chip with micro-bumps, wherein the micro-bumps include a low-temperature material containing Sn; preparing a lower chip having a copper pillar, and reducing the roughness of a bonding surface of the copper pillar; The bonding surfaces of the micro-bump and the copper column are placed opposite to each other, and bonding is performed under a vacuum environment at a temperature of 50-150° C., a pressure of 10-40 MPa, and a pulse voltage of 2-6V.

2. The low temperature bonding method of a chip according to claim 1, characterized in that: The vacuum degree of the vacuum environment is less than 10Pa.

3. The low temperature bonding method of a chip according to claim 1, characterized in that: The bonding step specifically includes: heating the temperature to 50-150° C. at a heating rate of 45-50° C. / min to perform the bonding.

4. The low temperature bonding method of a chip according to claim 1, characterized in that: The bonding time is 30-60 minutes.

5. The low temperature bonding method of a chip according to claim 1, characterized in that: The roughness of the bonding surface of the copper column is less than 0.5 nm, and the flatness of the bonding surface of the copper column is less than 5%.

6. The low temperature bonding method of a chip according to claim 1, characterized in that: The cooling after bonding is furnace cooling.

7. The low temperature bonding method of a chip according to claim 1, characterized in that: The Sn-containing low-temperature material includes: Sn-In material, Sn-Bi material and Sn-Zn material.

8. The low temperature bonding method of a chip according to claim 1, characterized in that: The bonding step specifically includes: assembling the upper chip and the lower chip on a bonding mold respectively, and then using the bonding mold to make the bonding surfaces of the micro-bumps and the copper pillars face each other.

9. The low temperature bonding method of a chip according to claim 8, characterized in that: The bonding mold includes two clamping parts, each of which is provided with a recess, and the two clamping parts are spliced ​​with each other, and the recesses of the two clamping parts are spliced ​​to form a groove, and the groove is used to place the upper chip or the lower chip.

10. The low temperature bonding method of a chip according to claim 9, characterized in that: The flatness of the bottom of the groove is less than 1 nm, and the depth of the groove is less than the thickness of the upper chip and less than the thickness of the lower chip.

Images