SiC trench MOSFET super junction for enhancing reverse recovery performance and preparation method thereof

Abstract

The invention relates to a SiC trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) super junction for enhancing reverse recovery performance and a preparation method of the SiC trench MOSFET super junction, and the SiC trench MOSFET super junction comprises a drain electrode, an n + substrate, an n-type drift region and two source electrodes which are bilaterally symmetrical, the left end and the right end of the n-column region respectively comprise a p1 + base region, a high-concentration first n + source region and a super junction region formed by a low-concentration n1 + region, the p1 + base regions are in bilateral symmetry, the p + source regions are in bilateral symmetry, the p body region is in bilateral symmetry, and the second n + source region is in bilateral symmetry. The n column region, the p + shielding region, the p body region and the second n + source region jointly form a groove, a gate oxide layer is arranged on the groove, and gate metal is arranged on the gate oxide layer; the sources are located at the left and right ends of the gate oxide layer respectively. According to the invention, the reverse recovery capability is strong, the voltage resistance is improved, the parasitic capacitance is reduced, the switching speed is improved, and the on-resistance is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of transistors, and in particular relates to a SiC trench MOSFET super junction for enhancing reverse recovery performance and a preparation method thereof. Background Art

[0002] Power MOSFETs exhibit faster switching capabilities, making them more popular than traditional bipolar devices in high-frequency power switching applications. The advent of superjunction technology has demonstrated significant advantages in power devices. Unlike traditional planar structures, superjunction technology combines vertical pn junctions to significantly increase the breakdown voltage without expanding the chip area. The technology also significantly reduces on-resistance, minimizes power losses, and improves overall performance.

[0003] However, the introduction of superjunctions also brings significant challenges. In superjunction devices, the reverse recovery performance of diodes or MOSFETs is poor. To address this problem, various technologies have been proposed at home and abroad to optimize and improve the reverse recovery performance of MOS devices. One approach is to use Si / SiC heterojunction diodes, but despite their benefits, their high interface state density has an adverse effect on device performance. The complexity of the heterojunction structure further complicates packaging, and fast switching may lead to higher frequency electromagnetic interference.

[0004] Schottky diodes, while advantageous in some respects, have a high interface state density, resulting in a Fermi level pinning effect. This makes it difficult to control the on-voltage, leading to poor thermal performance and reliability. On the other hand, trench diodes compromise device reliability, result in poor thermal conductivity and heat dissipation, and typically exhibit longer reverse recovery times than Schottky diodes.

[0005] Chinese patent publication number CN219017662U discloses a SiC trench MOSFET device, including a substrate layer, an N-drift region formed by epitaxy on the upper side of the substrate layer, a gate region trench formed on the upper surface of the N-drift region, a silicon dioxide layer formed on the bottom and sidewalls of the gate region trench, the remaining gap on the silicon dioxide layer in the trench is filled with gate polysilicon, a P well region is formed on both sides of the gate region trench, an N+ region and a P+ region are formed on each of the P well regions, the thickness of the P+ region is greater than the thickness of the N+ region, the P+ region is arranged outside the device, the N+ region is arranged inside the device, a gate is formed on the upper surface of the polysilicon, the two ends of the gate extend to the edge of the N+ region, a source is formed on the upper surface of the P+ region, and the source extends to the upper surface of the N+ region, and a drain is formed on the lower surface of the substrate layer. Although it can solve the problem of premature breakdown at the corner of the trench, it still requires a long reverse recovery time. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a SiC trench MOSFET super junction for enhancing reverse recovery performance and a preparation method thereof, which has the ability of strong reverse recovery, improved voltage resistance, reduced parasitic capacitance, increased switching speed, and reduced on-resistance.

[0007] The present invention provides a SiC trench MOSFET super junction for enhancing reverse recovery performance, which includes a drain, an n+ substrate, an n-type drift region and two left-right symmetrical source electrodes, wherein the drain, the n+ substrate and the n-type drift region are arranged in sequence from bottom to top, an n-column region is provided above the n-drift region, the n-column region is in a concave shape, and both left and right ends of the n-column region include a left-right symmetrical p1+ base region, a high-concentration first n+ source region and a low-concentration n1+ region to form a super junction region, the p1+ base region is in an L-shape, the bottom of which is connected to the n-type drift region, and the side surface is closely attached to the n-column region and extends upward, the first n+ source region and the n1+ region are both located in the L-shaped groove of the p1+ base region, and the n1+ region is closely attached to the n-column region and extends upward The first n+ source region is located above the n1+ region; the two ends of the top of the n column region include a left-right symmetrical p+ source region, a p body region and a high-concentration second n+ source region, the p+ source region and the p body region are closely attached to the n column region, the second n+ source region is located above the p body region, and the p+ source region is located between the first n+ source region and the second n+ source region; a p+ shielding region is provided in the groove at the top of the n column region, the n column region, the p+ shielding region, the p body region, and the second n+ source region jointly form a groove, a gate oxide layer is provided on the groove, and a gate metal is provided on the gate oxide layer; the source electrode is respectively located at the left and right ends of the gate oxide layer, and covers the second n+ source region, the p+ source region, the first n+ source region, and the p1+ base region.

[0008] Preferably, the thickness and concentration of the first n+ source region are consistent with those of the second n+ source region.

[0009] Preferably, the doping concentration of the n column region is 1.0×10 19 cm -3 .

[0010] Preferably, the thickness of the first n+ source region is 0.3 μm and the doping concentration is 1.0×10 19 cm -3 The second n+ source region has a thickness of 0.3 μm and a doping concentration of 1.0×10 19 cm -3 .

[0011] Preferably, the doping concentration of the p1+ base region is 5.0×10 16 cm -3 .

[0012] Preferably, the doping concentration of the n1+ region is 1.0×10 16 cm -3 .

[0013] Preferably, the p+ shielding region has a thickness of 0.2 μm and a doping concentration of 1.0×10 19 cm -3 .

[0014] Preferably, the source width is 2.5 μm, the gate width is 3.0 μm, and the gate thickness is 1.7 μm.

[0015] Preferably, the gate oxide layer has a thickness of 0.05 μm.

[0016] A method for preparing a SiC trench MOSFET super junction for enhancing reverse recovery performance comprises the following steps: S1: growing an epitaxial layer on a 4H-SiC substrate to form an n-drift region, and growing an n-column region above the n-drift region; S2: epitaxy and ion implantation are performed on the n-column region to form a bilaterally symmetrical p1+ base region; S3: Repeat the epitaxy and ion implantation process to generate a first n+ source region and an n1+ region in the p1+ base region; S4: further performing ion implantation above the n column region to complete the formation of p+ source regions at both ends, a p body region, and a second n+ source region; S5: then etching is performed starting from the top of the second n+ source region to form a groove penetrating to the n column region; S6: forming a p+ shielding region on the groove and forming a trench; S7: growing a gate oxide layer on the trench by thermal oxidation; after the thermal oxidation step, selectively removing the oxide layer in the trench source using a mask; S8: forming a gate metal in the gate oxide layer; S9: Deposit source and drain metals respectively to establish ohmic contacts and produce polysilicon gate.

[0017] The present invention has the following technical effects: 1. The super junction region is connected to the n-type drift region through the p1+ base region, which helps to smooth current conduction, eliminate electronic barriers, improve switching speed, and reduce switching losses; the high-concentration first n+ source region and the low-concentration n1+ region form a potential concentration difference, so that the super junction region has a high saturation electron velocity, which helps to reduce the switching time and improve the switching speed of the device, thereby reducing switching losses and shortening the reverse recovery time; the existence of the super junction region increases the pn junction area formed by the overall device, and increases the number of minority carriers in the depletion region, so that it has stronger reverse recovery performance, improves voltage resistance, reduces parasitic capacitance, improves switching speed, and reduces on-resistance.

[0018] 2. The p+ shielding region provides charge compensation for the n-column region and assists in depleting the n-column region. The n-column region and the p+ shielding region achieve charge balance together, improve the overall voltage resistance, and reduce parasitic capacitance. The n-column region and the p+ shielding region are alternately doped regions that can maintain charge balance under zero bias conditions. This charge balance enables the device to withstand a higher breakdown voltage without the need for heavily doped drift regions. The n-column region helps to evenly distribute the electric field when the device is in the off state. This uniform electric field distribution enables the device to have a higher breakdown voltage; due to the vertical arrangement of the n-column region and the p+ shielding region, the device can achieve a high breakdown voltage without sacrificing on-resistance. When the device is turned on, the n-column region can be used to reduce the on-resistance. When the device is working (gate is turned on), the n-column region is part of the current path; when the device is turned on, the current flows vertically through the n-column region, enhancing the overall current capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of a conventional 4H-SiC UMOSFET; Figure 2 This is a schematic diagram of the structure of this application; Figure 3 This is a schematic diagram of the structure of step 1 of the preparation method of this application; Figure 4 This is a schematic diagram of the structure of step 2 of the preparation method of this application; Figure 5 This is a schematic diagram of the structure of step 3 of the preparation method of this application; Figure 6 This is a schematic diagram of the structure of step 4 of the preparation method of this application; Figure 7 This is a schematic diagram of the structure of step 5 of the preparation method of this application; Figure 8 This is a schematic diagram of the structure of step 6 of the preparation method of this application; Fig. 9 This is a schematic diagram of the structure of step 7 of the preparation method of this application; Fig.10 This is a schematic diagram of the structure of step 8 of the preparation method of this application; Fig.11 This is a structural schematic diagram of step 9 of the preparation method of this application.

[0020] In the figure: 1. drain; 2. n+ substrate; 3. n-type drift region; 4. source; 5. n-column region; 6. p1+ base region; 7. first n+ source region; 8. n1+ region; 9. p+ source region; 10. p-body region; 11. second n+ source region; 12. p+ shielding region; 13. gate oxide layer; 14. gate metal. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings.

[0022] like Figure 1 Schematic diagram of the traditional 4H-SiC UMOSFET structure.

[0023] like Figure 2As shown, a SiC trench MOSFET super junction for enhancing reverse recovery performance includes a drain 1, an n+ substrate 2, an n-type drift region 3 and two left-right symmetrical source electrodes 4, wherein the drain 1, the n+ substrate 2 and the n-type drift region 3 are arranged in sequence from bottom to top, an n-column region 5 is provided above the n-drift region, and the n-column region 5 is concave in shape, and both left and right ends of the n-column region 5 include a left-right symmetrical p1+ base region 6, a high-concentration first n+ source region 7 and a low-concentration n1+ region 8 to form a super junction region, the p1+ base region 6 is L-shaped, the bottom of which is connected to the n-type drift region 3, and the side is closely attached to the n-column region 5 and extends upward, the first n+ source region 7 and the n1+ region 8 are both located in the L-shaped groove of the p1+ base region 6, the n1+ region 8 is closely attached to the n-column region 5 and extends upward, and the first n+ source region 7 is located The n1+ region 8 is above the n1+ region 8; the top two ends of the n column region 5 include a left-right symmetrical p+ source region 9, a p body region 10 and a high-concentration second n+ source region 11, the p+ source region 9 and the p body region 10 are closely attached to the n column region 5, the second n+ source region 11 is located above the p body region 10, and the p+ source region 9 is located between the first n+ source region 7 and the second n+ source region 11; a p+ shielding region 12 is provided in the groove at the top of the n column region 5, the n column region 5, the p+ shielding region 12, the p body region 10, and the second n+ source region 11 together form a groove, a gate oxide layer 13 is provided on the groove, and a gate metal 14 is provided on the gate oxide layer 13; the source electrode 4 is respectively located at the left and right ends of the gate oxide layer 13, and covers the second n+ source region 11, the p+ source region 9, the first n+ source region 7, and the p1+ base region 6.

[0024] The super junction region is connected to the n-type drift region 3 through the p1+ base region 6, which helps to smooth the current conduction, eliminate the electron barrier, improve the switching speed, and reduce the switching loss; the high-concentration first n+ source region 7 and the low-concentration n1+ region 8 form a potential concentration difference, so that the super junction region has a high saturation electron speed, which helps to reduce the switching time, improve the switching speed of the device, thereby reducing the switching loss and shortening the reverse recovery time; the super junction region increases the overall pn junction area, increases the number of minority carriers in the depletion region, so that it has stronger reverse recovery performance, improves voltage resistance, reduces parasitic capacitance, improves switching speed, and reduces on-resistance. Through the existence of the super junction region, a more heavily doped n-type drift region 3 can be used without increasing the on-resistance of the device, thereby improving the efficiency during operation.

[0025] The thickness and concentration of the first n+ source region 7 and the second n+ source region 11 are consistent. The thickness of the first n+ source region 7 is 0.3 μm, and the doping concentration is 1.0×10 19 cm -3 The second n+ source region 11 has a thickness of 0.3 μm and a doping concentration of 1.0×10 19cm -3 The p-body region 10 has a thickness of 0.6 μm and a doping concentration of 2.0×10 17 cm -3 The width of the source electrode 4 is 2.5 μm, the width of the gate electrode is 3.0 μm, and the thickness of the gate electrode is 1.7 μm. The thickness of the gate oxide layer 13 is 0.05 μm. The thickness of the n-type drift region 3 is 0.3 μm, and the doping concentration is 1.0×10 19 cm -3 The thickness of the p+ shielding region 12 is 0.2 μm, and the doping concentration is 1.0×10 19 cm -3 The thickness of the n+ substrate 2 is 0.2 μm. The doping concentration of the n column region 5 is 1.0×10 19 cm -3 The doping concentration of the p1+ base region 6 is 5.0×10 16 cm -3 The doping concentration of the n1+ region 8 is 1.0×10 16 cm -3 .

[0026] The p+ shielding region 12 provides charge compensation for the n-column region 5 and assists in depleting the n-column region 5. The n-column region 5 and the p+ shielding region 12 achieve charge balance together, improve the overall voltage resistance, and reduce parasitic capacitance. The n-column region 5 and the p+ shielding region 12 are alternately doped regions that can maintain charge balance under zero bias conditions. This charge balance enables the device to withstand a higher breakdown voltage without the need for a heavily doped drift region. The n-column region 5 helps to evenly distribute the electric field when the device is in the off state. This uniform electric field distribution enables the device to have a higher breakdown voltage; due to the vertical arrangement of the n-column region 5 and the p+ shielding region 12, the device can achieve a high breakdown voltage without sacrificing on-resistance. When the device is turned on, the n-column region 5 can be used to reduce the on-resistance. When the device is working (gate is turned on), the n-column region 5 is part of the current path; when the device is turned on, the current flows vertically through the n-column region 5, enhancing the overall current capability of the device.

[0027] A method for preparing a SiC trench MOSFET super junction for enhancing reverse recovery performance comprises the following steps: S1: Figure 3 As shown in the figure, an epitaxial layer is grown on a 4H-SiC substrate, and the doping concentration of the layer in the n-drift region is 3.0×10 15 cm 3 , with a thickness of 19.2 μm. Subsequently, the growth doping concentration was 1.0×10 16 cm 3 , an n column region 5 having a thickness of 19.2 μm.

[0028] S2: Figure 4 As shown, the n column region 5 is epitaxially grown and ion implanted to form a bilaterally symmetrical doping concentration of 5.0×10 16 cm 3 p1+ base region 6; S3: Figure 5 As shown, the epitaxy and ion implantation processes are repeated to produce a doping concentration of 1.0×10 19 cm 3 The first n+ source region 7 has a doping concentration of 1.0x10 16 cm 3 The n1+ region 8 domain, thereby forming a super junction region; S4: Figure 6 As shown, ion implantation is further performed above the n column region 5 to complete the doping concentration of both ends to be 1.0×10 19 cm 3 The p+ source region 9, the doping concentration is 2.0×10 17 cm 3 The p-body region has a doping concentration of 10 and a doping concentration of 1.0×10 19 cm 3 Formation of a second n+ source region 11; S5: Figure 7 As shown, etching is then performed starting from the top of the second n+ source region 11 to form a groove penetrating to the n column region 5; S6: Figure 8 As shown, a doping concentration of 1.0×10 19 cm 3 A p+ shielding region 12 is formed, and a trench is formed; S7: Fig. 9 As shown, a gate oxide layer 13 with a thickness of 0.05 μm is grown on the trench by thermal oxidation; after the thermal oxidation step, the oxide layer in the trench source 4 is selectively removed using a mask; S8: Fig.10 As shown, a gate metal 14 is formed in the gate oxide layer 13; S9: Fig.11 As shown, source 4 and drain 1 metals are deposited separately to establish ohmic contacts and produce a polysilicon gate.

[0029] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A SiC trench MOSFET super junction for enhancing reverse recovery performance, comprising a drain, an n+ substrate, an n-type drift region and two left-right symmetrical sources, wherein the drain, the n+ substrate and the n-type drift region are arranged sequentially from bottom to top, and characterized in that: An n-column region is provided above the n-drift region, and the n-column region is concave in shape. Both left and right ends of the n-column region include a left-right symmetrical p1+ base region, a high-concentration first n+ source region, and a super junction region formed by a low-concentration n1+ region. The p1+ base region is L-shaped, with its bottom connected to the n-type drift region, and its side surface is closely attached to the n-column region and extends upward. The first n+ source region and the n1+ region are both located in the L-shaped groove of the p1+ base region, and the n1+ region is closely attached to the n-column region and extends upward. The first n+ source region is located above the n1+ region; the top two ends of the n-column region include a left-right symmetrical p+ source region, a p-body region, and a region and a high-concentration second n+ source region, the p+ source region and the p-body region are closely attached to the n-column region, the second n+ source region is located above the p-body region, and the p+ source region is located between the first n+ source region and the second n+ source region; a p+ shielding region is provided in the top groove of the n-column region, the n-column region, the p+ shielding region, the p-body region, and the second n+ source region jointly form a groove, a gate oxide layer is provided on the groove, and a gate metal is provided on the gate oxide layer; the source electrodes are respectively located at the left and right ends of the gate oxide layer, and cover the second n+ source region, the p+ source region, the first n+ source region, and the p1+ base region.

2. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The thickness and concentration of the first n+ source region are consistent with those of the second n+ source region.

3. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The doping concentration of the n column region is 1.0×10 19 cm -3 .

4. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The thickness of the first n+ source region is 0.3 μm and the doping concentration is 1.0×10 19 cm -3 The second n+ source region has a thickness of 0.3 μm and a doping concentration of 1.0×10 19 cm -3 .

5. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The doping concentration of the p1+ base region is 5.0×10 16 cm -3 .

6. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The doping concentration of the n1+ region is 1.0×10 16 cm -3 .

7. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The p+ shielding region has a thickness of 0.2 μm and a doping concentration of 1.0×10 19 cm -3 .

8. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The source width is 2.5 μm, the gate width is 3.0 μm, and the gate thickness is 1.7 μm.

9. The SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: The gate oxide layer has a thickness of 0.05 μm.

10. A method for preparing a SiC trench MOSFET super junction for enhancing reverse recovery performance according to claim 1, characterized in that: It includes the following steps: S1: growing an epitaxial layer on a 4H-SiC substrate to form an n-drift region, and growing an n-column region above the n-drift region; S2: epitaxy and ion implantation are performed on the n-column region to form a bilaterally symmetrical p1+ base region; S3: Repeat the epitaxy and ion implantation process to generate a first n+ source region and an n1+ region in the p1+ base region; S4: further performing ion implantation above the n column region to complete the formation of p+ source regions at both ends, a p body region, and a second n+ source region; S5: then etching is performed starting from the top of the second n+ source region to form a groove penetrating to the n column region; S6: forming a p+ shielding region on the groove and forming a trench; S7: growing a gate oxide layer on the trench by thermal oxidation; after the thermal oxidation step, selectively removing the oxide layer in the trench source using a mask; S8: forming a gate metal in the gate oxide layer; S9: Deposit source and drain metals respectively to establish ohmic contacts and produce polysilicon gate.

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