High-precision reference voltage circuit

Abstract

According to the high-precision reference voltage circuit provided by the invention, the circuit comprises the anti-interference circuit module, the gain circuit module and the amplification buffer circuit module, so that the output voltage of the circuit has relatively low temperature coefficient, relatively high precision and relatively large output voltage swing. The circuit also comprises a biasing circuit and a voltage stabilization output circuit. The biasing circuit comprises an anti-interference circuit, so that the biasing circuit can work normally in a high-frequency electromagnetic interference environment. The bias circuit is arranged based on the circuit structure, so that the output bias voltage is stable and unchanged. The voltage stabilization output circuit comprises a gain circuit, so that the system has higher gain, and further has higher power supply rejection ratio. And an amplification buffer circuit in the voltage stabilization output circuit has a frequency compensation function, so that the system keeps stable operation in a low-frequency range and a high-frequency range. Meanwhile, based on the circuit structure of the amplification buffer circuit, the system has low output impedance, the current output capacity of the system is improved, and the output voltage has large voltage swing.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-precision reference voltage circuit. Background Art

[0002] The reference voltage circuit provides an accurate and stable reference voltage for the integrated circuit system as the reference voltage or threshold of the integrated circuit system. In order to make the output voltage of the reference voltage circuit have a lower temperature coefficient, curvature compensation technology, bandgap linearization technology, etc. are usually used for temperature compensation. However, the operational amplifier circuit used in the above-mentioned temperature offset compensation scheme based on resistance ratio has a large offset voltage, which seriously affects the output voltage accuracy of the reference voltage circuit. In addition, there are usually multiple high-frequency switching tubes in the integrated circuit system, and the high-frequency electromagnetic interference generated by them also has a great impact on the output accuracy of the reference voltage circuit. Summary of the invention

[0003] The problem solved by the present invention is to propose a high-precision reference voltage circuit. By including an anti-interference circuit module, a gain circuit module and an amplifying buffer circuit module in the circuit, the circuit output voltage has a lower temperature coefficient while having higher precision and a larger output voltage swing.

[0004] In order to solve the above problem, the present invention provides a high-precision reference voltage circuit including a bias circuit and a voltage-stabilizing output circuit.

[0005] The bias circuit is connected to the voltage-stabilizing output circuit, and the bias circuit outputs a precise and stable bias voltage to the voltage-stabilizing output circuit.

[0006] The bias circuit includes an anti-interference circuit, which enables the bias circuit to work normally in a high-frequency electromagnetic interference environment. Based on its circuit structure setting, the bias circuit can effectively shield the influence of power supply voltage jitter and make the output bias voltage stable.

[0007] The voltage-stabilized output circuit includes a gain circuit, which enables the system to have a higher gain and thus a higher power supply rejection ratio. The amplifier buffer circuit in the voltage-stabilized output circuit has a frequency compensation function, which enables the system to maintain stable operation in both low-frequency and high-frequency ranges. At the same time, based on its circuit structure, the amplifier buffer circuit enables the system to have a lower output impedance, improves the current output capacity of the system, and enables the output voltage to have a larger voltage swing. The merging circuit in the voltage-stabilized output circuit is mainly used to generate a reference voltage with a lower temperature coefficient.

[0008] The bias circuit includes a port VPES. The voltage regulated output circuit includes ports VCLS and VOUT.

[0009] The port VPES is connected to the port VCLS and is used to transmit the bias voltage Vbe. The port VOUT is a system output port and is used to output a reference voltage Vrt.

[0010] The bias circuit includes an anti-interference circuit and a bias voltage circuit.

[0011] The anti-interference circuit is connected to the bias voltage circuit, and the anti-interference circuit provides the bias voltage circuit with an anti-interference voltage, so that the bias voltage circuit can work normally in a high-frequency electromagnetic interference environment. The bias voltage circuit outputs a precise and stable bias voltage to the voltage stabilization output circuit.

[0012] The voltage-stabilized output circuit includes a gain circuit, an amplifying buffer circuit and a combining circuit.

[0013] The gain circuit is connected to the amplifier buffer circuit, and the gain circuit outputs a high gain voltage to the amplifier buffer circuit. The amplifier buffer circuit can stably output a high gain voltage in both low frequency and high frequency ranges through frequency compensation, and make the output voltage have a large voltage swing. The amplifier buffer circuit is connected to the merging circuit, and the amplifier buffer circuit outputs a voltage to the merging circuit. The merging circuit processes the voltage and outputs a reference voltage with a lower temperature coefficient.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention proposes a high-precision reference voltage circuit, including a bias circuit and a voltage-stabilizing output circuit. The bias circuit outputs a precise and stable bias voltage to the voltage-stabilizing output circuit, so that the voltage-stabilizing output circuit has high stability and precision. The bias circuit includes an anti-interference circuit, so that the bias circuit can work normally in a high-frequency electromagnetic interference environment. The bias circuit is set based on its circuit structure, which can effectively shield the influence of power supply voltage jitter and make the output bias voltage stable. The voltage-stabilizing output circuit includes a gain circuit, so that the system has a higher gain and thus has a higher power supply rejection ratio. The amplifying buffer circuit in the voltage-stabilizing output circuit has a frequency compensation function, so that the system maintains stable operation in both low-frequency and high-frequency ranges. At the same time, based on its circuit structure, the amplifying buffer circuit enables the system to have a lower output impedance, improves the current output capacity of the system, and enables the output voltage to have a larger voltage swing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0016] Figure 2 It is a schematic diagram of the principle structure of the bias circuit of the present invention;

[0017] Figure 3 It is a schematic diagram of the principle structure of the voltage-stabilizing output circuit of the present invention.

[0018] Description of reference numerals:

[0019] 1-bias circuit; 2-voltage stabilizing output circuit; 11-anti-interference circuit; 12-bias voltage circuit; 21-gain circuit; 22-amplifier buffer circuit; merging circuit. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, a high-precision reference voltage circuit includes a bias circuit 1 and a voltage-stabilizing output circuit 2 .

[0022] The bias circuit 1 is connected to the voltage stabilizing output circuit 2 , and the bias circuit 1 outputs a precise and stable bias voltage Vbe to the voltage stabilizing output circuit 2 .

[0023] The bias circuit 1 includes an anti-interference circuit, so that the bias circuit 1 can work normally in a high-frequency electromagnetic interference environment. Based on its circuit structure setting, the bias circuit 1 can effectively shield the influence of power supply voltage jitter and make the output bias voltage stable.

[0024] The voltage-stabilized output circuit 2 includes a gain circuit, which enables the system to have a higher gain and thus a higher power supply rejection ratio. The amplifier buffer circuit in the voltage-stabilized output circuit 2 has a frequency compensation function, which enables the system to maintain stable operation in both low-frequency and high-frequency ranges. At the same time, based on its circuit structure, the amplifier buffer circuit enables the system to have a lower output impedance, improves the current output capacity of the system, and enables the output voltage to have a larger voltage swing. The merging circuit in the voltage-stabilized output circuit 2 is mainly used to generate a reference voltage Vrt with a lower temperature coefficient.

[0025] The bias circuit 1 includes a terminal VPES.

[0026] The voltage regulated output circuit 2 includes ports VCLS and VOUT.

[0027] The port VPES is connected to the port VCLS and is used to transmit the bias voltage Vbe. The port VOUT is a system output port and is used to output a reference voltage Vrt.

[0028] like Figure 1 As shown, the bias circuit 1 includes an anti-interference circuit 11 and a bias voltage circuit 12 .

[0029] The anti-interference circuit 11 is connected to the bias voltage circuit 12, and the anti-interference circuit 11 provides the bias voltage circuit 12 with an anti-interference voltage Vgs, so that the bias voltage circuit 12 can work normally in a high-frequency electromagnetic interference environment. The bias voltage circuit 12 outputs a precise and stable bias voltage Vbe to the voltage stabilization output circuit 2.

[0030] like Figure 1 As shown, the voltage-stabilized output circuit 2 includes a gain circuit 21 , an amplifying buffer circuit 22 and a merging circuit 23 .

[0031] The gain circuit 21 is connected to the amplifier buffer circuit 22, and the gain circuit 21 outputs a high gain voltage Veh to the amplifier buffer circuit 22. The amplifier buffer circuit 22 can stably output a high gain voltage in both low frequency and high frequency ranges through frequency compensation, and make the output voltage have a large voltage swing. The amplifier buffer circuit 22 is connected to the merging circuit 23, and the amplifier buffer circuit 22 outputs a voltage Vpr to the merging circuit 23. The merging circuit 23 processes the voltage Vpr and outputs a reference voltage Vrt with a lower temperature coefficient.

[0032] like Figure 2 As shown, the anti-interference circuit 11 includes a self-bias power supply circuit 111 and a current limiting output circuit 112 .

[0033] The self-bias power supply circuit 111 is connected to the current limiting output circuit 112 , and the self-bias power supply circuit 111 outputs the anti-interference voltage Vgs to the current limiting output circuit 112 .

[0034] The self-bias power supply circuit 111 includes a MOS transistor M1 , a MOS transistor M2 , a MOS transistor M3 , and a MOS transistor M4 .

[0035] The source of MOS tube M1 is connected to the power supply VDD, the gate of MOS tube M1 is connected to the gate of MOS tube M2, and the drain of MOS tube M1 is connected to the drain of MOS tube M2. The drain of MOS tube M2 is connected to the drain of MOS tube M1, the gate of MOS tube M2 is connected to the drain of MOS tube M2, and the source of MOS tube M2 is connected to the drain of MOS tube M3. The drain of MOS tube M3 is connected to the source of MOS tube M2, the gate of MOS tube M3 is connected to the drain of MOS tube M3, and the source of MOS tube M3 is connected to the drain of MOS tube M4. The drain of MOS tube M4 is connected to the source of MOS tube M3, the gate of MOS tube M4 is connected to the gate of MOS tube M3, and the source of MOS tube M4 is grounded.

[0036] The MOS tube M1 , the MOS tube M2 , the MOS tube M3 , and the MOS tube M4 form a voltage-stabilized self-biased power supply structure, and provide a stable start-up voltage Vqk that is not interfered with for the MOS tube M5 .

[0037] The current limiting output circuit 112 includes a MOS transistor M5 and a MOS transistor M6.

[0038] The drain of MOS tube M5 is connected to the source of MOS tube M1, the gate of MOS tube M5 is connected to the drain of MOS tube M1, the source of MOS tube M5 is connected to the drain of MOS tube M6. The drain of MOS tube M6 is connected to the source of MOS tube M5, the gate of MOS tube M6 is connected to the drain of MOS tube M6, and the source of MOS tube M6 is connected to the drain of MOS tube M7.

[0039] The MOS transistor M5 and the MOS transistor M6 form a current limiting output structure, and output the anti-interference voltage Vgs to the bias voltage circuit 12 .

[0040] The bias voltage circuit 12 includes a shielding circuit 121 and a load circuit 122 .

[0041] The shielding circuit 121 is connected to the load circuit 122 , and the shielding circuit 121 outputs an accurate and stable bias voltage Vbe through the load circuit 122 .

[0042] The shielding circuit 121 includes a MOS transistor M8 , a MOS transistor M9 , a MOS transistor M10 , and a MOS transistor M11 .

[0043] The source of MOS tube M8 is connected to the power supply VDD, the gate of MOS tube M8 is connected to the gate of MOS tube M10, and the drain of MOS tube M8 is connected to the drain of MOS tube M9. The drain of MOS tube M9 is connected to the gate of MOS tube M9, the gate of MOS tube M9 is connected to the gate of MOS tube M11, and the source of MOS tube M9 is connected to the gate of MOS tube M7. The source of MOS tube M10 is connected to the source of MOS tube M8, the gate of MOS tube M10 is connected to the drain of MOS tube M10, and the drain of MOS tube M10 is connected to the drain of MOS tube M11. The drain of MOS tube M11 is connected to the gate of MOS tube M10, the gate of MOS tube M11 is connected to the drain of MOS tube M8, and the source of MOS tube M11 is connected to the drain of MOS tube M12.

[0044] The circuit structure formed by connecting MOS tubes M8, M9, M10 and M11 can shield the influence of power supply voltage jitter on related branches, so that the source voltage of MOS tube M9 and the source voltage of MOS tube M11 always remain stable, thereby improving the accuracy of the output voltage of port VPES.

[0045] The load circuit 122 includes a MOS transistor M7 , a MOS transistor M12 , a MOS transistor M13 , and a port VPES.

[0046] The drain of MOS tube M7 is connected to the source of MOS tube M9, the gate of MOS tube M7 is connected to the drain of MOS tube M7, and the source of MOS tube M7 is grounded. The drain of MOS tube M12 is connected to the source of MOS tube M11, the gate of MOS tube M12 is connected to the drain of MOS tube M12, and the source of MOS tube M12 is connected to the drain of MOS tube M13. The drain of MOS tube M13 is connected to the source of MOS tube M12, the gate of MOS tube M13 is connected to the gate of MOS tube M7, and the source of MOS tube M13 is connected to port VPES.

[0047] MOS tube M7, MOS tube M12, and MOS tube M13 are connected to form the output load of the bias voltage circuit 12. High-frequency electromagnetic interference in the environment will increase the gate voltage of MOS tube M9, thereby reducing the gate voltage of MOS tube M13, causing MOS tube M13 and MOS tube M7 to be turned off, and the branch current where the drain and source of MOS tube M13 are located is zero, and the bias voltage circuit 12 stops working. The anti-interference circuit 11 is connected to the source of MOS tube M9 through the source of MOS tube M6, and outputs the anti-interference voltage Vgs to the source of MOS tube M9, so that the source voltage of MOS tube M9 increases, and then MOS tube M13 and MOS tube M7 are turned on. After MOS tube M13 and MOS tube M7 are turned on, the gate voltage of MOS tube M9 can be pulled down, thereby restoring the normal operation of the bias voltage circuit 12. The bias voltage circuit 12 outputs a suitable bias voltage Vbe to the voltage stabilizing output circuit 2 through the port VPES.

[0048] MOS tube M18 and MOS tube M10 have the same size ratio, and MOS tube M18 and MOS tube M10 have the same size ratio. The channel width of MOS tube M13 is 4 times that of MOS tube M7. Based on the bias voltage circuit connection structure, the expression of the gate-source voltage Vgs13 of MOS tube M13 is shown in formula (1).

[0049]

[0050] In formula (1), Ibe is the current flowing through the drain and source of MOS tube M13, that is, the bias current output by the circuit. B13 is the width-to-length ratio of the conductive channel of MOS tube M13, and Vth13 is the threshold voltage of MOS tube M13. Similarly, the expression of the gate-source voltage Vgs7 of MOS tube M7 is shown in formula (2).

[0051]

[0052] In formula (2), Ibe is the bias current output by the circuit. K is the size ratio of MOS tube M13 and M7, and in this example, K=4. B7 is the width-to-length ratio of the conductive channel of MOS tube M7, and Vth7 is the threshold voltage of MOS tube M7.

[0053] The bias current Ibe output by the circuit can be deduced from formula (1) and formula (2), and its expression is shown in formula (3).

[0054]

[0055] In formula (3), R is the on-resistance of the MOS tube M13, B13 is the width-to-length ratio of the conductive channel of the MOS tube M13, and K is the size ratio of the MOS tube M13 to M7. In this example, K=4.

[0056] like Figure 3 As shown, the gain circuit 21 includes a coupling circuit 211 and a constant current region circuit 212

[0057] The coupling circuit 211 is connected to the constant current region circuit 212, and the constant current region circuit 212 enables the MOS tube in the coupling circuit 211 to work in the constant current region by providing a bias current. The coupling circuit 211 generates and outputs a high gain voltage Veh to the amplifying buffer circuit 22, thereby increasing the power supply rejection ratio of the voltage stabilizing output circuit 2, thereby improving the system output accuracy. The coupling circuit 211 participates in the generation of a low temperature coefficient reference voltage by connecting to the merging circuit 23.

[0058] The coupling circuit 211 includes a MOS transistor M14 , a MOS transistor M15 , a MOS transistor M17 , and a MOS transistor M18 .

[0059] The source of MOS tube M14 is connected to the power supply VDD, the gate of MOS tube M14 is connected to the gate of MOS tube M17, and the drain of MOS tube M14 is connected to the drain of MOS tube M15. The drain of MOS tube M15 is connected to the gate of MOS tube M14, the gate of MOS tube M15 is connected to the drain of MOS tube M28, and the source of MOS tube M15 is connected to the drain of MOS tube M16. The source of MOS tube M17 is connected to the source of MOS tube M14, the gate of MOS tube M17 is connected to the drain of MOS tube M15, and the drain of MOS tube M17 is connected to the drain of MOS tube M18. The drain of MOS tube M18 is connected to the drain of MOS tube M17, the gate of MOS tube M18 is connected to the drain of MOS tube M27, and the source of MOS tube M18 is connected to the drain of MOS tube M19.

[0060] The interconnected structure of the MOS transistor M14 and the MOS transistor M17 has a current source load characteristic, and makes the drain voltage difference of the MOS transistor M15 and the MOS transistor M18 zero, thereby ensuring the output accuracy of the gain circuit 21.

[0061] MOS transistor M15 and MOS transistor M18 have the same conductive channel width-to-length ratio, and based on the related connection between MOS transistor M15 and MOS transistor M18, a source coupling structure is formed. The voltage Veh of the node connected by the drain of MOS transistor M17 and the drain of MOS transistor M18 has a large gain, and is transmitted to the amplification buffer circuit 22 through the connection between the drain of MOS transistor M17 and the gate of MOS transistor M20. The gate of MOS transistor M15 and the gate of M18 are respectively connected to the merging circuit 23 to participate in the generation of the low temperature coefficient reference voltage.

[0062] The constant current region circuit 212 includes a MOS transistor M19, a MOS transistor M16, and a port VCLS.

[0063] The drain of MOS tube M16 is connected to the source of MOS tube M19, the gate of MOS tube M16 is connected to port VCLS, and the source of MOS tube M16 is grounded. The drain of MOS tube M19 is connected to the source of MOS tube M18, the gate of MOS tube M19 is connected to the drain of MOS tube M19, and the source of MOS tube M19 is connected to the source of MOS tube M15.

[0064] The gate of the MOS transistor M16 is connected to the port VCLS, and the bias voltage Vbe is obtained through the connection between the port VCLS and the port VPES. Based on the relevant circuit connection structure of the MOS transistor M16 and the MOS transistor M19, the constant current region circuit 212 provides bias current for the MOS transistor M15 and the MOS transistor M18, so that the MOS transistor M15 and the MOS transistor M18 work in the constant current region.

[0065] like Figure 3 As shown, the amplifying and buffering circuit 22 includes a frequency compensation circuit 221 and a common source amplifying circuit 222 .

[0066] The frequency compensation circuit 221 is connected to the common source amplifier circuit 222. The frequency compensation circuit 221 generates a system main pole to maintain the stable operation of the common source amplifier circuit 222 in the high frequency band. The common source amplifier circuit 222 outputs a voltage Vpr with high gain and high swing to the merging circuit 23.

[0067] The frequency compensation circuit 221 includes a resistor R1 , a capacitor C1 , a MOS transistor M20 , a MOS transistor M21 , and a MOS transistor M24 .

[0068] The source of MOS tube M20 is connected to the source of MOS tube M17, the gate of MOS tube M20 is connected to the drain of MOS tube M17, and the drain of MOS tube M20 is connected to the drain of MOS tube M21. The upper end of resistor R1 is connected to the lower end of capacitor C1, and the lower end of resistor R1 is connected to the drain of MOS tube M18. The upper end of capacitor C1 is connected to the drain of MOS tube M20, and the lower end of capacitor C1 is connected to the upper end of resistor R1. The drain of MOS tube M21 is connected to the drain of MOS tube M20, the gate of MOS tube M21 is connected to the gate of MOS tube M24, and the source of MOS tube M21 is connected to the source of MOS tube M22. The drain of MOS tube M24 is connected to the source of MOS tube M20, the gate of MOS tube M24 is connected to the drain of MOS tube M21, and the source of MOS tube M24 is connected to the source of MOS tube M25.

[0069] The resistor R1, the capacitor C1, the MOS tube M20, the MOS tube M21 and the MOS tube M24 are connected to form a frequency compensation circuit, which generates the main pole of the amplifier buffer circuit 22. The frequency compensation circuit enables the amplifier buffer circuit 22 to maintain stable operation in both low-frequency and high-frequency ranges, and enables the entire circuit system including the bias circuit 1 and the voltage-stabilizing output circuit 2 to have a phase margin of 70°. When the system phase shift reaches 180°, the system gain is less than -20dB. In the frequency range of 0 to 10KHz, the system open-loop gain is 50dB, which ensures the stable operation of the system and meets the system design indicators.

[0070] The common-source amplifier circuit 222 includes a MOS transistor M22 , a MOS transistor M23 , a MOS transistor M25 , and a MOS transistor M26 .

[0071] The source of MOS tube M22 is connected to the source of MOS tube M21, the gate of MOS tube M22 is connected to the gate of MOS tube M25, and the drain of MOS tube M22 is connected to the drain of MOS tube M23. The drain of MOS tube M23 is connected to the gate of MOS tube M22, the gate of MOS tube M23 is connected to the gate of MOS tube M16, and the source of MOS tube M23 is grounded. The source of MOS tube M25 is connected to the gate of MOS tube M27, the gate of MOS tube M25 is connected to the drain of MOS tube M22, and the drain of MOS tube M25 is connected to the drain of MOS tube M26. The drain of MOS tube M26 is connected to the drain of MOS tube M25, the gate of MOS tube M26 is connected to the drain of MOS tube M26, and the source of MOS tube M26 is grounded.

[0072] The circuit connection structure of the MOS transistor M22, the MOS transistor M23, the MOS transistor M25, and the MOS transistor M26 has a common source amplification function and a small output impedance, so that the voltage Vpr at the node where the source of the MOS transistor M24 and the source of the MOS transistor M25 are connected has a large voltage amplitude. The gate of the MOS transistor M27 is connected to the source of the MOS transistor M25, and the voltage Vpr is output to the merging circuit 23 to increase the gain and voltage swing of the reference voltage Vrt output by the merging circuit 23. Based on the circuit connection structure of the common source amplifier circuit 222, the expression of the voltage Vpr is shown in formula (4).

[0073]

[0074] In formula (4), Vdd is the power supply voltage, Ia is the branch current where the gate source of the MOS tube M24 is located, u is the electron mobility, Cox is the gate oxide layer capacitance of the MOS tube, B25 is the width-to-length ratio of the conductive channel of the MOS tube M25, B26 is the width-to-length ratio of the conductive channel of the MOS tube M26, Vth25 is the threshold voltage of the MOS tube M25, and Vth26 is the threshold voltage of the MOS tube M26.

[0075] like Figure 3 As shown, the merging circuit 23 includes an input circuit 231 , a branch current circuit 232 and an output circuit 233 .

[0076] The input circuit 231 is connected to the branch current circuit 232, and the input circuit 231 provides a working voltage to the branch current circuit 232 so that it generates branch currents Ib and Ic respectively. The input circuit 231 is connected to the output circuit 233, and the input circuit 231 copies the currents Ib and Ic in the branch current circuit 232 to the output circuit 233 to combine and generate the current Io. The output circuit 233 generates a reference voltage Vrt based on the current Io.

[0077] The input circuit 231 includes a MOS transistor M27 , a MOS transistor M28 , and a MOS transistor M29 .

[0078] The source of MOS tube M27 is connected to the power supply VDD, the gate of MOS tube M27 is connected to the gate of MOS tube M28, and the drain of MOS tube M27 is connected to the emitter of triode Q1. The source of MOS tube M28 is connected to the source of MOS tube M27, the gate of MOS tube M28 is connected to the gate of MOS tube M29, and the drain of MOS tube M28 is connected to the upper end of resistor R3. The source of MOS tube M29 is connected to the source of MOS tube M28, the gate of MOS tube M29 is connected to the gate of MOS tube M27, and the drain of MOS tube M29 is connected to the drain of MOS tube M30.

[0079] MOS transistor M27, MOS transistor M28 and MOS transistor M29 are connected to form an input circuit 231, which receives a voltage Vpr and copies the current Ib of the branch where the drain and source of MOS transistor M27 are located, and the current Ic of the branch where the drain and source of MOS transistor M28 are located, to the branch where the drain and source of MOS transistor M29 are located. The current Ib and the current Ic are combined in the branch where the drain and source of MOS transistor M29 are located to form an output current Io.

[0080] The branch current circuit 232 includes a resistor R2 , a resistor R3 , a resistor R4 , a transistor Q1 , a transistor Q2 , a transistor Q3 , and a transistor Q4 .

[0081] The upper end of the resistor R2 is connected to the drain of the MOS tube M27, and the lower end of the resistor R2 is connected to the base of the transistor Q1. The emitter of the transistor Q1 is connected to the drain of the MOS tube M27, the base of the transistor Q1 is connected to the collector of the transistor Q1, and the collector of the transistor Q1 is connected to the emitter of the transistor Q2. The emitter of the transistor Q2 is connected to the lower end of the resistor R2, the base of the transistor Q2 is connected to the collector of the transistor Q2, and the collector of the transistor Q2 is grounded. The upper end of the resistor R3 is connected to the drain of the MOS tube M28, and the lower end of the resistor R3 is connected to the emitter of the transistor Q3. The upper end of the resistor R4 is connected to the upper end of the resistor R3, and the lower end of the resistor R4 is connected to the base of the transistor Q3. The emitter of the transistor Q3 is connected to the lower end of the resistor R3, the base of the transistor Q3 is connected to the lower end of the resistor R4, and the collector of the transistor Q3 is connected to the emitter of the transistor Q4. The emitter of the transistor Q4 is connected to the collector of the transistor Q3 , the base of the transistor Q4 is connected to the collector of the transistor Q4 , and the collector of the transistor Q4 is grounded.

[0082] The connection structure of the resistor R2, the transistor Q1 and the transistor Q2 is mainly used to generate the branch current Ib. The expression of the current Ib is shown in formula (5).

[0083]

[0084] In formula (5), Vd27 is the drain voltage of MOS tube M27, Vqe1 is the collector-emitter voltage of transistor Q1, and r2 is the resistance value of resistor R2.

[0085] The connection structure of the resistor R3, the resistor R4, the transistor Q3, and the transistor Q4 is mainly used to generate a branch current Ic. The expression of the current Ic is shown in formula (6).

[0086]

[0087] In formula (6), Vd28 is the drain voltage of MOS tube M28, Vqe3 is the collector-emitter voltage of transistor Q3, r3 is the resistance value of resistor R3, and r4 is the resistance value of resistor R4.

[0088] The output circuit 233 includes a MOS transistor M30 , a MOS transistor M31 , and a port VOUT.

[0089] The drain of MOS tube M30 is connected to port VOUT, the gate of MOS tube M30 is connected to the drain of MOS tube M30, the source of MOS tube M30 is connected to the drain of MOS tube M31, the drain of MOS tube M31 is connected to the source of MOS tube M30, the gate of MOS tube M31 is connected to the gate of MOS tube M30, and the source of MOS tube M31 is grounded.

[0090] The circuit connection structure of the MOS transistor M30 and the MOS transistor M31 constitutes an output load, whose impedance is Rn. The current Io is the sum of the current Ib and the current Ic, and the system output reference voltage Vrt is the product of the current Io and the impedance Rn. Therefore, the expression of the system output reference voltage Vrt is shown in formula (7).

[0091]

[0092] In formula (7), rn is the impedance value of the impedance Rn, r4 is the resistance value of the resistor R4, Vqe1 is the collector-emitter voltage of the transistor Q1, r3 is the resistance value of R3, Vt is the thermal voltage, and LnN is the subthreshold slope factor of the MOS tube.

[0093] In formula (7), Vqe1 has a negative temperature coefficient, while (r4 / r3×Vt×LnN) has a positive temperature coefficient. The two terms cancel each other out, so that the reference voltage Vrt has a temperature coefficient close to zero. Since the reference voltage Vrt is generated based on the voltage Vqr, it has a lower temperature coefficient while having higher accuracy and a larger output voltage swing. The reference voltage Vrt is output through the port VOUT.

Claims

1. A high-precision reference voltage circuit, characterized in that: It comprises a bias circuit (1) and a voltage-stabilizing output circuit (2); The bias circuit (1) is connected to the voltage stabilizing output circuit (2), and the bias circuit (1) outputs a precise and stable bias voltage (Vbe) to the voltage stabilizing output circuit (2); The bias circuit (1) includes an anti-interference circuit, so that the bias circuit (1) can work normally in a high-frequency electromagnetic interference environment; The bias circuit (1) can effectively shield the influence of power supply voltage jitter based on its circuit structure setting, so that the output bias voltage is stable and unchanged; The voltage stabilizing output circuit (2) includes a gain circuit, so that the system has a higher gain and thus has a higher power supply rejection ratio; The amplifying buffer circuit in the voltage-stabilizing output circuit (2) has a frequency compensation function, so that the system can maintain stable operation in both low-frequency and high-frequency ranges; The merging circuit in the voltage-stabilizing output circuit (2) is mainly used to generate a reference voltage (Vrt) with a relatively low temperature coefficient.

2. A high-precision reference voltage circuit according to claim 1, characterized in that: The bias circuit (1) comprises an anti-interference circuit (11) and a bias voltage circuit (12); The anti-interference circuit (11) is connected to the bias voltage circuit (12), and the anti-interference circuit (11) provides an anti-interference voltage (Vgs) to the bias voltage circuit (12), so that the bias voltage circuit (12) can work normally in a high-frequency electromagnetic interference environment; The bias voltage circuit (12) outputs a precise and stable bias voltage (Vbe) to the voltage stabilization output circuit (2).

3. A high-precision reference voltage circuit according to claim 1, characterized in that: The voltage-stabilizing output circuit (2) comprises a gain circuit (21), an amplifying buffer circuit (22) and a merging circuit (23); The gain circuit (21) is connected to the amplifying buffer circuit (22), and the gain circuit (21) outputs a high gain voltage (Veh) to the amplifying buffer circuit (22); The amplifying buffer circuit (22) can stably output a high-gain voltage in both low-frequency and high-frequency ranges through frequency compensation, and make the output voltage have a large voltage swing; The amplifying buffer circuit (22) is connected to the merging circuit (23). The amplifying buffer circuit (22) outputs a voltage (Vpr) to the merging circuit (23). The merging circuit (23) processes the voltage (Vpr) and outputs a reference voltage (Vrt) with a relatively low temperature coefficient.

4. A high-precision reference voltage circuit according to claim 2, characterized in that: The anti-interference circuit (11) comprises a self-bias power supply circuit (111) and a current limiting output circuit (112); The self-bias power supply circuit (111) is connected to the current limiting output circuit (112), and the self-bias power supply circuit (111) outputs an anti-interference voltage (Vgs) to the current limiting output circuit (112).

5. A high-precision reference voltage circuit according to claim 2, characterized in that: The bias voltage circuit (12) comprises a shielding circuit (121) and a load circuit (122); The shielding circuit (121) is connected to the load circuit (122), and the shielding circuit (121) outputs a precise and stable bias voltage (Vbe) through the load circuit (122).

6. A high-precision reference voltage circuit according to claim 3, characterized in that: The gain circuit (21) comprises a coupling circuit (211) and a constant current region circuit (212); The coupling circuit (211) is connected to the constant current region circuit (212), and the constant current region circuit (212) enables the MOS tube in the coupling circuit (211) to operate in the constant current region by providing a bias current; The coupling circuit (211) generates and outputs a high-gain voltage (Veh) to the amplifying buffer circuit (22), thereby increasing the power supply rejection ratio of the voltage-stabilizing output circuit (2), thereby improving the output accuracy of the system; The coupling circuit (211) participates in the generation of a low temperature coefficient reference voltage by being connected to the combining circuit (23).

7. A high-precision reference voltage circuit according to claim 3, characterized in that: The amplifying and buffering circuit (22) comprises a frequency compensation circuit (221) and a common source amplifying circuit (222); The frequency compensation circuit (221) is connected to the common source amplifier circuit (222), and the frequency compensation circuit (221) generates a system main pole to maintain stable operation of the common source amplifier circuit (222) in a high frequency band; The common source amplifier circuit (222) outputs a voltage (Vpr) having a high gain and a high swing to the combining circuit (23).

8. A high-precision reference voltage circuit according to claim 3, characterized in that: The merging circuit (23) comprises an input circuit (231), a branch current circuit (232) and an output circuit (233); The input circuit (231) is connected to the branch current circuit (232), and the input circuit (231) provides a working voltage for the branch current circuit (232), so that the branch current circuit (232) generates branch currents (Ib) and (Ic) respectively; The input circuit (231) is connected to the output circuit (233), and the input circuit (231) copies the currents (Ib) and (Ic) in the branch current circuit (232) to the output circuit (233) to combine and generate the current (Io); The output circuit (233) generates a reference voltage (Vrt) based on the current (Io).

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