Context switching method and device and electronic equipment

Abstract

The invention provides a context switching method and device and electronic equipment, and the method comprises the steps: responding to a received context switching instruction of a program, and detecting whether the program has an uncompleted first synchronization operation or not in a pause state of a processor; the processor comprises a plurality of computing cores and a hardware synchronization unit; in response to detecting that the first synchronization operation which is not completed exists, repeatedly executing the following first operation until the first synchronization operation is completed: continuing to execute a program instruction of the program through the computing core; if a subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, executing the first synchronization operation according to the synchronization instruction; and executing a context switching operation when the first synchronization operation is in a completed state. According to the context switching completed by the scheme, when the program is operated again according to the context, the program can be operated continuously from the pause position accurately.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a context switching method, device and electronic device. Background Art

[0002] In order to improve the computing power of the processor, multiple computing cores can be set in the processor. These computing cores can perform computing tasks in parallel and independently. However, when computing tasks need to cooperate with each other, the computing tasks of different computing cores need to be synchronized. Usually, the synchronization between computing cores can be completed by software, but with the improvement of processor technology and the increase in user requirements for processor computing power, more and more functions that could have been completed by software are now transferred to the processor to be executed by hardware units. Accordingly, a hardware synchronization unit is set in the processor to achieve synchronization between different computing cores inside the processor.

[0003] However, when performing context switching on a processor with a hardware synchronization unit, it is difficult to save and switch contexts because the context switching timing is not fixed or the processor may not be able to achieve steady-state suspension. Summary of the invention

[0004] The present disclosure provides a context switching method, device and electronic device.

[0005] According to a first aspect of the present disclosure, a context switching method is provided, the method comprising: in response to receiving a context switching instruction of a program, detecting whether the program currently has an unfinished first synchronization operation in a paused state of a processor; the processor comprising a plurality of computing cores and a hardware synchronization unit; in response to detecting that there is an unfinished first synchronization operation, repeatedly performing the following first operation until the synchronization operation is completed: continuing to execute program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, performing the first synchronization operation according to the synchronization instruction; and performing a context switching operation when the first synchronization operation is in a completed state.

[0006] According to a second aspect of the present disclosure, a context switching device is provided, which includes: a detection unit, which is used to detect whether the program currently has an unfinished first synchronization operation in a paused state of a processor in response to receiving a context switching instruction of a program; the processor includes multiple computing cores and a hardware synchronization unit; an execution unit, which is used to repeatedly perform the following first operation in response to determining that the hardware synchronization unit only supports read data operations and in response to detecting an unfinished first synchronization operation until the first synchronization operation is completed: continue to execute the program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, execute the first synchronization operation according to the synchronization instruction; a switching unit, which is used to perform a context switching operation when the first synchronization operation is in a completed state.

[0007] According to a third aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method provided in the first aspect.

[0008] According to a fourth aspect of the present disclosure, a computer program product is provided, comprising: a computer program, wherein the computer program is stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program so that the electronic device executes the method described in the first aspect.

[0009] According to the scheme disclosed in the present invention, in response to receiving a context switch instruction of a program, it is detected in a paused state of a processor whether the program currently has an unfinished first synchronization operation; the processor includes multiple computing cores and a hardware synchronization unit; in response to detecting that there is an unfinished first synchronization operation, the following first operation is repeatedly performed until the synchronization operation is completed: the program instructions of the program are continued to be executed by the computing core; if the subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, the first synchronization operation is executed according to the synchronization instruction; when the first synchronization operation is in a completed state, a context switch operation is performed, thereby realizing that when the context is switched, the context switch is performed when the unfinished first synchronization operation is completed. When the first synchronization operation is completed, there is no unfinished existing synchronization operation, and it can be considered that the operation of the program is in a steady-state pause at this time. When the context switch is completed at this time, when the above-mentioned program instructions are re-run according to the context, it can be accurately continued from the pause point.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0012] Figure 1 It is a schematic diagram of a structural diagram of a multi-computing core processor provided by the present disclosure;

[0013] Figure 2 is a schematic diagram of a structure of a computing core provided by the present disclosure;

[0014] Figure 3 is a schematic flow chart of an embodiment of the context switching method disclosed in the present invention;

[0015] Figure 4 is a schematic flow chart of another embodiment of the context switching method disclosed herein;

[0016] Figure 5 is a schematic flow chart of another embodiment of the context switching method of the present disclosure;

[0017] Figure 6 is a principle flow chart of the context switching method disclosed in the present invention;

[0018] Figure 7 is a principle flow chart of the context switching method disclosed in the present invention;

[0019] Figure 8 is a schematic structural diagram of the context switching device disclosed in the present invention;

[0020] Fig. 9 is a schematic block diagram of an example electronic device that can be used to implement embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] Computing power is the core indicator of artificial intelligence processors. Computing power refers to computing power, specifically the amount of computing per unit time. Artificial intelligence processors usually include multiple computing cores, which can execute the same or different program instructions at the same time. In an artificial intelligence processor, each computing core can independently perform computing tasks. When tasks need to collaborate with each other, such as the need to collaborate with each other to implement artificial intelligence training tasks and / or reasoning tasks, the tasks performed by different computing cores need to be synchronized during the collaboration process. The tasks that need to be synchronized here can be regarded as synchronous operations. Synchronous operations refer to: a sequence of operations that have a fixed timing relationship with each other, and subsequent operations cannot be performed before the previous operations are completed.

[0023] In the related art, a memory synchronization method is used to achieve synchronization between different computing tasks. Specifically, in this synchronization technology, a synchronous memory space is allocated to each computing task respectively. When the computing task of a computing core reaches the synchronization point, the computing core can send a set signal to the synchronous memory space corresponding to the computing task. The synchronous memory space can write a preset synchronization identifier in the synchronous memory space according to the set signal. The preset computing core can poll the synchronization identifiers of each synchronous memory space to determine whether the computing cores that need to cooperate have reached the synchronization point. When some computing cores have not reached the synchronization point, the computing cores that have reached the synchronization point are in a waiting state. After determining that the computing cores that need to cooperate have reached the synchronization point, the preset core can perform corresponding operations on the intermediate results of each computing core. In addition, the above-mentioned computing cores can start subsequent computing tasks.

[0024] In this method, since it is necessary to write the synchronization flag into the memory synchronization space and then read the synchronization flag in the memory synchronization space to determine whether the computing cores that need to cooperate have reached the synchronization point, it takes a long time and, to some extent, affects the computing power of the multi-computing core processor.

[0025] In order to further improve the computing power of the multi-computing core processor, a hardware synchronization unit can be set in the multi-computing core processor. The hardware synchronization unit can use the registers in the multi-computing core processor to save the synchronization identifier corresponding to the synchronization operation. Since the hardware synchronization unit uses the register space inside the multi-computing core processor, the access and polling speed is faster, which can improve the synchronization performance and efficiency, thereby improving the computing power of the multi-computing core processor.

[0026] During the process of program development, debugging, operation and maintenance, programs running on multi-core processors not only need to be attached and debugged, but also need to be hot migrated and hot switched. These requirements require pausing the running program, saving the program context, and then importing the context into the idle processor to continue running the previously paused program, which is the program context switch.

[0027] When an artificial intelligence processor uses a hardware synchronization unit, it becomes difficult to save and switch program contexts due to the following reasons: on the one hand, the timing of context switching is not fixed, and only part of the synchronization information may be saved in the hardware synchronization unit. After the program is switched out, the information is incomplete, and it is necessary to comprehensively consider the software execution status and hardware information for context switching; on the other hand, the processor only provides a small number of read data interfaces for the hardware synchronization unit, and the reading and writing of the hardware synchronization unit cannot be realized.

[0028] In order to achieve a relatively smooth and complete context switch for program instructions with synchronization operations when the above-mentioned processor has only a small number of data reading interfaces of the hardware synchronization unit, the context switching method provided by the present disclosure, when switching the context of the program instruction, if there is an unfinished first synchronization operation, continues to run the computing core of the unfinished synchronization operation until the first synchronization operation is completed, so that the scheme can execute the synchronization operations that have not been executed in a step-by-step manner. The switching operation can be executed when the unfinished synchronization operation is completed. Therefore, under the premise that the processor has a small number of data reading interfaces of the hardware synchronization unit, a relatively complete context switch can be achieved.

[0029] Please refer to Figure 1 , Figure 1 A schematic diagram of a multi-computing core processor provided by the present disclosure. Figure 1 As shown, the processor 10 includes multiple computing cores such as computing core 1, computing core 2, computing core 3 and computing core 4. In addition, the processor also includes a hardware synchronization unit 101. Each computing core can communicate with the hardware synchronization unit 101. That is, the processor 10 that runs the program is a multi-computing core processor. The processor 10 can exchange information with the memory 102 and obtain program instructions from the memory. Optionally, the above-mentioned multi-computing core processor can be a graphics processing unit (GPU) or an intelligent processor, which is not specifically limited here.

[0030] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of the computing core provided by the present disclosure. Figure 2As shown, the computing core 20 may include an instruction queue 201 and an instruction execution unit 202. For the computing core, the multi-computing core processor can distribute the instruction stream extracted from the memory to each computing core. After the computing core receives the above-mentioned instruction stream assigned to itself, it can store these instruction streams in the instruction queue. The instruction execution unit 202 can extract instructions from the instruction queue 201 and execute them. When the instruction execution unit executes a synchronization instruction, it can send synchronization information 203 to the hardware synchronization unit.

[0031] The above-mentioned multi-computing core processor can form a heterogeneous computing system with a general-purpose processor (such as a central processing unit CPU), wherein the multi-computing core processor and the general-purpose processor have different instruction set architectures, and the general-purpose processor can execute the following context switching method to implement context switching of the multi-computing core processor. And the execution subject of the context switching method disclosed in the present invention can be a general-purpose processor.

[0032] Please refer to Figure 3 , which shows a schematic flow chart of an embodiment of the context switching method of the present disclosure. Figure 3 As shown, the context switching method includes the following steps:

[0033] S301: In response to receiving a context switch instruction of a program, detecting whether the program currently has an unfinished first synchronization operation in a paused state of a processor; the processor includes multiple computing cores and a hardware synchronization unit.

[0034] In this embodiment, the execution subject of the context switching method may be a central processing unit (CPU) running in the terminal device. The processor running the program may be, for example, an artificial intelligence processor. The processor running the program may be a multi-computing core processor, including multiple computing cores and a hardware synchronization unit, such as Figure 1 shown.

[0035] During the execution of a program, a context switch may occur. The context switch instruction may be a switch instruction generated when a takeover or debugging requirement is received, or a switch instruction generated when a hot migration or hot switching requirement occurs.

[0036] After receiving the context switch instruction, the execution subject may send a pause instruction to each computing core of the multi-computing core processor, and wait for each computing core to run to a pause state. In the pause state, each computing core stops fetching instructions.

[0037] When a multi-computing core processor is in the pause state, the instruction queue in the computing core can only be in two states: idle state and non-idle state. The idle state means that all instructions in the instruction queue have been executed. The non-idle state means that the instruction execution unit is blocked by the synchronization instruction, resulting in the inability to continue to execute subsequent instructions. The blocked instructions in the instruction queue can only be executed after the synchronization operation corresponding to the synchronization instruction is completed.

[0038] If the instruction queue of a computing core is in a non-idle state, correspondingly, there are instructions of the first synchronization operation that have not been completed. These unfinished instructions of the first synchronization operation may need to be executed by the computing core, or may need to be executed by other computing cores. For example, the computing core that is currently in an idle state obtains the unfinished instructions of the first synchronization operation from the memory and executes them.

[0039] The above-mentioned multiple computing cores in the processor can execute the program instructions of the above-mentioned program. The program here can be a program for completing various tasks. Schematically, the above-mentioned program can be a program for completing reasoning tasks or training tasks in artificial intelligence. The above-mentioned program may include multiple program instructions, and the multiple program instructions can complete the corresponding tasks. The above-mentioned task can be divided into multiple subtasks. There is a strict execution order between different subtasks. In addition, the subtasks can also be processed collaboratively by multiple computing cores.

[0040] When a multi-computing core processor executes the same program, multiple computing cores in the multi-computing core processor will cooperate with each other to complete the task of the program. In order to ensure the calculation correctness of multiple computing cores, multiple computing cores need synchronization instructions. The operating system or processor can pre-set synchronization instructions in the program instructions. The synchronization instruction includes an identifier of a synchronization event generated according to the synchronization instruction, which is used to indicate the identifier of the computing core involved in the synchronization event and the synchronization range corresponding to each computing core.

[0041] When a multi-computing core processor extracts instructions from the memory and distributes them to each computing core, it will also send synchronization instructions to the computing core. When the computing core executes the synchronization instruction, it can send a synchronization request to the hardware synchronization unit according to the synchronization instruction, and the hardware synchronization unit can create a synchronization event according to the synchronization request. The above synchronization request may include the identifier of the synchronization event to be created, the identifier of the computing core involved, and the synchronization range corresponding to each computing core. The synchronization range corresponding to each different computing core indicated by each synchronization instruction can be regarded as a synchronization operation. The synchronization operation can also be a separate synchronization task.

[0042] The instruction corresponding to the first synchronization operation may be a task instruction indicated by a synchronization instruction that has been sent to a computing core and at least one computing core has sent a synchronization request to a hardware synchronization unit.

[0043] After each computing core executes multiple instructions within the synchronization range indicated by the synchronization instruction, the computing core may send synchronization information indicating that the instructions within the synchronization range have been executed to the hardware synchronization unit, and the synchronization information includes a computing core identifier. After receiving the synchronization information, the hardware synchronization unit may determine whether the synchronization condition is met according to the synchronization request. If the synchronization condition is not met, the hardware synchronization unit may record the received synchronization information, or record the identifier information of the computing core that has completed the instructions within the synchronization range.

[0044] The synchronization condition is that the hardware synchronization unit receives synchronization information sent by all computing cores indicated by the synchronization request. After the hardware synchronization unit determines that the synchronization request meets the synchronization condition, it can clear the synchronization information and the corresponding synchronization request information.

[0045] In some application scenarios, for some synchronization instructions of synchronization modes (such as synchronization instructions of consumer-end synchronization mode), when the computing core executes the synchronization instruction, it is necessary to block the execution of subsequent instructions in the instruction stream where the synchronization instruction is located in the computing core, until other computing cores associated with the synchronization instruction have executed the preceding instructions, and then the computing core executes subsequent instructions.

[0046] In some application scenarios, for some synchronization instructions of synchronization modes (such as synchronization instructions of production-end synchronization mode), when a computing core executes the synchronization instruction, it needs to wait for the execution of the previous instructions in the instruction stream where the synchronization instruction is located in the computing core to be completed, and then other computing cores associated with the synchronization instruction can execute subsequent instructions. For these synchronization instructions, before the above-mentioned previous instructions of the computing core are executed, the instructions within the synchronization range indicated by the synchronization instruction in the instruction queues of other computing cores are in a blocked state.

[0047] In some application scenarios, instructions of the same subtask executed on different computing cores may have corresponding synchronization instructions.

[0048] In these application scenarios, when a computing core executes an instruction of a subtask and reaches a synchronization instruction corresponding to the subtask, synchronization information can be sent to the hardware synchronization unit. The synchronization information can include a subtask (synchronization range) identifier. The identifier of the subtask is used to distinguish different subtasks.

[0049] As an illustration, if multiple instructions of a subtask can be respectively Figure 1The computing core 1, computing core 2, computing core 3 and computing core 4 shown in the figure are used for execution. In each computing core, a synchronization instruction can be set after the last instruction of the subtask in the computing core. The synchronization instruction is used to send synchronization information carrying the subtask identifier to the hardware synchronization unit. When each computing core executes the synchronization instruction corresponding to the subtask, it generates synchronization information carrying the subtask identifier according to the synchronization instruction, and sends the synchronization information to the hardware synchronization unit. The hardware synchronization unit can record the synchronization information sent by each computing core. When the hardware synchronization unit receives the synchronization information carrying the identifier of the above-mentioned subtask sent by the above-mentioned computing core 1, computing core 2, computing core 3 and computing core 4 respectively, it can be regarded as that the synchronization condition of the subtask (first synchronization operation) has been met. When the synchronization condition is met, the first synchronization operation is completed. Otherwise, the first synchronization operation corresponding to the subtask is not completed.

[0050] S302: In response to detecting an unfinished first synchronization operation, repeatedly executing the following first operation until the first synchronization operation is completed: continuing to execute program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, executing the first synchronization operation according to the synchronization instruction.

[0051] In this embodiment, the execution subject can read multiple synchronization information in the hardware synchronization unit, and determine the unfinished first synchronization operation based on the multiple synchronization information. Since the information in the hardware synchronization unit cannot be directly deleted and modified, and the information in the hardware synchronization unit may change during the context switching process, the context of the program is in a changing state when it is paused. When the synchronization information in the hardware synchronization unit indicates that there is an unfinished first synchronization operation, the context switching needs to wait until the first synchronization operation is completed before executing, in order to obtain a stable context state. In the stable context state, the context of the program switched to another processor can be executed normally.

[0052] In some embodiments, it can also be determined from the synchronization information which computing cores have not completed the first synchronization operation. In these embodiments, these computing cores that have not completed the first synchronization operation can be used as target computing cores, and the above-mentioned execution entity can promote the target computing cores to gradually execute their corresponding subsequent program instructions.

[0053] Multi-core processors include Figure 1The computing core 1, computing core 2, computing core 3 and computing core 4 shown are taken as examples. Each computing core can include an instruction queue and an instruction execution unit. The instruction queues corresponding to the computing cores 1, 2, 3 and 4 can store instruction streams extracted from the memory. The instruction execution unit in the computing core 1 can extract instructions from the instruction queue and execute the extracted instructions. When the instruction executed by the instruction execution unit is a synchronization instruction, the computing core 1 sends a synchronization request to the hardware synchronization unit (for example, a synchronization request sent by a synchronization instruction in the consumer-side synchronization mode). The synchronization request includes the identifier of subtask 1, as well as the identifiers of computing cores 2, 3 and 4. After issuing the synchronization request, the computing core 1 can be in a waiting state, that is, the subsequent instruction stream of the computing core 1 is blocked.

[0054] If context switching is performed at this time, it can be determined that the computing cores that have not completed the first synchronization operation are computing core 2, computing core 3, and computing core 4 according to the hardware request read from the hardware synchronization unit.

[0055] The first operation includes: computing core 2 , computing core 3 , and computing core 4 execute instructions in their respective instruction queues to execute subtask 1 (ie, the first synchronization operation).

[0056] A synchronization instruction may be set after the last instruction of subtask 1 in the instruction queue of each computing core. The synchronization instruction is used to send synchronization information that subtask 1 of the computing core has been completed to the hardware synchronization unit.

[0057] If, when executing the first operation, the instructions of computing core 2 execute the synchronization instructions after subtask 1, synchronization information is sent to the hardware synchronization unit. The hardware synchronization unit can determine that computing core 2 has completed its corresponding synchronization range. The hardware synchronization unit determines that computing core 3 and computing core 4 have not completed their respective corresponding subtasks 1 (synchronization range) based on the original synchronization request, and computing core 3 and computing core 4 can continue to execute the instructions of their respective corresponding subtasks 1. Until computing core 2, computing core 3 and computing core 4 have all completed subtask 1. The first synchronization operation is completed. The hardware synchronization unit sends the information that the first synchronization operation is completed to each computing core. After receiving the above-mentioned information that the first synchronization operation is completed, the subsequent instructions blocked in computing core 1 can continue to be executed.

[0058] It is understandable that if the number of the first synchronization operations is more than two, the context switch is performed after each of the first synchronization operations is completed.

[0059] After the processor is suspended and before the context is switched, for the target computing core that has not completed the first synchronization operation, the target computing core continues to execute each instruction in the instruction queue of the target computing core.

[0060] In some application scenarios, if during the first operation, each target computing core needs to fetch instructions that are not fetched into the instruction queue from the memory, the target computing core can fetch the program instructions corresponding to the target computing core from the memory one by one, and execute the above program instructions one by one.

[0061] The program instructions may include calculation instructions, control instructions, synchronization instructions, etc. When there is a synchronization instruction in the subsequent program instructions, the execution subject may determine whether to continue to execute the first operation according to the synchronization information generated by executing the synchronization instruction.

[0062] When the target computing core executes the synchronization instruction, if the hardware synchronization unit determines that the first synchronization operation is completed according to the synchronization information generated by the synchronization instruction, the target computing core determines not to continue to execute the first operation. If the hardware synchronization unit determines that the first synchronization operation is not completed according to the synchronization information generated by the target computing core executing the synchronization instruction, the first operation continues to be executed.

[0063] In some embodiments, the context switching method may further include the following sub-steps:

[0064] First, in response to detecting that an uncompleted first synchronization operation exists, unexecuted synchronization instructions in the program instructions are replaced with breakpoint instructions.

[0065] Secondly, based on the breakpoint instruction, the first operation is repeatedly executed.

[0066] In these embodiments, when a context switch of a program occurs, there may be program instructions temporarily stored in the instruction queue of the computing core that have not been executed due to being blocked. For the program instructions that have been loaded into the computing core and temporarily stored in the instruction queue, the above-mentioned execution subject can use the preset interface provided by the multi-core processor (for example, an interface for reading data from the processor) to export these blocked program instructions from the instruction queue of the computing core. The above-mentioned execution subject can replace the synchronization instructions in these exported program instructions with breakpoint instructions, and then the above-mentioned computing core loads these program instructions into the instruction queue of the computing core, so that the target computing core continues to execute these program instructions.

[0067] Since the above synchronization instruction is replaced by a breakpoint instruction, after the instruction execution unit of any computing core executes the breakpoint instruction, the computing core can send an interrupt message to the above execution subject according to the breakpoint instruction. After receiving the interrupt message, the above execution subject can judge whether the synchronization information generated by executing the synchronization instruction indicates to continue to execute the first synchronization operation according to the synchronization instruction corresponding to the current interrupt message.

[0068] Specifically, when the execution subject exports the unexecuted program instructions from the instruction queue of the computing core, the execution subject can also read the existing synchronization information in the hardware synchronization unit in the multi-core processor according to the preset interface. The execution subject can judge whether the first synchronization operation meets the synchronization condition according to the existing synchronization information in the synchronization unit and the synchronization information to be generated when the synchronization instruction corresponding to the execution breakpoint instruction is executed. If the first synchronization operation meets the synchronization condition, the first synchronization operation is completed and the first operation ends. Otherwise, the computing core continues to execute its corresponding program instruction until the first synchronization operation is completed.

[0069] S303: When the first synchronization operation is in a completed state, perform a context switching operation.

[0070] When the first synchronization operation is in a completed state, the execution subject may perform a context switching operation.

[0071] In this embodiment, in response to receiving a context switch instruction of a program, when the processor is in a paused state, it is detected whether the program currently has an unfinished first synchronization operation; the processor includes multiple computing cores and a hardware synchronization unit; in response to detecting that there is an unfinished first synchronization operation, the following first operation is repeatedly performed until the first synchronization operation is completed: the program instruction of the program continues to be executed by the computing core; if the subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, the first synchronization operation is executed according to the synchronization instruction; when the first synchronization operation is in a completed state, the context switch operation is performed, thereby realizing that when a context switch is required, the context switch is performed when the existing unfinished first synchronization operation is completed. When the first synchronization operation is completed, there is no unfinished synchronization operation in the object cut out from it, and it can be considered that the program is in a steady-state pause at this time. Completing the context switch at this time can enable the above program to be accurately continued from the pause point when it is re-run according to the context.

[0072] Please refer to Figure 4 , which shows a schematic flow chart of another embodiment of the context switching method of the present disclosure, such as Figure 4 As shown, the method comprises the following steps:

[0073] S401: In response to receiving a context switch instruction of a program, detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor; the processor includes multiple computing cores and a hardware synchronization unit; the context switch instruction is: a context switch instruction instructing to switch the context of the program from the processor to a storage medium.

[0074] In this embodiment, the execution subject may be a central processing unit (CPU) running in the terminal device.

[0075] The processor running the program may have multiple computing cores, including multiple computing cores and hardware synchronization units, that is, a multi-computing core processor. The hardware architecture of the multi-computing core processor can be as follows: Figure 1 and Figure 2 In this embodiment, the context switch instruction of the program is a context switch instruction for instructing the processor to switch the context of the program to the storage medium.

[0076] The storage medium here may be a storage medium on the terminal device on which the above-mentioned processor is arranged, such as a memory.

[0077] When receiving the context switch instruction, the execution subject may send a pause instruction to the multi-computing core processor. After receiving the pause instruction, the processor may temporarily stop the execution of the instruction and other operations.

[0078] The computing core may include an instruction queue and an execution unit. The instruction queue is used to temporarily store instruction streams obtained from the memory. The execution unit can extract instructions from the instruction queue and execute them.

[0079] The unexecuted synchronization instructions here may be all the synchronization instructions that have not been executed when the switching instruction is received.

[0080] All unexecuted synchronization instructions in the memory may be replaced with breakpoint instructions, and the instructions before and after the replacement may be recorded.

[0081] As an implementation manner, in these implementations, the above step S401 may include the following steps:

[0082] First, the synchronization information in the hardware synchronization unit is read.

[0083] Secondly, it is detected whether there is an unfinished first synchronization operation according to the synchronization information, wherein the synchronization information indicates a state of the first synchronization operation.

[0084] In these embodiments, the processor may provide a data reading hardware interface for reading data from the hardware synchronization unit. The execution subject may read synchronization information from the hardware synchronization unit through the interface. The synchronization information may be read into a memory.

[0085] The execution subject may determine which first synchronization operations have not been completed and the target computing cores of the instructions corresponding to the first synchronization operations that have not been completed based on the synchronization information read from the memory.

[0086] In some embodiments, the synchronization information in the synchronization unit may carry a subtask identifier and synchronization condition information. The CPU may determine which first synchronization operation the synchronization information corresponds to based on the subtask identifier of the synchronization information, and may also determine whether the first synchronization operation meets the synchronization condition based on the synchronization condition information.

[0087] The first synchronization operation here may include one unfinished synchronization operation or may include multiple unfinished synchronization operations.

[0088] S402: In response to detecting an unfinished first synchronization operation, the central processing unit repeatedly executes the following first operation until the first synchronization operation is completed: continue to execute the program instructions of the program through the computing core; if the subsequent synchronization instructions in the program instructions indicate to continue to execute the first synchronization operation, execute the first synchronization operation according to the synchronization instructions; if it is determined that the subsequent synchronization instructions in the program instructions indicate to add a second synchronization operation, record the newly added synchronization information indicating the second synchronization operation in the memory.

[0089] It should be noted that when the context switch instruction is a processor-switched instruction, Figure 1 The relevant specific implementation of steps S301 to S302 shown in the figure is still applicable in this embodiment. The same implementation is not repeated here.

[0090] and Figure 3 The difference is that if the CPU determines that the subsequent synchronization instruction indicates the creation of a new second synchronization operation, the execution subject may transfer the synchronization instruction to the storage medium for execution, and create synchronization information of the second synchronization operation in the storage medium. For example, the synchronization information of the newly created second synchronization operation is written to the storage medium in the form of a preset software data structure in the storage medium.

[0091] Specifically, all currently unexecuted synchronization instructions (including synchronization instructions that were originally in the instruction queue) can be replaced with breakpoint instructions. Then continue to advance the operation of the computing core. While the computing core continues to run, program instructions are taken from the instruction queue for execution. When the computing core takes a breakpoint instruction from the instruction queue, an interrupt is reported. The above-mentioned execution subject can receive the above-mentioned interruption and determine the synchronization instruction corresponding to the interruption. If the synchronization instruction indicates to continue to execute the first operation, the above-mentioned computing core is promoted to execute the synchronization instruction. If the synchronization instruction indicates to create a new second synchronization operation, the synchronization instruction is copied to the storage medium for execution, and the synchronization information corresponding to the second synchronization operation is stored in the storage medium.

[0092] When the synchronization information corresponding to the second synchronization operation is written into the storage medium, the information of the computing core corresponding to the second synchronization operation can be carried, so that when the context of the program is subsequently switched from the storage medium to the processor, it can be determined which computing cores have not completed the synchronization instruction according to the synchronization information of the second synchronization operation.

[0093] In the process of repeatedly executing the first synchronization operation, for the synchronization instruction of the newly added second synchronization operation, the synchronization instruction can be transferred to the storage medium for execution, and the synchronization information corresponding to the second synchronization operation is saved in the storage medium. The first operation is repeatedly executed until the first synchronization operation meets the synchronization condition, that is, the first synchronization operation is completed.

[0094] In the process of repeatedly executing the first operation, the instruction queue of each computing core gradually becomes idle. The instruction queue is not idle because it is blocked by the synchronization instruction. The synchronization instruction needs to wait for the execution of the synchronization instruction of other computing cores or instruction queues to be completed before it is executed. In the process of looping the first operation, the synchronization instruction that updates the first synchronization operation is executed in the processor, and the synchronization instruction that generates the new synchronization information of the second synchronization operation is transferred to the storage medium for execution. Therefore, the synchronization instruction that blocks the instruction in the instruction queue is gradually executed, so that the instructions in the instruction queue are gradually cleared.

[0095] As an illustrative illustration, Figure 3 , Figure 4 The method embodiment shown is also applicable to Figure 1 Hardware construction. Assume that computing cores 1, 2, and 3 respectively execute the computing instructions of subtasks A11, A12, and A13 of subtask A1. Synchronization instructions are respectively set after the computing instructions of subtasks A11, A12, and A13. In the hardware synchronization unit, corresponding registers A', B', and C' for temporarily storing synchronization request information can be allocated to the computing cores respectively.

[0096] After executing subtask A11, computing core 1 executes the corresponding synchronization instruction, and when executing the synchronization instruction, synchronization information S1 can be sent to register A' of the hardware synchronization unit. Computing core 2 executes the corresponding synchronization instruction after executing subtask A12, and when executing the synchronization instruction, synchronization request information S1 can be sent to register B' of the hardware synchronization unit. Computing core 3 executes the corresponding synchronization instruction after executing subtask A13, and when executing the synchronization instruction, synchronization request information S1 can be sent to register C' of the hardware synchronization unit. When the hardware synchronization unit receives the synchronization request information S1 from registers A', B' and C' respectively, it can be determined that the synchronization request information S1 meets the synchronization condition, the first synchronization operation A1 is completed, and the synchronization information S1 in registers A', B' and C' can be cleared.

[0097] If it is determined that the synchronization request information S1 is temporarily stored in the register A', it can be determined that the computing cores 2 and 3 have not yet completed the synchronization. Therefore, the computing cores 2 and 3 can be the target computing cores.

[0098] According to the synchronization information read from the hardware synchronization unit, the first synchronization operation and the target computing core that have not completed synchronization can be determined. All unexecuted synchronization instructions are replaced with interrupt instructions. Then run the target computing core that has not completed synchronization. For example, the target computing core is made to fetch instructions from the memory one by one and run. If the instructions fetched by the target computing core include interrupt instructions, it can be determined that the interrupt instruction point is a synchronization instruction. The above-mentioned execution subject can determine whether the synchronization instruction continues to execute the first synchronization operation or adds a second synchronization operation. If the first synchronization operation is continued, the first synchronization operation is executed. If the synchronization indicates that a second synchronization operation is added, the synchronization instruction is transferred to the storage medium for execution, and the synchronization information of the second synchronization operation is stored in the storage medium according to the execution result. The above-mentioned first operation is looped until the first synchronization operation is completed.

[0099] S403: When the first synchronization operation is completed, perform a context switching operation.

[0100] For example, information such as intermediate processing results in the processor's registers, instruction information in the memory, location information where instructions in the memory are executed, intermediate processing results stored in the memory, and second synchronization information are copied to the storage medium.

[0101] In some embodiments, the above step S403 includes the following steps:

[0102] First, when the first synchronization operation is in a completed state, it is detected whether the instruction queue of each computing core is in an idle state.

[0103] Secondly, in response to the instruction queue being in an empty state, information of the task storage space corresponding to the program is saved to the storage medium, completing the context switching operation.

[0104] When the computing core is in the paused state, the states of the instruction queues in all computing cores are checked in turn. If all instruction queues are idle, the context switching is completed after the task storage space information is saved.

[0105] Otherwise, find the instruction queue in non-idle state for subsequent processing. When paused, the instruction queue can only have two states: idle state, which means that all instructions in the instruction queue have been executed. Non-idle state, which means that the instruction execution unit is blocked by synchronous instructions, resulting in the inability to continue to execute subsequent instructions.

[0106] When the first synchronization operation is in the completed state, and the synchronization information of the newly added synchronization operation is saved to the storage medium, there will be no congestion in the instruction queue of the computing core, that is, if there are instructions in the instruction queue of the computing core that have not been executed, these instructions can be smoothly executed when the first synchronization operation is completed. Therefore, after all these instructions are executed in the computing core, the upper and lower switches can be performed. This can further ensure that the program is in a steady-state pause when switching out.

[0107] In this embodiment, for the context switch instruction that switches the context of the program from the processor to the storage medium, if the subsequent synchronization instruction continues to execute the unfinished first synchronization operation, the synchronization instruction continues to be executed in the processor. If the candidate synchronization is cured to execute the newly added second synchronization operation, the synchronization instruction is copied to the storage medium for execution until the first synchronization operation is completed, and the context switch operation is performed when the first synchronization operation is completed. When the first synchronization operation is completed, there is no unfinished synchronization operation in the processor, and it can be considered that the program is in a steady-state pause at this time. At this time, the program context is switched out from the processor, so that when the above program is re-run according to the context, it can be accurately continued from the pause point.

[0108] In some embodiments, multiple instruction queues and multiple instruction execution units may be set in the computing core of the multi-computing core processor. Instructions in multiple instruction queues may be executed in parallel, and instructions are taken out of the queues and executed by the instruction execution units. When the execution units execute synchronization instructions, they interact with the hardware synchronization unit to determine whether the synchronization condition is met. If it is met, it continues to execute backwards, and if it is not met, it continues to wait.

[0109] In some application scenarios, each instruction execution unit may correspond to an instruction queue. In this application scenario, an instruction execution unit may extract instructions from its corresponding instruction queue. When the instruction extracted by the instruction execution unit from its corresponding instruction queue is a synchronization instruction, the instruction execution unit may send synchronization information to the hardware synchronization unit.

[0110] Please refer to Figure 5 , which shows a schematic flow chart of another embodiment of the context switching method of the present disclosure, such as Figure 5 As shown, the method comprises the following steps:

[0111] S501: In response to receiving a context switch instruction of a program, detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor; the processor includes multiple computing cores and a hardware synchronization unit; the context switch instruction is an instruction to switch the context of the program from a storage medium to the processor.

[0112] S502: In response to detecting that there is an incomplete first synchronization operation, repeatedly executing the following first operation until the first synchronization operation is completed: continuing to execute the program instructions of the program through the computing core; if the subsequent synchronization instructions in the program instructions indicate to continue to execute the first synchronization operation, executing the first synchronization operation according to the synchronization instructions; if the subsequent synchronization instructions in the program instructions indicate to add a third synchronization operation, recording new synchronization information indicating the addition of the third synchronization operation in the hardware synchronization unit of the processor.

[0113] In this embodiment, the execution subject may be a central processing unit.

[0114] The processor running the program may be a multi-computing core processor, which may have multiple computing cores.

[0115] In this embodiment, the context switching instruction of the above program is an instruction to switch the context of the program from the storage medium to the multi-computing core processor.

[0116] The storage medium here may be a storage medium on a terminal device on which the multi-computing core processor is arranged, such as a memory, or a removable storage medium, etc.

[0117] The context information of the program stored in the storage medium may be cut out from other processors. The above storage medium may store the hardware structure information of the other processors, such as the hardware information of the computing core, hardware synchronization unit, registers storing intermediate results, etc. involved in the program.

[0118] When the central processing unit enters the program context into the multi-computing core processor, it can establish a mapping relationship between the hardware structure of other multi-computing core processors and the hardware structure of the multi-computing core processor according to the recorded hardware structure information of other multi-computing core processors. For example, the central processing unit establishes a mapping relationship between the computing cores in the other multi-computing core processors and the computing cores of the multi-computing core processor, and establishes a mapping relationship between the registers storing intermediate results in other multi-computing core processors and the registers of the multi-computing core processor, etc. In this way, the computing cores in the other multi-computing core processors can correspond one-to-one to the computing cores in the multi-computing core processor.

[0119] The program context in the above-mentioned storage medium may be a program context cut out from other multi-computing core processors. The above-mentioned storage medium may include unexecuted program instructions of the program, intermediate execution results of executed program instructions read from registers of the above-mentioned other multi-computing core processors, and synchronization information of newly created second synchronization operations (when performing program context cutting in, these second synchronization operations may be regarded as first synchronization operations) obtained when the program context is cut out from other multi-computing core processors. The above-mentioned synchronization information may carry information of the corresponding computing core, and the information of the computing core may include, for example, an identifier of the computing core. The identifier of the computing core is used to distinguish different computing cores.

[0120] In this embodiment, when the central processing unit receives the context switch instruction, it can copy the program instructions to be executed in the storage medium to the memory corresponding to the central processing unit for storing program instructions.

[0121] The intermediate execution result is then saved in the register of the multi-computing core processor corresponding to the execution subject.

[0122] For the above synchronization information in the storage medium, the central processing unit can also gradually import the above synchronization information into the multi-computing core processor.

[0123] In addition, since there are not enough data interaction interfaces of the hardware synchronization unit in the multi-computing core processor, it is impossible to directly copy the synchronization information of the first synchronization operation in the storage medium to the hardware synchronization unit. The first synchronization operation can be executed in a step-by-step manner, and after the first synchronization operation is completed, the program context is switched to the processor.

[0124] The central processing unit detects from the memory space whether there is an unfinished first synchronization operation corresponding to the program.

[0125] After detecting that there is an unfinished first synchronization operation, the central processing unit may replace all synchronization instructions in the unexecuted instructions in the memory with breakpoint instructions, and record the replacement information.

[0126] Specifically, since the synchronization information of the first synchronization operation imported from the storage medium into the above-mentioned memory also records the information of the computing cores of other multi-computing core processors, the target computing core that has not completed synchronization can be determined based on the synchronization information of the first synchronization operation. Then the above-mentioned target computing core is run on the above-mentioned terminal device. Specifically, the target computing core is driven to fetch instructions from the above-mentioned memory. The above-mentioned target computing core puts the fetched instructions into the instruction queue. The instruction execution unit of the target computing core can fetch instructions from the above-mentioned instruction queue in sequence and execute them.

[0127] When the instruction execution unit executes the breakpoint instruction, the central processing unit reports the breakpoint information to the above-mentioned execution subject. The above-mentioned execution subject determines the synchronization instruction corresponding to the breakpoint information. Then, according to the synchronization instruction, it is determined whether to update the first synchronization information or add new synchronization information. If the first synchronization operation continues to be executed, the instruction execution unit does not execute the synchronization instruction, and the instruction execution unit continues to execute the instructions after the synchronization instruction. At the same time, the above-mentioned execution subject executes the above-mentioned synchronization instruction in the memory to update the synchronization information of the first synchronization operation in the memory.

[0128] If the synchronization instruction is to add a third synchronization operation, the synchronization instruction is executed in the instruction execution unit, and synchronization information of the newly added third synchronization operation is written into the hardware synchronization unit of the processor with multiple computing cores.

[0129] After executing the above-mentioned synchronization instruction and obtaining the synchronization information of the synchronization instruction, the above-mentioned central processing unit can determine whether the synchronization information of the first synchronization operation meets the synchronization condition. If the synchronization condition is met, the above-mentioned central processing unit can send the above-mentioned information that meets the synchronization condition to the multi-computing core processor. The synchronization unit of the multi-computing core processor sends a signal to each computing core to notify that the first synchronization operation is synchronized and completed. The above-mentioned execution subject can clear the synchronization information of the above-mentioned first synchronization operation in the above-mentioned memory. If the synchronization condition is not met, the above-mentioned central processing unit re-determines the target computing core based on the synchronization information obtained after executing the above-mentioned synchronization instruction, and repeats the above-mentioned first operation. Until the first synchronization operation in the above-mentioned memory is completely completed.

[0130] S503: When the first synchronization operation is in a completed state, perform a context switching operation.

[0131] The above step S503 includes: when the first synchronization operation is in a completed state, restoring the program instructions, so that each computing core starts running from the specified instructions, and completing the context switching operation.

[0132] Before the first synchronization operation is completed, the program instructions to be executed in the storage medium have been copied to the memory space of the terminal device running the multi-computing core processor, and the processor information stored in the storage medium has been copied to the multi-computing core processor. When the first synchronization operation is completed, the program instructions can be restored, so that each computing core starts running from the specified instructions, and the context switch is completed.

[0133] In this embodiment, when the context of the program is cut into the processor from the storage medium, the information stored in the storage medium is imported into the memory space corresponding to the processor. For the unfinished first synchronization operation in the storage medium, the operation of the computing core is promoted. For the subsequent synchronization instruction indicating the continuation of the first synchronization operation, the computing core synchronizes the first synchronization operation to the memory for execution and updates the synchronization information of the first synchronization operation; for the subsequent synchronization instruction indicating the addition of a third synchronization operation, the computing core executes the synchronization instruction and saves the synchronization information corresponding to the third synchronization operation in the hardware synchronization unit until the first synchronization operation is completed. The program is cut into at the steady state. In addition, the above-mentioned step-by-step method is adopted to cut into the context of the above-mentioned program, which can save the physical space for setting the hardware synchronization unit write operation entry for the processor, can reduce the volume of the processor, and is conducive to the miniaturization of the processor; or more computing cores are arranged under the same processor area to improve the computing power of the processor.

[0134] Please refer to Figure 6 , which shows a principle flow chart of the context switching method disclosed in the present invention. The context switching is used to cut out the program context from the processor. Figure 6 As shown, the execution subject receives the context switch instruction 61, and the execution subject sends a pause request to the processor to pause each computing core in the processor 62. Specifically, after receiving the pause request, the processor sends a pause command to all computing cores, waiting for the computing core to stop working (that is, stop fetching instructions from the memory).

[0135] When the computing core is in the paused state, the execution subject sequentially checks whether the instruction queues in all computing cores are in an idle state 63. If all instruction queues of the computing core are idle, the context switch is completed after the task storage space information is saved. For example, the execution subject may send a command to the processor to feedback the state of the instruction queue of the computing core, and the processor may feedback the feedback information of whether each computing core is in an idle state to the execution subject.

[0136] If some instruction queues are not in idle state, then find out the instruction queues in non-idle state for subsequent processing. For example, determine the identifier of the computing core in non-idle state based on the feedback information. When paused, the instruction queue can only have two states: idle state, indicating that all instructions in the instruction queue have been executed. Non-idle state, indicating that the instruction execution unit is blocked by the synchronization instruction, resulting in the inability to continue to execute subsequent instructions.

[0137] In some application scenarios, the execution entity may regard the computing core having the instruction queue in a non-idle state as a target computing core.

[0138] In some embodiments, the above-mentioned execution subject can export the synchronization information in the hardware synchronization unit through the hardware synchronization unit data reading interface provided by the processor, and determine the unfinished first synchronization operation according to the synchronization information, and determine the target computing core that has not completed the first synchronization operation.

[0139] The execution subject may also replace the synchronization instructions in the instructions in the memory that have not been fetched into the instruction queue with the breakpoint instructions 64 .

[0140] The execution subject sends a running instruction to the processor, and the processor runs each computing core in turn and waits for a breakpoint 65. When a computing core runs to a synchronization instruction (which has been replaced by a breakpoint instruction), it will report an interrupt, and at this time it is determined whether the synchronization instruction will continue to execute the first synchronization operation. If the instruction will continue to execute the first synchronization operation 66, the computing core will execute the instruction 67. After executing the first synchronization operation, the computing core will send synchronization information to the hardware synchronization unit. The synchronization information in the hardware synchronization unit is updated. The hardware synchronization unit determines whether the first synchronization operation is completed based on the updated synchronization information 68. For example, the hardware synchronization unit determines whether the synchronization condition of the first synchronization operation is met based on the updated synchronization information. If it is met, the first synchronization operation is completed, otherwise it is not completed. After determining that the first synchronization operation is completed, the hardware synchronization unit will send a prompt message to each computing core that the first synchronization operation has been completed. The processor can send the prompt message to the execution subject, and the execution subject performs a context switch-out operation to save memory storage space 69. When the computing core runs to the synchronization instruction, an interrupt is reported. The execution subject determines to add a second synchronization operation according to the interrupt, and then copies the synchronization instruction to the storage medium for execution 610. The synchronization information of the second synchronization operation obtained by executing the synchronization instruction is stored in the storage medium. In addition, when the execution subject copies the synchronization instruction to the storage medium for execution, it can send an instruction to the processor to continue running the computing core and wait for the breakpoint. Repeat steps 65 to 68 and 610. When the hardware synchronization unit determines that the first synchronization operation is not completed according to the updated synchronization information 68, repeat steps 65 to 68 and 610 until the first synchronization operation is completed.

[0141] Please refer to Figure 7 , which shows a principle flow chart of the context switching method of the present invention. The context switch is used to cut into the program context in the processor. All information recorded in the software needs to be restored to the computing core hardware module so that it can continue to run from the state when it was suspended. The cut-in process can be executed when there are idle computing cores. It should be noted that the cut-in process starts from the full takeover state (the full takeover state is that the position of the instructions executed by each computing core is fixed, and the instructions can be replaced and modified arbitrarily).

[0142] like Figure 7 As shown, a context switch-in instruction 71 is received, and the context switch-in process is the reverse process of the switch-out process. When the context switch-in instruction is received, the program storage space (including program instructions, intermediate processing results, etc.) in the storage medium is copied to the device memory, that is, the storage space 72 is restored.

[0143] The central processing unit checks the program context data information to be switched in the storage medium, and determines whether the synchronization information of the first synchronization operation satisfies the synchronization condition 73. If there is no synchronization information corresponding to the unfinished first synchronization operation, the synchronization condition is satisfied, and the central processing unit can restore the program instructions to their original state, and directly start the computing core from the specified instructions to continue running, and the context switching is completed at this time.

[0144] If there is synchronization information corresponding to the unfinished first synchronization operation in the context data information of the program to be switched in (the synchronization information in the context data information of the program to be switched in has not been cleared), it is necessary to gradually advance the running of the program until the synchronization information of the first synchronization operation of all software is cleared, specifically:

[0145] The CPU replaces all unexecuted synchronization instructions with breakpoint instructions 74 and drives the computing core to start running until it reports a breakpoint (runs to the synchronization instruction) 75.

[0146] The central processing unit checks whether the synchronization instruction will execute the first synchronization operation 76. If the synchronization instruction indicates to execute the first synchronization operation, the central processing unit instructs the computing core not to execute the synchronization instruction, and updates the synchronization information of the first synchronization operation in the above-mentioned software data structure. After updating the synchronization information of the first synchronization operation, the above-mentioned execution subject can determine whether the synchronization condition is met 77. If the synchronization condition is met, the first synchronization operation is completed, and the computing core continues to run 79, and the cut-in is completed.

[0147] If the central processing unit checks that the synchronization instruction does not execute the first synchronization operation, it will replace the instruction with the original instruction and continue to execute it in the computing core (at this time, when the computing core executes the synchronization instruction, it will create new synchronization information of the third synchronization operation in the hardware synchronization unit).

[0148] When the CPU is executing the above synchronization instruction by calculation and operation, it can return to step 76 to continue to run and wait for the breakpoint. Steps 75 to 77 are repeatedly executed until the first synchronization operation is completed.

[0149] At this time, the program instructions are restored to their original state, so that each computing core starts running from the specified instructions, and the context switching is completed.

[0150] It should be noted that the operability of the hardware synchronization unit is related to the specific hardware function and circuit implementation. If the hardware synchronization unit only supports reading data, you can follow the above Figure 3 and Figure 4 The process shown completes the context switch.

[0151] In some embodiments, when the multi-computing core processor supports the operations of reading, writing and clearing data of the hardware unit, the context switching method for switching out the program context from the multi-computing core processor includes the following steps:

[0152] First, in response to detecting that there is an uncompleted first synchronization operation, synchronization information indicating the first synchronization operation is read out from the hardware synchronization unit.

[0153] Secondly, a software synchronization data structure is created for the synchronization information in the storage medium, and the synchronization information is stored in the software synchronization data structure.

[0154] Again, clear the synchronization information in the hardware synchronization unit to allow the blocked instructions to continue running.

[0155] Finally, the context switch operation is completed when the processor's instruction queue is in an idle state.

[0156] If the hardware synchronization unit supports reading, writing and clearing (which will increase the complexity of the hardware circuit program), you can refer to the relevant solutions for context switching in software to implement the execution of switching out the program context from the processor.

[0157] In some embodiments, when the processor supports the operations of reading, writing and clearing data of the hardware unit, the context switching method for switching into the program context of the processor includes the following steps:

[0158] First, in response to determining that the hardware synchronization unit supports read, write and clear data operations, and in response to detecting an uncompleted first synchronization operation, importing synchronization information in a software synchronization data structure into the hardware synchronization unit of the processor;

[0159] Second, the instructions are restored and all computing cores are made to run from the specified location.

[0160] If the hardware synchronization unit supports reading, writing and clearing (which will increase the complexity of the hardware circuit program), then the relevant solution for context switching in software can be referred to to implement the execution of switching the program context into the processor.

[0161] Please refer to Figure 8 , which shows a schematic diagram of the structure of the context switching device provided by the present disclosure. Figure 8 As shown, the context switching device includes a detection unit 801, an execution unit 802 and a switching unit 803.

[0162] The detection unit 801 is used for detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor in response to receiving a context switch instruction of the program; the processor includes multiple computing cores and a hardware synchronization unit;

[0163] The execution unit 802 is configured to, in response to detecting that there is an uncompleted first synchronization operation, repeatedly perform the following first operation until the first synchronization operation is completed: continue to execute the program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instruction indicates to continue to execute the first synchronization operation, perform the first synchronization operation according to the synchronization instruction;

[0164] The switching unit 803 is configured to perform a context switching operation when the first synchronization operation is in a completed state.

[0165] In some embodiments, the execution unit 802 is further configured to:

[0166] In response to detecting that there is an uncompleted first synchronization operation, replacing the unexecuted synchronization instructions in the program instructions with breakpoint instructions;

[0167] Based on the breakpoint instruction, the first operation is repeatedly executed.

[0168] In some embodiments, the context switch instruction is a context switch instruction that instructs the context of a program to be switched from the processor to the storage medium.

[0169] In some embodiments, the detection unit 801 is further configured to:

[0170] Read the synchronization information in the hardware synchronization unit;

[0171] It is detected whether there is an unfinished first synchronization operation according to the synchronization information, wherein the synchronization information indicates a state of the first synchronization operation.

[0172] In some embodiments, the first operation performed by the execution unit 802 further includes:

[0173] If it is determined that the subsequent synchronization instruction in the program instruction indicates the addition of a second synchronization operation, the newly added synchronization information indicating the second synchronization operation is recorded in the memory.

[0174] In some embodiments, the switching unit 803 is further configured to:

[0175] When the first synchronization operation is in a completed state, detecting whether the instruction queue of each computing core is in an idle state;

[0176] In response to the instruction queue being in an empty state, information of the task storage space corresponding to the program is saved to the storage medium, and the context switching operation is completed.

[0177] In some embodiments, the context switch instruction is an instruction for switching the context of a program from a storage medium to a processor.

[0178] In some embodiments, the detection unit 801 is further configured to:

[0179] In a suspended state of the processor, detecting whether the program currently has an unfinished first synchronization operation includes:

[0180] It is detected from the storage medium whether there is an uncompleted first synchronization operation corresponding to the program.

[0181] In some embodiments, the first operation performed by the execution unit 802 further includes:

[0182] If the subsequent synchronization instruction in the program instruction indicates adding a third synchronization operation, the newly added synchronization information indicating the newly added third synchronization operation is recorded in the hardware synchronization unit of the processor.

[0183] In some embodiments, the switching unit 803 is further configured to:

[0184] When the first synchronization operation is in a completed state, the program instructions are restored so that each computing core starts running from the specified instructions, completing the context switching operation.

[0185] The present disclosure also provides an electronic device involved in the context switching method.

[0186] refer to Fig. 9 , which shows a schematic diagram of the structure of an electronic device 900 suitable for implementing the embodiment of the present disclosure, and the electronic device 900 may be a terminal device or a server. The terminal device may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (Portable Android Devices, PADs), portable multimedia players (PMPs), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 9 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0187] like Fig. 9As shown, the electronic device 900 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 to a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the electronic device 900 are also stored. The processing device 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0188] Typically, the following devices may be connected to the I / O interface 905: input devices 906 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 908 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 909. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data. Although Fig. 9 The electronic device 900 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0189] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 909, or installed from the storage device 908, or installed from the ROM 902. When the computer program (computer execution instruction) is executed by the processing device 901, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0190] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code (computer-executable instructions) contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0191] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0192] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0193] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0194] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0195] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0196] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0197] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A context switching method, the method comprising: In response to receiving a context switch instruction of a program, detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor; The processor includes a plurality of computing cores and a hardware synchronization unit; In response to detecting that there is an uncompleted first synchronization operation, repeatedly performing the following first operation until the first synchronization operation is completed: Continue to execute the program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instructions indicates to continue to execute the first synchronization operation, execute the first synchronization operation according to the synchronization instruction; When the first synchronization operation is in a completed state, a context switching operation is performed.

2. The method according to claim 1, characterized in that In response to detecting that there is an uncompleted first synchronization operation, repeatedly performing the following first operation includes: In response to detecting an uncompleted first synchronization operation, replacing the unexecuted synchronization instructions in the program instructions with breakpoint instructions; Based on the breakpoint instruction, the first operation is repeatedly performed.

3. The method according to claim 1, characterized in that The context switch instruction is a context switch instruction for instructing the processor to switch the context of the program to a storage medium.

4. The method according to claim 3, characterized in that The detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor comprises: Reading synchronization information in the hardware synchronization unit; It is detected whether there is an unfinished first synchronization operation according to the synchronization information, wherein the synchronization information indicates a state of the first synchronization operation.

5. The method according to claim 3, characterized in that: The first operation further includes: If it is determined that the subsequent synchronization instruction in the program instruction indicates a newly added second synchronization operation, newly added synchronization information indicating the second synchronization operation is recorded in the memory.

6. The method according to claim 3, characterized in that The performing of the context switching operation when the first synchronization operation is in a completed state comprises: When the first synchronization operation is in a completed state, detecting whether the instruction queue of each computing core is in an idle state; In response to the instruction queue being in an empty state, information of the task storage space corresponding to the program is saved to a storage medium, thereby completing a context switching operation.

7. The method according to claim 1, characterized in that The context switching instruction is an instruction for switching the context of the program from the storage medium to the processor.

8. The method according to claim 7, characterized in that The detecting whether the program currently has an unfinished first synchronization operation in a paused state of the processor comprises: It is detected from the storage medium whether there is an uncompleted first synchronization operation corresponding to the program.

9. The method according to claim 7, characterized in that: The first operation further includes: If the subsequent synchronization instruction in the program instruction indicates a newly added third synchronization operation, newly added synchronization information indicating the newly added third synchronization operation is recorded in the hardware synchronization unit of the processor.

10. The method according to claim 7, characterized in that The performing of the context switching operation when the first synchronization operation is in a completed state comprises: When the first synchronization operation is in a completed state, the program instructions are restored so that each computing core starts running from the specified instructions, completing the context switching operation.

11. A context switching device, the device comprising: A detection unit, configured to detect whether the program currently has an unfinished first synchronization operation in a paused state of the processor in response to receiving a context switch instruction of the program; the processor comprises a plurality of computing cores and a hardware synchronization unit; The execution unit is configured to, in response to determining that the hardware synchronization unit only supports the read data operation and in response to detecting that there is an uncompleted first synchronization operation, repeatedly perform the following first operation until the first synchronization operation is completed: Continue to execute the program instructions of the program through the computing core; if a subsequent synchronization instruction in the program instructions indicates to continue to execute the first synchronization operation, execute the first synchronization operation according to the synchronization instruction; The switching unit is used to perform a context switching operation when the first synchronization operation is in a completed state.

12. An electronic device, characterized in that: include: Processor and memory; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method according to any one of claims 1 to 10 is implemented.

Images