Large-scale real-time data link layer simulation method and system

Abstract

According to the large-scale real-time data link layer simulation method, a data link layer simulation system based on an FPGA (Field Programmable Gate Array) is composed of a wireless channel simulation module, a media access control module and a logic link control module; the wireless channel simulation module is used for carrying out modeling simulation on a physical channel transmitted in reality in an FPGA (Field Programmable Gate Array), and the channel distributes control signals to different nodes according to the control signals of the media access control module and transmits high-speed data transmitted by an upper-layer transmitting end back to the media access control module after passing through the simulated channel; the wireless channel simulation module has two functions of quantizing a channel model and quantizing an error rate model; in the quantization implementation of channel simulation, the quantization implementation of a channel model is completed, and the FPGA calculates the SNR in the transmission process through the sending frequency, the distance and the system transmission loss parameters transmitted by the upper layer; and randomly carrying out packet loss on the data according to the PER in quantization implementation of the error rate model so as to simulate real communication.

Description

Technical Field

[0001] The invention relates to a data link layer simulation method and system that meet large-scale real-time requirements, and relates to the technical field of network communication simulation. Background Art

[0002] In the field of large-scale wireless communications, building a physical test platform with mobile nodes in a physical environment has the disadvantages of high difficulty and high cost. Therefore, using corresponding simulators and emulators has become a cost-effective testing solution.

[0003] CN202210503276.6 discloses a real-time data link situation simulation system and method that combines virtual and real, belonging to the technical field of real-time data link situation simulation, including: a distributed simulation environment framework subsystem, used to provide situation display and planning, situation deduction, data centralized control and data link equipment access gateway, and build Josim warehouse, shooting range data archive and timing management equipment; a terminal access subsystem, used to build a distributed data link simulation environment based on the data link equipment access gateway and DDS middleware, and access the data link terminal through an agent to realize real-time simulation of the data link situation, wherein the data link terminal includes a virtual terminal and a real terminal, and provides a simulation method of a real-time data link situation simulation system that combines virtual and real to realize battlefield situation simulation; the present invention relates to solving the problem of insufficient authenticity and real-time performance of data link situation simulation.

[0004] The current mainstream emulators and simulators can be divided into:

[0005] ① Discrete event-based simulation software. Represented by NS-3 and OPNET, this type of simulation software was originally designed to calculate network behavior. The software runs according to the tick inside the program, which is different from the real world time, and needs to process the event content according to the order in the event queue.

[0006] ②The virtualization-based network simulation platform aims to use software to generate virtualized network nodes. There is an isolation mechanism between nodes, and the generated nodes can simulate the transmitted data stream in real time using real-world physical time.

[0007] The above-mentioned simulators and emulators have the following problems in the field of large-scale communication simulation:

[0008] ① Discrete event-based simulation software cannot achieve real-time simulation, and in large-scale simulations with many simulation nodes, its actual running time will be much longer than the simulation time inside the simulator.

[0009] ② The virtualization-based network simulation platform uses software to reproduce the complete wireless protocol stack in the node, which makes it extremely dependent on the memory size and CPU computing power of the host machine, and abandons some fidelity to ensure real-time. The simulation results are quite different from reality.

[0010] ③ Both of the above two simulators cannot realize the complete data link layer on the basis of meeting large-scale real-time wireless communication simulation.

[0011] The existence of the above problems is mainly due to the fact that the time slot control of the wireless protocol in the baseband cannot be directly simulated by software in real-world time, and the physical channel model designed in the simulator is relatively sophisticated, which results in a long calculation time and cannot meet the actual simulation requirements.

[0012] Therefore, the present invention proposes a data link layer simulation method and system that meets large-scale real-time requirements. The real MAC protocol and the approximate physical transmission channel model are implemented in the FPGA. Different from traditional simulators and emulators, the present invention can enable up to one thousand nodes to perform wireless communication simulation in real time and realistically on a single FPGA. On this basis, horizontal expansion can meet the needs of larger-scale simulation, providing a feasible solution for the field of large-scale wireless communication simulation. Summary of the invention

[0013] The purpose of the present invention is that the existing mainstream wireless simulation system has its inevitable shortcomings in the field of large-scale wireless communication, and it is impossible to realize a complete data link layer on the basis of large-scale real-time wireless communication simulation. The traditional simulator uses software to indirectly realize the time slot control of the bottom layer of the wireless protocol stack, which leads to the need to slow down the simulation time and cannot achieve real-time; the traditional simulator simplifies the implementation of the protocol, and although it can achieve real-time, it cannot meet the fidelity. Because of the existence of the above problems, it is meaningful to improve the efficiency of large-scale wireless communication simulation through hardware acceleration of heterogeneous fusion. Therefore, the programmable controller FPGA is introduced in the present invention, so that the MAC protocol and physical transmission channel model in the data link layer can be realized in hardware, so that the system can run in real-world time. And because the hardware level can support the parallel calculation of the complete MAC protocol of more than one thousand nodes in a single FPGA, and the fine architecture designed can meet the simulation of the physical transmission channel, the system can achieve large-scale real-time data link layer simulation.

[0014] The current large-scale wireless communication simulation system cannot fully reproduce the 802.11 MAC layer protocol while meeting the real-time simulation requirements, and thus cannot achieve the desired fidelity. To address this problem, the present invention proposes a data link layer simulation method and system that meets large-scale real-time requirements.

[0015] The method of the present invention deploys and implements the data link layer in wireless communication in the form of hardware in FPGA, which is easy to expand horizontally. Therefore, it can realize large-scale wireless communication simulation that meets both real-time and fidelity requirements, and is used to solve the difficulties in the above-mentioned fields.

[0016] Technical solution of the present invention: The present invention implements a real MAC protocol in a high-performance FPGA network card, and quantitatively implements different types of commonly used channel models at the hardware level. Data is sent by the sending node and transmitted to the receiving node through the channel model to complete the real space radio propagation simulation. At the same time, sufficient interfaces are reserved for the upper layer to call and control. The media access control module can support multiple MAC modes, and the implemented protocols include:

[0017] Polling access; TDMA (Time Division Multiplexing) in channel partitioning media access control; CSMA / CA (Carrier Sense Multiple Access with Collision Avoidance) in random access media access control;

[0018] The method of the present invention includes a wireless channel simulation module, a media access control module and a logic link control module in a single FPGA. The functions and interfaces of each module are as follows: Figure 1 Shown: Media Access Control Module

[0019] ① Wireless channel simulation module: This module is mainly responsible for modeling and simulating the physical channel transmitted in reality in FPGA. The channel will be allocated to different nodes according to the control signal of the media access control module, and the high-speed data transmitted from the upper-layer transmitter will be transmitted back to the media access control module through the simulated channel. This module is mainly divided into two parts: the quantization implementation of the channel model and the quantization implementation of the error rate model. In the quantization implementation of channel simulation, several common channel models are implemented, such as the Friis free space propagation model, the logarithmic distance path loss model, the logarithmic shadow fading model, etc. FPGA calculates the SNR, i.e. the signal-to-noise ratio, during the transmission process through the parameters such as the transmission frequency, the distance between each other, and the system transmission loss transmitted from the upper layer. Studies have shown that in different propagation models, SNR and PER (Packet Error Rate) have an approximate corresponding relationship. In the quantization implementation of the error rate model, data packets are randomly dropped according to PER to simulate real communication.

[0020] The specific steps are as follows:

[0021] 1) The user determines the channel model of the communication system or uses the default free space propagation model.

[0022] 2) Read the transmission frequency, receiving and sending distance and other information in the upper layer through the reserved interface.

[0023] 3) The channel model quantization module calculates the SNR.

[0024] 4) According to the obtained SNR, the SNR-PER lookup table is addressed to obtain the corresponding PER.

[0025] 5) The error rate model quantification module refers to the PER to generate a random number to determine whether an error packet occurs.

[0026] ②Media Access Control Module: This module is mainly responsible for channel access and control. It implements various MAC mechanisms in practice, including polling, TDMA, and CSMA / CA, by using hardware logic on the FPGA side. It is used to simulate the channel access control of large-scale wireless communication systems. Users can configure the specific protocol used by the media access control module at the upper layer according to their own simulation requirements. CSMA / CA is used by default to control the flow of the channel. In addition, an interface for information interaction is reserved in this layer, through which high-speed data in the logical link control module can be received and transmitted, as well as node configuration information written by the user, such as node location, node IP information, etc.

[0027] When using the polling access mechanism, the polling list will be initialized first, which includes all nodes that can access the channel. The optional polling order is: sequential polling and weighted polling. Sequential polling is used by default. The controller queries each node in turn according to a fixed time slot. If there is a request, it will be transmitted according to the corresponding request. Weighted polling requires the user to configure the weight of each node by himself, so that the controller can allocate different polling times according to the priority of each node.

[0028] When using the TDMA mechanism, the system divides the total time into several time slots, each of which is assigned to a specific user node. Each node can only transmit and receive data within the specified time slot.

[0029] When using the CSMA / CA mechanism, it also includes the RTS / CTS handshake interaction mechanism. The specific mechanism is as follows:

[0030] 1) The sender sends an RTS frame to indicate a request to send data before sending it.

[0031] 2) After the receiving end parses the source address and destination address in the RTS frame, if it finds that its own address is the same as the destination address in the frame, it returns a CTS frame to the sending end.

[0032] 3) After receiving the CTS frame, the sender performs a handshake and simultaneously sends the data frame and reserves the channel.

[0033] 4) After the sender successfully sends DATA, if the receiver verifies that the data is correct, it will return an ACK frame to indicate that the data has been successfully delivered.

[0034] 5) If the sender has not received a returned ACK frame, it will retransmit the message. If the retransmission exceeds 16 times, the transmission will fail.

[0035] There are two commonly used inter-frame spacings in CSMA / CA: SIFS and DIFS. SIFS, short inter-frame spacing, has a time length of 28μs and is commonly used for CTS frames and ACK frames; DIFS, distributed inter-frame spacing, has a time length of 128μs and is commonly used for DATA frames and management frames. The backoff mechanism of CSMA / CA is specifically divided into the following steps:

[0036] 1) Listen and prepare to fallback: The node listens to whether the channel is idle. If idle, it waits for a DIFS and starts preparing to fallback.

[0037] 2) Calculate the contention window CW: The minimum value of the contention window is set to 16. If backoff occurs during transmission, the contention window is doubled. The maximum value is 255, that is, the contention window is no longer expanded after the sixth backoff.

[0038] 3) Get a random backoff value: Randomly select an integer value Num from the contention window, and the random backoff time obtained is T = Num*T slot , where T slot is the basic backoff time, i.e., one time slot interval.

[0039] 4) Perform backoff: Count down according to the backoff value obtained, and continue to listen to the channel in each time slot. If the channel is busy, the backoff will be temporarily suspended. If the channel is idle and the timer reaches the randomly obtained backoff time, the send command is executed.

[0040] 5) Check whether there is a conflict: If the sender does not receive an ACK frame within the specified time, it means a sending conflict. At this time, the above steps will be repeated until the sender and receiver successfully handshake each other.

[0041] ③ Logical link control module: This module is mainly responsible for providing an interface to the network layer and handling various types of protocols. Because it provides a unified interface, it is compatible with different upper-layer network protocols. The logical link control module inserts an LLC header into the upper-layer data frame, which specifically includes three fields: DSAP field, SSAP field, and Control field. The DSAP field and SSAP field are both one byte long and are used to identify the target service access point and source service access point of the data frame, respectively. Therefore, different network layer protocols can be compatible in the same data link layer through only a simple interface. The Control field is one or two bytes long and is mainly used to control the transmission and processing of data frames.

[0042] In addition, based on the implementation of the MAC protocol in the media access control module, the present invention uses hardware parallelism to install more than 1024 media access control modules inside the FPGA, that is, the communication scenarios of more than 1024 nodes can be simulated simultaneously in one FPGA. Each module performs channel contention and data transmission and reception in the form of different nodes according to the corresponding instructions, data and other information transmitted from the upper layer. Each behavior of the node, such as backing off at a certain moment, sending an RTS request at a certain moment, receiving data at a certain moment, etc., will be saved in their respective log files for users to view the simulation results by themselves.

[0043] When each node receives a communication request from the upper layer, it will first compete for the channel in its own MAC layer according to the set MAC protocol. After the contention is successful, the communication data in the upper layer will be input into the simulated channel in the physical layer, and the data that the receiving end should receive will be simulated according to the parameters set in the channel, and transmitted to the node with the corresponding IP address. The receiving end will verify the data, and if the verification passes, it will return a signal to the sending end to complete the simulation of communication between nodes.

[0044] At the same time, the present invention reserves a high-speed expansion interface in the top-level modules of the MAC layer and the PHY layer, so that the present invention can meet the ultra-large-scale communication simulation when there are more than one thousand nodes. Users can cascade FPGAs according to their own needs to obtain a large-scale FPGA array for simulation of the corresponding scale.

[0045] In summary, a complete system using the method of the present invention can be obtained, which can be composed of a traffic generator, a set of virtual nodes, a single high-performance FPGA network card or a large-scale FPGA array. Figure 2 shown.

[0046] The user generates the virtual data stream that each node needs to transmit through the traffic generator, and transmits it to different nodes in different node sets through the data bus. The user configures the basic communication information and communication requests of each node, and transmits this information and request to the FPGA through the interface. The logical link control module distributes the data to different media access control modules according to the node information. In the scenario of multiple FPGA cascade, the media access control modules and wireless channel simulation modules in each FPGA share information through the cascade module, so it can achieve ultra-large-scale wireless communication data link layer simulation.

[0047] Beneficial effects: The MAC protocol and propagation channel simulation in the present invention are simulated in FPGA and can run in real-world time to meet real-time requirements. The present invention implements FPGA horizontal high-speed expansion modules, so that FPGAs can be cascaded to each other to obtain large-scale FPGA arrays for ultra-large-scale wireless communication simulation. On the basis of meeting large-scale real-time wireless communication simulation (easily achieving more than 1024 nodes), the present invention implements a complete data link layer, which makes up for the shortcomings of current mainstream simulators and emulators. The present invention reserves sufficient interfaces for the upper layer, which can be conveniently called and tested by the upper layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 The function and interface diagram of each module are given;

[0049] Figure 2 A schematic diagram of the overall system architecture is given.

[0050] Figure 3 A logical schematic diagram of the simulated propagation channel is given. DETAILED DESCRIPTION

[0051] The present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be noted that the case given here is only used to provide a more vivid and detailed description of the present invention to facilitate the reader's understanding, and does not mean that the present invention is limited to this example.

[0052] The specific steps are as follows:

[0053] Step 1: User-defined configuration in the upper layer

[0054] In this example, two FPGA boards are used. The FPGA used here takes the Alveo U280 data center accelerator card released by Xilinx as an example. Through configuration, the user implements a virtual network card driver for 2000 nodes in the Linux kernel, which are mounted on the 2000 MAC layers instantiated in the present invention, respectively, with 1000 nodes mounted on each FPGA board, and the two FPGA boards are cascaded. And set through the parameter configuration script 1) total simulation time T = 3000s 2) number of simulation nodes N = 2000 3) IP address of each virtual node, for example 192.168.30.2 4) location information Loc of each virtual node i (t)5) Collision domain Dmax of each virtual node i =40 6) Transmission gain of each virtual node G s (i) = 40 dB, transmission power P s (i) = 35dBm and receiving gain G r(i) = 45 dB 7) The connectivity matrix Topo(t) of the initial network topology 8) The physical propagation channel model is a free space propagation model 9) The number of transmission channels is 1 and the frequency bands of all nodes are consistent.

[0055] Step 2: Collision domain node perception

[0056] According to the configured location information Loc i (t), get the position information (x, y, z) of the i-th node at time t, and use the collision domain Dmax of each node i And the network topology connectivity matrix Topo(t) at time t, count the number of connected nodes m of each node. For example, the position of the first node at the 100th second is (38,15,9), in the collision domain Dmax i =40, its initial connected state matrix It means that node 1 can communicate with all nodes under the premise of satisfying the collision domain.

[0057] The specific steps are as follows:

[0058] Step 2.1: Calculation of the distance matrix D(t) of each node

[0059] The distance d between two points at time t0 i,j (t0) is calculated as:

[0060]

[0061] The distance matrix of the i-th node can be obtained:

[0062]

[0063] Step 2.2: The connected node set P in the collision domain of each node i (t) Calculation

[0064] In the Topo(t) matrix, if the element in the i-th row and j-th column is 1, it means that the network topology of nodes i and j is connected.

[0065] If the nodes satisfy both the initial connectivity matrix and the collision domain, Topo(t) represents the value of the sending and receiving nodes is 1, and the distance between the two points is less than Dmax i , will add the other node to the set P i (t) indicates that the two points can communicate normally. When a node not in the set attempts to communicate, the system will not be able to respond to the communication request and will output the reason for the failure in the log file.

[0066] Step 3: Channel Arbitration and Allocation

[0067] The user can configure the channel model and corresponding parameters used in the simulation at the upper layer. The optional channel models include the Friis free space propagation model, the logarithmic distance path loss model, and the logarithmic shadow fading model. The Friis free space propagation model is used in this example. This model is used to simulate the line of sight (LOS) path loss generated in a free space environment. There is no object that absorbs, diffracts, reflects, or changes any other characteristics of the radiated wave. After the signal passes through the model, the RSSI during the transmission process will be calculated. The calculation process is described in step 5. The physical layer contains a channel arbitrator to monitor the occupancy of different channel types globally. When the corresponding channel is idle, the signals to be sent in the waiting queue will be taken out in turn, and the channel will be allocated to the node.

[0068] Step 4: Listen to the channel and send data

[0069] The node receives the sending request and data from the upper layer and keeps listening to the channel. If the channel becomes idle, it waits for a DIFS time (distributed coordination function inter-frame interval time) and prepares to fall back.

[0070] According to the number of backoff times, the backoff window size CW of the node at this time is obtained i (t). Randomly obtain a backoff integer value Num in the backoff window and wait for Num basic backoff time slots, that is, T = Num*T slot For example, when no backoff is performed, the minimum backoff window value is taken, that is, CW i (t)=16, and Num is a random integer satisfying the interval [0,16].

[0071] If the channel becomes busy during the waiting process, the system will back off and suspend.

[0072] If the channel is idle and the backoff time countdown is 0, the RTS / CTS interaction begins. After the interaction is successful, data transmission begins.

[0073] Step 5: Calculate the packet loss rate of the network link

[0074] According to the set transmission channel model, the transmission gain G s (i) Transmit power P s (i) and receiving gain G r (i), the frequency band between nodes and the distance d between the sending and receiving nodes i,j , the rssi during the transmission process can be calculated.

[0075] rssi=G r (i)+G s (i)+P s (i)-C

[0076] The constant C is obtained from the channel model, transmission frequency band and node distance.

[0077] After converting rssi into half dB value, the packet loss rate of the node transmission process can be obtained by looking up the generated SNR-BER comparison table. For example, in this example, rssi = -40dB is calculated, and the packet loss rate is 0.5% by looking up the table.

[0078] Step 6. Simulate node update log

[0079] Each simulation node has a separate log file to record the communication history of the node. If the node has sending or receiving behavior at time t0, whether backoff occurs, whether the transmission is successful, and the corresponding packet loss rate will be output in the log file for users to call and view the simulation results.

[0080] Step 7: Determine whether the total simulation time has been reached

[0081] The simulation system will count the running time of this time. If the set running time is reached, the simulation ends. Otherwise, each node continues to try to compete for the channel for communication.

[0082] Calculation of the perception of collision or collision domain nodes in CSMA / CA carrier sense multiple access with collision avoidance:

[0083] According to the configured location information Loc i (t), get the position information (x, y, z) of the i-th node at time t, and use the collision domain Dmax of each node i And the network topology connectivity matrix Topo(t) at time t, count the number of connected nodes m of each node. For example, the position of the first node at the 100th second is (38,15,9), in the collision domain Dmax i =40, its initial connected state matrix It means that node 1 can communicate with all nodes under the premise of satisfying the collision domain.

[0084] The specific steps are as follows:

[0085] Step 2.1: Calculation of the distance matrix D(t) of each node

[0086] The distance d between two points at time t0 i,j (t0) is calculated as:

[0087]

[0088] Get the distance matrix of the i-th node:

[0089]

[0090] Step 2.2: The connected node set P in the collision domain of each node i (t) Calculation

[0091] In the Topo(t) matrix, if the element in the i-th row and j-th column is 1, it means that the network topology of nodes i and j is connected.

[0092] If the nodes satisfy both the initial connectivity matrix and the collision domain, Topo(t) represents the value of the sending and receiving nodes is 1, and the distance between the two points is less than Dmax i , will add the other node to the set P i (t) indicates that the two points can communicate normally. When a node not in the set attempts to communicate, the system will not be able to respond to the communication request and will output the reason for the failure in the log file.

[0093] The above-mentioned examples are only preferred examples of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A large-scale real-time data link layer simulation method, characterized in that: A data link layer simulation system based on FPGA, which consists of a wireless channel simulation module, a media access control module and a logical link control module; Wireless channel simulation module: The physical channel transmitted in reality is modeled and simulated in FPGA. The channel will be allocated to different nodes according to the control signal of the media access control module, and the high-speed data transmitted from the upper-layer transmitter will be transmitted back to the media access control module through the simulated channel. The wireless channel simulation module has two functions: the quantization implementation of the channel model and the quantization implementation of the error rate model. In the quantization implementation of channel simulation, the quantization implementation of common channel models is completed, including the Friis free space propagation model, the logarithmic distance path loss model, and the logarithmic shadow fading model. The FPGA calculates the SNR, i.e., signal-to-noise ratio, during the transmission process through the transmission frequency, separation distance, and system transmission loss parameters transmitted from the upper layer. There is an approximate corresponding relationship between SNR and PER (Packet Error Rate). In the quantization implementation of the error rate model, data packets are randomly dropped according to PER to simulate real communication. The specific steps are as follows: 1) The user determines the channel model of the communication system or uses the default free space propagation model; 2) Read the transmission frequency, receiving and sending distance and other information in the upper layer through the reserved interface; 3) The channel model quantization module calculates the SNR; 4) According to the obtained SNR, address the SNR-PER lookup table to obtain the corresponding PER; 5) The error rate model quantification module refers to the PER to generate a random number to determine whether an error packet occurs; Media access control module: For channel access and control, multiple MAC mechanisms (data link layer protocol, responsible for data frame transmission and routing) are implemented by hardware logic on the FPGA side, including polling, TDMA and CSMA / CA; used to simulate the channel access control of large-scale wireless communication systems; users can configure the specific protocol used by the media access control module at the upper layer according to their own simulation requirements, and CSMA / CA is used by default to control the flow of the channel; and an interface for information interaction is reserved in this layer, through which high-speed data in the logical link control module can be received and transmitted, as well as node configuration information independently written by users, including node location and node IP information; When using the polling access mechanism, the polling list will be initialized first, which includes all nodes that can access the channel. The optional polling order is: sequential polling and weighted polling. The default is sequential polling, where the controller queries each node in turn according to a fixed time slot, and transmits according to the corresponding request if there is a request. Weighted polling requires the user to configure the weight of each node, so that the controller can allocate different polling times according to the priority of each node. By implementing the real MAC protocol in a high-performance FPGA network card and quantizing different types of common channel models at the hardware level, data is sent from the sending node and transmitted to the receiving node through the channel model to complete the real-space radio propagation simulation. At the same time, sufficient interfaces are reserved for the upper layer to call and control; The media access control module can support multiple MAC modes, and the implemented protocols include: Polling access; TDMA (time division multiplexing) in channel division media access control; CSMA / CA (Carrier Sense Multiple Access with Collision Avoidance) in random access media access control, an algorithm to avoid data transmission conflicts between stations during data transmission. Its characteristic is that it cannot detect whether there is a conflict on the channel while sending a packet, and can only try to "avoid" it); Logical link control module: provides an interface to the network layer and handles various types of protocols; the logical link control module inserts the LLC frame header into the upper layer data frame, which specifically contains three fields: DSAP field, SSAP field and Control field. The DSAP field and SSAP field are both one byte long and are used to identify the target service access point and source service access point of the data frame, respectively. Therefore, different network layer protocols can be compatible in the same data link layer through a simple interface; the Control field is one or two bytes long and is mainly used to control the transmission and processing of data frames; On the basis of implementing the MAC protocol in the media access control module, more than 1024 media access control modules are installed in the FPGA by using hardware parallelism, that is, the communication scenarios of more than 1024 nodes can be simulated simultaneously in one FPGA; each media access control module performs channel contention and data transmission and reception in the form of different nodes according to the corresponding instructions, data and other information transmitted from the upper layer. The behaviors of the nodes include: backing off at a certain time, sending RTS requests at a certain time, and receiving data at a certain time, which will be saved in their respective log files for users to view the simulation results by themselves; When each node receives a communication request from the upper layer, it will first compete for the channel in its own MAC layer according to the set MAC protocol. After the competition is successful, the communication data in the upper layer will be input into the simulated channel in the physical layer, and the data that the receiving end should receive will be simulated according to the parameters set in the channel, and then transmitted to the node with the corresponding IP address. The receiving end will verify the data, and if the verification passes, it will return a signal to the sending end to complete the simulation of communication between nodes. At the same time, high-speed expansion interfaces are reserved in the top-level modules of the MAC layer and the PHY layer, which can meet the ultra-large-scale communication simulation of more than one thousand nodes. Users can cascade FPGAs according to their own needs to obtain large-scale FPGA arrays for simulations of corresponding scales.

2. The large-scale real-time data link layer simulation method according to claim 1 is characterized in that: When using the TDMA mechanism, the system divides the total time into several time slots, each of which is assigned to a specific user node. Each node can only transmit and receive data within the specified time slot.

3. The large-scale real-time data link layer simulation method according to claim 2 is characterized in that: When using the CSMA / CA mechanism, it also includes the RTS / CTS handshake interaction mechanism. The specific mechanism is as follows: 1) The sender sends an RTS frame to indicate a request to send data before sending it. 2) After the receiving end parses the source address and destination address in the RTS frame, if it finds that its own address is the same as the destination address in the frame, it returns a CTS frame to the sending end; 3) After receiving the CTS frame, the sender performs a handshake and simultaneously sends data frames and reserves the channel; 4) After the sender successfully sends DATA, if the receiver verifies that the data is correct, it will return an ACK frame to indicate that the data has been successfully delivered; 5) If the sender does not receive an ACK frame, it will retransmit. If the retransmission exceeds 16 times, the transmission will fail. There are two commonly used inter-frame space (IFS) in CSMA / CA: SIFS and DIFS. SIFS, short inter-frame space, has a time length of 28 μs and is commonly used for CTS frames and ACK frames. DIFS, distributed inter-frame space, has a time length of 128 μs and is commonly used for DATA frames and management frames.

4. The large-scale real-time data link layer simulation method according to claim 2 is characterized in that: The CSMA / CA backoff mechanism is divided into the following steps: 1) Listen and prepare to fallback: The node listens to whether the channel is idle. If it is idle, it waits for a DIFS and starts to prepare to fallback; 2) Calculate the contention window CW: The minimum value of the contention window is set to 16. If backoff occurs during transmission, the contention window is doubled. The maximum value is 255, that is, the contention window is no longer expanded after the sixth backoff; 3) Get a random backoff value: Randomly select an integer value Num from the contention window, and the random backoff time obtained is T = Num*T slot , where T slot is the basic backoff time, i.e., a time slot interval; 4) Perform backoff: Count down according to the backoff value obtained, and continue to listen to the channel in each time slot. If the channel is busy, the backoff will be temporarily suspended. If the channel is idle and the timer reaches the randomly obtained backoff time, the send command is executed; 5) Check whether there is a conflict: If the sender does not receive the ACK frame within the specified time, it means a sending conflict. At this time, the above steps will be repeated until the sender and receiver successfully handshake each other.

5. The large-scale real-time data link layer simulation method according to claim 1 is characterized in that: Calculation of the perception of collision or collision domain nodes in CSMA / CA carrier sense multiple access with collision avoidance: According to the configured location information Loc i (t), get the position information (x, y, z) of the i-th node at time t, and use the collision domain Dmax of each node i And the network topology connectivity matrix Topo(t) at time t, counting the number of connected nodes m of each node. The specific steps are as follows: Step 2.1: Calculation of the distance matrix D(t) of each node The distance d between two points at time t0 i,j (t0) is calculated as: Get the distance matrix of the i-th node: Step 2.2: The connected node set P in the collision domain of each node i (t) Calculation In the Topo(t) matrix, if the element in the i-th row and j-th column is 1, it means that the network topology of nodes i and j is connected. If the nodes satisfy both the initial connectivity matrix and the collision domain, Topo(t) represents the value of the sending and receiving nodes is 1, and the distance between the two points is less than Dmax i , will add the other node to the set P i (t) indicates that the two points can communicate normally. When a node not in the set attempts to communicate, the system will not be able to respond to the communication request and will output the reason for the failure in the log file. Step 3: Channel Arbitration and Allocation The user can configure the channel model and corresponding parameters used in the simulation at the upper layer. The optional channel models include the Friis free space propagation model, the logarithmic distance path loss model, and the logarithmic shadow fading model. The Friis free space propagation model is used in this example. This model is used to simulate the line of sight (LOS) path loss generated in a free space environment. There is no object that absorbs, diffracts, reflects, or changes any other characteristics of the radiated wave. After the signal passes through the model, the RSSI during the transmission process will be calculated. The calculation process is described in step 5. The physical layer contains a channel arbitrator to monitor the occupancy of different channel types globally. When the corresponding channel is idle, the signals to be sent in the waiting queue will be taken out in turn, and channels will be allocated to nodes; Step 4: Listen to the channel and send data: The node receives the sending request and data from the upper layer and keeps listening to the channel. If the channel becomes idle, it waits for a DIFS time and prepares to fall back. According to the number of backoff times, the backoff window size CW of the node at this time is obtained i (t). Randomly obtain a backoff integer value Num in the backoff window and wait for Num basic backoff time slots, that is, T = Num*T slot For example, when no backoff is performed, the minimum backoff window value is taken, that is, CW i (t)=16, and Num is a random integer satisfying the interval [0,16]. If the channel becomes busy during the waiting process, the system will back off and suspend. If the channel is idle and the backoff time countdown is 0, the RTS / CTS interaction begins. After the interaction is successful, data transmission begins. Step 5: Calculate the packet loss rate of the network link According to the set transmission channel model, the transmission gain G s (i) Transmit power P s (i) and receiving gain G r (i), the frequency band between nodes and the distance d between the sending and receiving nodes i,j , the rssi during the transmission process can be calculated. rssi=G r (i)+G s (i)+P s (i)-C The constant C is obtained from the channel model, transmission frequency band and node distance. After converting rssi into half dB value, the packet loss rate of the node transmission process can be obtained by looking up the generated SNR-BER comparison table. For example, in this example, rssi = -40dB is calculated, and the packet loss rate is 0.5% by looking up the table. Step 6. Simulate node update log Each simulation node has a separate log file to record the communication history of the node. If the node has sending or receiving behavior at time t0, whether backoff occurs, whether the transmission is successful, and the corresponding packet loss rate will be output in the log file for users to call and view the simulation results. Step 7: Determine whether the total simulation time has been reached The simulation system will count the running time of this time. If the set running time is reached, the simulation ends. Otherwise, each node continues to try to compete for the channel for communication.

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