Integrated chip power failure test method and system, and storage medium

Abstract

The invention provides an integrated chip power failure test method and system and a storage medium, and relates to the technical field of memories. The method is applied to the power-on device, the power-on device is provided with a wiring terminal with a plurality of power supply channels, and the method comprises the steps that the physical state of each power supply channel is set to be disconnected; each product to be tested is integrated with an integrated chip; sequentially traversing each product to be tested in the current round; the power supply channel corresponding to the traversed to-be-tested product is switched on for the corresponding power-on test duration and then is switched off, so that the power-on test duration of the traversed to-be-tested product reaches the corresponding power-on test duration; after each to-be-tested product completes the current round of traversal, the next round of traversal is carried out on each to-be-tested product again according to the test sequence, and the power-on test durations obtained by each round of the same to-be-tested product are different; the automatic endpoint test can be simultaneously carried out on a plurality of to-be-tested products, the test result of the performance of the to-be-tested products is more reliable, and the efficiency is higher.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of memory technology, and in particular to a method, system, and storage medium for power-off testing of an integrated chip. Background Art

[0002] Integrated chips (such as memory chips, power management chips, etc.) are core components of high-voltage power products, and their performance seriously affects the user experience of their application products. Therefore, in order to ensure the high reliability of integrated chips, power-off tests are often performed on the products to which they are applied during the startup phase while testing the performance of the chips themselves. For example, products powered by 12V~24V power supplies such as OTT, TV, and projectors all have integrated chips. By performing power-off tests on high-voltage power products such as OTT and TV during the startup phase, the performance of integrated chips can be better evaluated. However, in the actual testing process, timing relays are often used to manually test each high-voltage power product, and timing relays can often only be tested for a fixed duration, resulting in low reliability and low test efficiency. Therefore, there is an urgent need for a method to achieve efficient testing of integrated chips and improve the reliability of test results. Summary of the invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims. The embodiments of the present application provide a method, system, and storage medium for integrated chip power-off testing, which can achieve efficient testing of chips and improve the reliability of test results.

[0004] In a first aspect, a method for power-off testing of an integrated chip according to an embodiment of the present application is applied to a power-on device, wherein the power-on device is provided with a wiring terminal, and a plurality of power supply channels are provided on the wiring terminal; the method comprises: Setting the physical state of each power supply channel to disconnected, so that the products to be tested connected to each power supply channel are in a power-off state; wherein each of the products to be tested is integrated with an integrated chip; According to the preset test sequence, each of the products to be tested is traversed in the current round; Obtain the power-on test duration of each product to be tested traversed in the current round, and turn on the power supply channel corresponding to the traversed product to be tested for the corresponding power-on test duration and then disconnect it, so that the power-on test duration of the traversed product to be tested reaches the corresponding power-on test duration; After each of the products to be tested completes the current round of traversal, the next round of traversal is performed again on each of the products to be tested according to the test order, wherein the power-on test duration obtained in the current round of traversal for the same product to be tested is different from the power-on test duration obtained in the previous round of traversal.

[0005] In a second aspect, a system for power-off testing of an integrated chip provided according to an embodiment of the present application includes a power-on device; wherein the power-on device includes: A wiring terminal, wherein a plurality of power supply channels are arranged on the wiring terminal; a first end of each of the power supply channels is connected to a power supply, a second end of each of the power supply channels supports connection to a product to be tested, and each of the products to be tested is integrated with an integrated chip; A control module, wherein the control module executes any method of the first aspect.

[0006] In a third aspect, according to an embodiment of the present application, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the method for power-off testing of an integrated chip described in any one of the first aspects is implemented.

[0007] The above-mentioned embodiments of the present application have at least the following beneficial effects: multiple products to be tested can be connected to the power supply through the corresponding power supply channels through the wiring terminals. At this time, by controlling the on and off of each power supply channel connected to the products to be tested, the products to be tested can be automatically powered on and off. And through the program control method, it is more flexible to perform different power-on test durations on different products to be tested, and the performance reliability of the integrated chip can be further ensured. Therefore, compared with the related art, the embodiments of the present application can realize automatic testing of multiple products to be tested with different power-on test durations, and the test is more flexible and the test efficiency is higher. At this time, the test results of the performance of the products to be tested are more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0009] Figure 1 It is a structural schematic diagram of an embodiment of a system for integrated chip power-off testing provided by the present application; Figure 2 It is a flow chart of the integrated chip power-off test method provided by the present application; Figure 3 It is a test process schematic diagram of an embodiment of the integrated chip power-off test method provided by the present application; Figure 4 is a test process schematic diagram of another embodiment of the integrated chip power-off test method provided by the present application; Figure 5 It is a schematic diagram of the hardware structure of the device corresponding to the integrated chip power-off test method provided in this application. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art belonging to the technical field of the present application. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. The terms "first", "second", "third", "fourth", etc. (if present) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order.

[0012] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0013] Reference Figure 1 As shown, according to an embodiment of the present application, a system for integrated chip power-off testing includes a power-on device; wherein the power-on device includes: A wiring terminal having a plurality of power supply channels arranged thereon; a first end of each power supply channel being connected to a power supply, a second end of each power supply channel supporting connection to a product to be tested, and each product to be tested being integrated with an integrated chip; Control module, the control module performs the following steps: Setting the physical state of each power supply channel to disconnected so that the products to be tested connected to each power supply channel are in a power-off state; wherein each product to be tested is integrated with an integrated chip; According to the preset test sequence, traverse the current round of each product to be tested; Obtain the power-on test duration of each product under test traversed in the current round, turn on the power supply channel corresponding to the traversed product under test for the corresponding power-on test duration and then disconnect it, so that the power-on test duration of the traversed product under test reaches the corresponding power-on test duration; After all products under test have completed the current round of traversal, the next round of traversal is performed again on each product under test in the test order, wherein the power-on test duration obtained in the current round of traversal for the same product under test is different from the power-on test duration obtained in the previous round of traversal.

[0014] It is understandable that the products to be tested are high voltage power products such as OTT and TV; the products to be tested on the same terminal block have the same type of integrated chips.

[0015] It is understandable that the embodiment of the present application does not limit the number of connection terminals, nor does it limit the number of power supply channels on the connection terminals. Those skilled in the art can selectively set according to actual needs.

[0016] The embodiments of the present application do not limit how to realize the conduction and disconnection of each power supply channel. For example, a relay or switch can be set for each power supply channel, so that the conduction and disconnection of each power supply channel can be realized. When the power supply channel is turned on, the power supply can provide power to the product under test through the turned-on power supply channel, and the product under test can be powered on normally.

[0017] The power-on test duration represents the duration of the chip startup phase, so that power-off testing can be performed on each product under test during the startup phase.

[0018] The embodiments of the present application do not limit the number of test rounds, and those skilled in the art can selectively set them according to actual needs, such as setting the cumulative test duration or the cumulative number of tests. When one of the above is met, the power-on test of the product to be tested corresponding to the integrated chip can be terminated. After the power-on test is completed, if the product to be tested can still start normally, it means that the integrated chip is normal and meets the performance requirements.

[0019] The test sequence can be selectively set according to actual needs, and the embodiments of the present application do not limit it.

[0020] The duration of power-on tests in different rounds for the same product under test is different, so that step-by-step power-on tests can be performed on each product under test.

[0021] It is understandable that the control module may be an MCU or a PLC chip, and after the above method is burned into it in a program form, power-on testing of multiple products to be tested can be implemented.

[0022] It is understandable that the type of the product to be tested connected to each power supply channel is different.

[0023] By setting the type of each product to be tested to be different, the performance of the same type of integrated chip applied to different products can be further ensured, thereby further ensuring the reliability of the test results.

[0024] For example, refer to Figure 1 As shown, there are n products to be tested, namely product 1 to product n to be tested, the live wires of product 1 to product n to be tested are electrically connected to the power supply through the wiring terminals, the control module is electrically connected to the wiring terminals, and the control module controls the conduction state of the power supply channels of the wiring terminals connected to product 1 to product n to be tested respectively, so that product 1 to product n to be tested are turned on in sequence and the conduction time can be set according to program changes, thereby more flexibly realizing the power-on test of each product to be tested in the startup stage.

[0025] Reference Figure 2 As shown, according to a method for power-off testing of an integrated chip in an embodiment of the present application, the method is applied to a power-on device, the power-on device is provided with a wiring terminal, and a plurality of power supply channels are provided on the wiring terminal; the method comprises: Step S100, setting the physical state of each power supply channel to disconnect, so that the products to be tested connected to each power supply channel are in a power-off state; wherein each product to be tested is integrated with an integrated chip; Step S200: traverse the current round of each product to be tested according to a preset test sequence; Step S300, obtaining the power-on test duration of each product to be tested traversed in the current round, turning on the power supply channel corresponding to the traversed product to be tested for the corresponding power-on test duration and then disconnecting it, so that the power-on test duration of the traversed product to be tested reaches the corresponding power-on test duration; Step S400: After all products under test have completed the current round of traversal, the next round of traversal is performed again on each product under test in the test order, wherein the power-on test duration obtained by the same product under test in the current round of traversal is different from the power-on test duration obtained in the previous round of traversal.

[0026] Therefore, multiple products to be tested can be connected to the power supply through the corresponding power supply channels through the wiring terminals. At this time, by controlling the on and off of each power supply channel connected to the products to be tested, the products to be tested can be automatically powered on and off. And through the program control method, it is possible to more flexibly implement different power-on test durations for different products to be tested without changing the system connection relationship, thereby further ensuring the performance reliability of the integrated chip. Therefore, compared with the related art, the embodiment of the present application can realize automatic testing of multiple products to be tested with different power-on test durations, and the test is more flexible and efficient. At this time, the test results of the performance of the products to be tested are more reliable.

[0027] When the physical state of the power supply channel is disconnected, the product under test is disconnected from the power supply, so that each product under test can be in a power-off state in the initial state.

[0028] When starting the test, each product to be tested is tested one by one to ensure that the products to be tested do not affect each other, and the test results are more reliable. The test sequence can be selectively set according to actual needs, such as according to the number of the power supply channel or the number of the product to be tested. In this regard, the embodiment of the present application does not limit the test sequence.

[0029] When the power supply channel is turned on, the power supply can supply power to the product under test through the turned-on power supply channel, and the product under test starts power-on testing.

[0030] The power-on test duration is used to ensure that the product to be tested is in the power-on stage. The embodiment of the present application can set the power-on test duration according to actual needs. The power-on test duration of each product to be tested can be set differently or the same. In this regard, the embodiment of the present application does not limit how to set the power-on test duration.

[0031] The embodiment of the present application does not impose any restrictions on how to set the power-on test duration of each product to be tested in each round. It can be set in a fixed step-by-step manner. For example, an initial power-on test duration is set, and each time a new round of power-on test is performed, a fixed step is added to the power-on test duration of the previous round to obtain the power-on test duration of the current round.

[0032] It is understandable that the embodiments of the present application do not limit the termination conditions for whether to terminate the power-on test of all products to be tested. Technical personnel in this field can selectively set it according to actual needs, such as the number of test rounds is greater than the preset number of rounds, such as the cumulative duration of the test is greater than the preset duration.

[0033] For example, refer to Figure 3 As shown in the figure, taking the products to be tested as Y001, Y002, Y003, and Y004 as an example, the power-on test duration of each product to be tested is the same in the same round of power-on test. Figure 3 As shown, during the first round of power-on test, the power-on test duration of each product to be tested is set to t1, and during the second round of power-on test, the power-on test duration of each product to be tested is set to t2; during the first round of power-on test, firstly, the power supply channel corresponding to Y001 is closed to power on Y001, and Y001 is disconnected after t1 to power off Y001; then the same operation is performed on Y002, and when Y004 is also powered on for t1, the first round of testing is completed, and at this time, the second round of power-on test is started, and during the second round of power-on test, the test is re-started from Y001, as shown in FIG. Figure 3 As shown in the figure, the power-on test duration of Y001, Y002, Y003, and Y004 is all t2, and t2 is different from t1. This process is repeated until Y001, Y002, Y003, and Y004 all meet the preset test stop conditions.

[0034] It is understandable that, according to the preset test sequence, each product to be tested is traversed in the current round, including: Get the traversal time interval of the current round; the traversal time intervals of different rounds are different; In the current round, according to the test sequence, at each traversal time interval, the product under test that has not been powered on is regarded as the product under test traversed at the current moment.

[0035] It is understandable that the traversal time interval of each round is greater than the power-on test duration. At this time, by setting the traversal time interval, it can be ensured that each product to be tested will wait for a period of time after the corresponding power-on test duration is powered on before disassembling and testing the next product to be tested, thereby reducing the mutual influence between the products to be tested.

[0036] It is understandable that, according to the preset test sequence, each product to be tested is traversed in the current round, including: Get the pre-configured script file; Start reading from the first line of the script file in sequence to obtain the test instructions for each product to be tested.

[0037] By configuring the script, you can make the test more flexible. In this case, the test order is the order of the test instructions in the script.

[0038] It is understandable that obtaining the power-on test duration of each product to be tested traversed in the current round, and switching on the power supply channel corresponding to the traversed product to be tested for the corresponding power-on test duration and then disconnecting it includes: For each test instruction read, a connection instruction is issued to the target power supply channel corresponding to the test instruction, so as to supply power to the corresponding connected product under test through the target power supply channel; For each test instruction read, execute the power-on test duration waiting instruction in the test instruction; For each test instruction read, after the power-on test time waits for the instruction to be executed, a disconnection instruction is sent to the target power supply channel to make the target power supply channel stop supplying power to the corresponding product under test.

[0039] The power-on test duration waiting instruction defines the power-on test duration of the target power supply channel, which is used to make the control module wait for the power-on test duration before executing subsequent instructions.

[0040] It is understood that the method further comprises: Get the duration threshold; When the accumulated duration of the power-on test of each product under test meets the duration threshold, the power supply function of each product under test is verified to obtain a test result.

[0041] The power supply function verification is to keep the product under test powered on to determine whether the product under test can start successfully.

[0042] It is understood that the method further comprises: Change the connection relationship between each product under test and the power supply channel; and jump to the step of setting the physical state of each power supply channel to disconnected.

[0043] By changing the connection relationship between each product under test and the power supply channel, a more comprehensive test can be performed on the product under test, and the test result is more reliable.

[0044] It is understandable that the power-on device is also provided with an indicator light; before traversing the current round of each product to be tested according to a preset test sequence, the method further includes: Turn on the indicator light; When the accumulated duration of the power-on test of each product to be tested meets the duration threshold, the indicator light is turned off.

[0045] The embodiment of the present application does not limit the color of the lighted indicator light, such as red when lit, or green. By setting the indicator light, the tester can more intuitively determine whether the test is finished, and then start the performance test of the product to be tested.

[0046] For example, refer to Figure 4 As shown, the test method of the embodiment of the present application is described, wherein the wiring terminal can be connected to at least 8 products to be tested at the same time, and a maximum of 16 products to be tested. When multiple products to be tested are powered on step by step, the signal indicator light is turned on. At this time, the signal indicator light is red, and then the test script written using PCL software is loaded, wherein the power-on test duration in the test script is 1S, 2S~10S, and 10S~60S as a cycle. Among them, the power supply supports a supply voltage of 12~24V. The wiring terminal is 16-way, and the interface order of 1~16 is Y000~Y015. According to the set program, step by step power is turned on for one cycle, and then enter the next cycle; then the steps for each cycle are as follows: Step 1, starting from Y001, each product i to be tested is regarded as product i to be tested; for each product i to be tested, power is continuously supplied to product i to be tested for a certain period of time and then disconnected; when all products to be tested have completed a round of testing, jump to step 2; Step 2: Determine whether the number of test rounds meets the preset round number threshold, if not, jump to step 3; if yes, jump to step 4; Step 3: Update the power-on test duration of each product to be tested and jump to step 1; Step 4: Initialize the power-on test duration and the number of test rounds and jump to step 1 to start the next cycle.

[0047] Through the above steps, a stepper power-on device can be formed by using a power supply 220V to 12V~24V voltage regulator, a control module, and a terminal block combination. The stepper power-on program code can be programmed using PCL programming software and burned into the control module to implement a stepper power-on test of 8~16 products to be tested. When different types of products with the same working voltage (OTT, TV, projector) are connected after the test is completed, if the product still steps on the device normally, it means that the requirements are met.

[0048] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above method when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0049] See also Figure 5 , Figure 5 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes: The processor 601 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; The memory 602 may be a NAND flash, and the relevant program code is stored in the memory 602, and is called by the processor 601 to execute the method of the embodiment of the present application; Input / output interface 603, used to implement information input and output; Communication interface 604, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.); A bus 605 that transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604); The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0050] An embodiment of the present application further provides a computer-readable storage medium, which is a computer-readable storage medium that stores a computer program. When the computer program is executed by a processor, the above method is implemented.

[0051] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0052] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0053] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0054] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0055] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0056] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0058] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0059] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0061] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0062] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for power-off testing of an integrated chip, characterized in that: Applied to a power-on device, the power-on device is provided with a wiring terminal, and the wiring terminal is provided with a plurality of power supply channels; the method comprises: Setting the physical state of each power supply channel to disconnected, so that the products to be tested connected to each power supply channel are in a power-off state; wherein each of the products to be tested is integrated with an integrated chip; According to the preset test sequence, each of the products to be tested is traversed in the current round; Obtain the power-on test duration of each product to be tested traversed in the current round, and turn on the power supply channel corresponding to the traversed product to be tested for the corresponding power-on test duration and then disconnect it, so that the power-on test duration of the traversed product to be tested reaches the corresponding power-on test duration; After each of the products to be tested completes the current round of traversal, the next round of traversal is performed again on each of the products to be tested according to the test order, wherein the power-on test duration obtained in the current round of traversal for the same product to be tested is different from the power-on test duration obtained in the previous round of traversal.

2. The method for power-off testing of an integrated chip according to claim 1, characterized in that: The traversal of the current round of each of the products to be tested according to the preset test sequence includes: Get the traversal time interval of the current round; the traversal time intervals of different rounds are different; In the current round, according to the test sequence, at each traversal time interval, the products to be tested that have not been powered on are taken as the products to be tested that are traversed at the current moment.

3. The method for power-off testing of an integrated chip according to claim 1, characterized in that: The traversal of the current round of each of the products to be tested according to the preset test sequence includes: Get the pre-configured script file; The script file is read sequentially starting from the first line to obtain the test instructions of each product to be tested.

4. The method for power-off testing of an integrated chip according to claim 3, characterized in that: The step of obtaining the power-on test duration of each product to be tested traversed in the current round, and switching on the power supply channel corresponding to the traversed product to be tested for the corresponding power-on test duration and then disconnecting it, comprises: For each test instruction read, a connection instruction is issued to the target power supply channel corresponding to the test instruction, so as to supply power to the corresponding connected product to be tested through the target power supply channel; For each test instruction read, executing the power-on test duration waiting instruction in the test instruction; For each test instruction read, after the power-on test duration waiting instruction is executed, a disconnection instruction is sent to the target power supply channel, so that the target power supply channel stops supplying power to the corresponding product to be tested.

5. The method for power-off testing of an integrated chip according to claim 1, characterized in that: The method further comprises: Get the duration threshold; When the accumulated duration of the power-on test of each of the products to be tested meets the duration threshold, the power supply function of each of the products to be tested is verified to obtain a test result.

6. The method for power-off testing of an integrated chip according to claim 5, characterized in that: The method further comprises: The connection relationship between each of the products to be tested and the power supply channel is changed; and the process jumps to the step of setting the physical state of each power supply channel to disconnected.

7. The method for power-off testing of an integrated chip according to claim 5, characterized in that: The power-on device is also provided with an indicator light; before traversing the current round of each of the products to be tested according to a preset test sequence, the method further includes: Lighting up the indicator light; When the accumulated duration of the power-on test of each of the products to be tested meets the duration threshold, the indicator light is turned off.

8. A system for integrated chip power-off testing, characterized in that: The invention comprises a power-on device; wherein the power-on device comprises: A wiring terminal, wherein a plurality of power supply channels are arranged on the wiring terminal; a first end of each of the power supply channels is connected to a power supply, a second end of each of the power supply channels supports connection to a product to be tested, and each of the products to be tested is integrated with an integrated chip; A control module, wherein the control module executes the method according to claim 1.

9. The system for power-off testing of an integrated chip according to claim 8, characterized in that: The type of the product to be tested connected to each of the power supply channels is different.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for power-off testing of an integrated chip according to any one of claims 1 to 7 is implemented.

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