Inductor for semiconductor package substrate

Abstract

A coaxial magnetic inductor structure for semiconductor package applications is provided. The coaxial magnetic inductor may be located in a semiconductor package core, and the semiconductor package core may be composed of, for example, an amorphous solid glass material. A method of fabricating a coaxial magnetic inductor in a package substrate core is also provided.

Description

Technical Field

[0001] The description relates generally to packages for semiconductor chips and, more particularly, to inductors for semiconductor chip package substrates. Background Art

[0002] Semiconductor chips that are critical to smart devices and systems (e.g., personal computers, laptops, tablets, phones, servers, and other consumer and industrial products and systems) are packaged so that power can be delivered, data can be input and output, heat can be dissipated, and the chips can be protected from environmental challenges. The packaging of semiconductor chips is extremely important to optimize the performance life of the chips.

[0003] Packaging semiconductor devices presents many challenges, and these challenges are magnified as devices become smaller and performance requirements increase. Challenges include, for example, unwanted material interactions, precision and scaling requirements, thermal management, power delivery requirements, limited fault tolerance, and material and manufacturing costs. In addition, power delivery requirements for chips (e.g., such as those used in data centers) are expected to increase two to three times over the next few years. Systems that can support the increased power delivery requirements are needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings are provided to aid in understanding the present invention. The accompanying drawings may include diagrams and illustrations of exemplary structures, components, data, methods, and systems. To facilitate explanation and understanding of these structures, components, data, methods, and systems, the accompanying drawings are not exhaustive detailed descriptions. Therefore, the accompanying drawings should not be construed as showing the entire boundaries of possible structures, components, data, methods, and systems without departing from the scope of the present invention.

[0005] Figure 1 Exemplary inductor structures in sections of a package substrate are provided.

[0006] Figure 2 Another exemplary inductor structure in a section of a package substrate is shown.

[0007] Figure 3 Shows Figure 1 and 2 Dimensions of an exemplary inductor structure.

[0008] Figure 4 Shows Figure 1 and 2 Cross-sectional view of an exemplary inductor structure.

[0009] Figure 5A and 5B An exemplary fabrication process for an inductor structure is described.

[0010] Figure 6 Additional exemplary fabrication processes for inductor structures are shown.

[0011] Figure 7 A flow chart of an example of a process for manufacturing a coaxial magnetic inductor is provided.

[0012] Figure 8 Example package assemblies including coaxial magnetic inductors are provided.

[0013] Fig. 9 An exemplary computing system in which a coaxial magnetic inductor is employed is provided.

[0014]

[0013] What follows is a description of certain details and implementations, including a non-limiting description of the accompanying drawings that illustrate some examples and implementations. DETAILED DESCRIPTION

[0015] Reference to one or more examples should be understood as describing a specific feature, structure or characteristic included in at least one embodiment of the present invention. The phrase "an example" or "example" does not necessarily refer to the same example or embodiment. Any aspect described herein can potentially be combined with any other aspect or similar aspect described herein, regardless of whether these aspects are described with respect to the same drawings or elements.

[0016] The words "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but are separated by one or more elements, but they can still cooperate or interact with each other, for example, physically, magnetically or electrically.

[0017] The words "first", "second", etc. do not indicate order, quantity, or importance, but are used to distinguish one element from another. The words "one" and "an" herein do not indicate a limitation of quantity, but rather indicate the presence of at least one of the referenced items. The term "following" or "after" may indicate immediately following or following some other one or more events. Other sequences of operations may also be performed according to alternative embodiments. Furthermore, additional operations may be added or removed depending on the particular application.

[0018] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is often used to indicate that an element or feature can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language should be understood not to imply that certain embodiments require that at least one of X, at least one of Y, or at least one of Z each be present.

[0019] The flowcharts as shown herein provide examples of sequences of various process actions. The flowcharts may indicate operations to be performed by software or firmware routines and / or physical operations. Although shown in a particular sequence or order, the order of the actions may be modified unless otherwise stated. Therefore, the figures shown should be understood only as examples, the process may be performed in a different order, and some actions may be performed in parallel. In addition, one or more actions may be omitted, and not all embodiments will perform all actions. The physical operations may be performed by, for example, semiconductor processing equipment.

[0020] To the extent that various computer operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Software content may be provided via an article having content stored thereon, or via a method of operating a communication interface to send data via a communication interface. A machine-readable storage medium may enable a machine to perform the functions or operations described, and includes any mechanism for storing information in a tangible form accessible by a machine (e.g., a computing device), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices). A communication interface includes any mechanism for communicating with another device via an interface, such as a hardwired, wireless, or optical medium, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller.

[0021] Terms such as chip, die, IC (integrated circuit) chip, IC die, or semiconductor chip may be used interchangeably and refer to a semiconductor device including an integrated circuit.

[0022] The terms "package", "package", "IC package" or "chip package", "microelectronic package" or "semiconductor chip package" are interchangeable and generally refer to an enclosed carrier of one or more dies, wherein the dies are attached to a package substrate and encapsulated. The package substrate provides electrical interconnection between the die(s) and other dies and / or a motherboard or other printed circuit board for I / O (input / output) communications and power delivery. For example, a package with multiple dies may be a system in a package.

[0023] The package substrate generally includes a dielectric layer or structure with conductive structures on and / or embedded in the dielectric layer or structure. Other structures or devices within the package substrate are also possible. The semiconductor package substrate may have a core or be coreless.

[0024] "Core" or "package core" generally refers to a layer that is typically embedded within a package substrate. The core can provide structure or rigidity to the package substrate. The core is an optional feature of the package substrate. The core can be a dielectric organic or inorganic material and can have conductive vias extending through the layers. The package core can, for example, include glass (e.g., aluminosilicates, borosilicates, aluminoborosilicates, silicon dioxide, and fused silica), silicon, silicon nitride, silicon carbide, gallium nitride, or aluminum oxide. In some examples, the core material is a glass fiber reinforced organic resin, such as an epoxy resin. Another example package substrate core is FR4 (woven glass fiber reinforced epoxy resin).

[0025] In another example of a package substrate core, the substrate core is a glass core comprising an amorphous solid glass material. The glass substrate core may include glass (e.g., aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and molten silica), which may further optionally include one or more of the following: Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and / or Zn. In other examples of glass cores, the glass may include silicon (Si) and oxygen (O), and optionally any one or more of the following: aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, the glass package substrate core includes at least 23% silicon, at least 26% oxygen, and at least 5% aluminum by weight. The package substrate core composition may vary depending on the product application.

[0026] Power delivery networks for semiconductor chips typically include a voltage regulator (VR) as a voltage regulation circuit. In one example, the VR is integrated into the semiconductor chip and includes a portion of the power delivery network. These integrated voltage regulators can be, for example, fully integrated voltage regulators (FIVRs). Voltage regulation systems including integrated voltage regulators (e.g., FIVRs) can be employed in chips used in data centers and elsewhere. Inductors located in semiconductor chip packages can be an important part of a power delivery network (e.g., a power delivery network including an integrated voltage regulator).

[0027] Figure 1 An exemplary coaxial magnetic inductor structure is shown. Figure 1, a section of a package substrate 100 is shown. The section of the package substrate 100 includes a package substrate core 105, and includes an inductor structure having a conductive through-core via 110, an optional conductive region seed layer 115, an adhesion layer 120, a polymer layer 125, a magnetic layer 130, a magnetic region seed layer 135, and a package substrate core liner 140. In an exemplary package substrate, the package substrate core 105 is a glass core including an amorphous solid glass material as described herein. The package substrate core liner 140 can improve the adhesion of subsequent layers to the package substrate core. Although for simplicity, layers 115, 120, 125, 130, 135 and 140 are shown as having approximately the same relative thickness, the thicknesses of the layers may alternatively be different relative thicknesses for some or all of the layers. Figure 3 and the accompanying description provides Figure 1 Some exemplary device dimensions for a coaxial magnetic inductor structure.

[0028] exist Figure 1In the present invention, the conductive region 110 is composed of, for example, a metal. The metal may be copper, silver, gold, or a combination thereof. Other metals or conductive materials may also be used for the conductive region 110. The optional conductive region seed layer 115 is composed of, for example, copper, ruthenium (Ru), a copper alloy, and / or an oxide of Cu, Cu-Ti, Cu-Ta, and / or Cu-Ru (i.e., a material including Cu, Cu-Ti, Cu-Ta, and / or Cu-Ru and a certain amount of oxygen). The copper alloy may be, for example, an alloy of copper and ruthenium, tantalum, and / or titanium. Other materials are possible for the optional conductive region seed layer 115. The adhesion layer 120 is composed of, for example, Ti or one of the materials described herein for the optional conductive region seed layer 115. In the case where the materials of the adhesion layer 120 and the conductive region seed layer 115 are the same, these layers are substantially the same, and either layer may be considered optional. For simplicity, the conductive region seed layer 115 has been described herein as being optional, although the adhesion layer 120 or the conductive region seed layer 115 may be considered optional depending on the choice of material. The polymer layer 125 is composed of, for example, polyparaxylene and / or an aliphatic or aromatic polymer. Useful aliphatic or aromatic polymers include polyvinyl and polypyrimidine. Other polymer materials are also possible, and one function that the polymer layer can play is to reduce the mechanical stress in the multilayer coaxial magnetic inductor structure. Materials that are compatible with the resulting coaxial magnetic inductor structure and manufacturing process and provide mechanical stress reduction are useful. In some examples, the polymer layer 125 is optional, depending on the mechanical stress state of the semiconductor package component. The magnetic layer 130 is composed of a magnetic material, such as a high permeability alloy. In an example of the present invention, the high permeability alloy has a permeability (μ) of 5 to 100. Useful magnetic materials include CoNiFeX, CoFe, CoFeX, CoW, CoFeW, NiFe and NiFeX, where X is S, O, P, B and / or V. The magnetic region seed layer 135 is composed of, for example, Ru, Cu or another atomic layer deposition compatible material. Materials that can be used for the package substrate core liner 140 include, for example, Ti, Cr, TiCr and TiN. Additional materials that can be used for the package substrate core liner layer 140 include polymers, such as those described herein with respect to the polymer layer 125. The section of the package substrate 100 also includes an organic layer 150, such as an organic buildup layer. The dashed lines and arrows labeled "i" show Figure 4 Cross-sectional slices and viewing directions of the device views shown in .

[0029] Figure 2 Additional exemplary coaxial magnetic inductor devices are shown. Figure 2, the illustrated section of the package substrate 200 includes a package substrate core 105 and includes an inductor structure having a conductive through-core via 110, an optional conductive region seed layer 215, an adhesion layer 220, a polymer layer 225, a magnetic layer 130, a magnetic region seed layer 135, and a package substrate core liner layer 140. The illustrated section of the package substrate 200 has the same features as described herein. Figure 1 The description and useful exemplary materials of the parts with the same reference numerals as those of the parts described also apply to Figure 2 In addition, coaxial layers 215, 220, and 225 correspond to layers 115, 120, and 125, respectively, and the descriptions and exemplary materials used herein for layers 115, 120, and 125 apply to layers 215, 220, and 225, respectively. For example, package substrate core 105 can be a glass core including an amorphous solid glass material as described herein. Similar to Figure 1 , if the materials of adhesion layer 220 and conductive region seed layer 215 are the same, then these layers are substantially the same and either one may be considered optional. Conductive region seed layer 215 has been described herein as being optional, although depending on the choice of material, adhesion layer 220 or conductive region seed layer 215 may be considered optional. Figure 2 In some examples, polymer layer 225 is also optional, depending on the mechanical stress state of the semiconductor package assembly. Although for simplicity, layers 215, 220, 225, 130, 135 and 140 are shown as having approximately the same relative thickness, for some or all layers, the thickness of the layers can alternatively be different relative thicknesses. Figure 3 and the accompanying description provides Figure 2 Some exemplary device dimensions for a coaxial magnetic inductor device. The dashed line and arrow labeled "ii" show Figure 4 Section slices and viewing directions for the views shown in .

[0030] Figure 3 An illustration of the dimensions of a portion of an exemplary coaxial magnetic inductor structure in a package substrate core is provided. Figure 1 The exemplary device of has been used for some device illustrations, but the size is not Figure 2 Examples are also useful. Figure 2 In FIG. 1 , coaxial layers 215, 220, and 225 extend over package substrate core 105, however, the dimensions shown for the areas corresponding to coaxial layers 115, 120, and 125 apply to similarly positioned areas of layers 215, 220, and 225, respectively. Although some exemplary dimensions are provided here, other dimensions are possible. Figure 3, a section of a package substrate 300 is shown, which includes a package substrate core 105 and also includes a portion of an inductor structure having a conductive through-core via 110, an optional conductive region seed layer 115, an adhesion layer 120, a polymer layer 125, a magnetic layer 130, a magnetic region seed layer 135, and a package substrate core liner layer 140. An exemplary thickness of the package substrate core 105 ( Figure 3 The double-ended arrow marked "a" in FIG. 1 ) ranges between 50 and 2000 microns. An exemplary end diameter of a through-core via ( Figure 3 The diameter of the through-core via (double-ended arrow marked "b" in FIG. 1 ) ranges between 20 and 500 microns. Figure 3 The double-ended arrow marked "c" in FIG. 1 ) ranges between 20 and 500 microns. An exemplary end segment diameter range of the conductive region 110 ( Figure 3 The double-ended arrow marked "d" in FIG. 1 is between 10 and 475 micrometers. An exemplary mid-segment diameter range of the conductive region 110 ( Figure 3 The double-ended arrow marked "e" in FIG. 1 is 10 to 475 micrometers. The exemplary pad area diameter range of the conductive region 110 is ( Figure 3 The double-ended arrow marked as "f" in FIG. 1 is between 20 and 500 microns. An exemplary end width range of the conductive region seed layer 115 ( Figure 3 The double-ended arrow marked as "g" in FIG. 1 is 10 nm to 50 microns. The exemplary end width range of the adhesion layer 120 ( Figure 3 The double-ended arrow marked as "h" in FIG. 1 is 10 nm to 50 microns. The exemplary end width range of the polymer layer 125 ( Figure 3 The double-ended arrow marked as "j" in FIG. 1 is 10 nm to 50 microns. The exemplary end width range of the magnetic layer 130 ( Figure 3 The double-ended arrow marked as "k" in FIG. 1 is 10 nm to 50 microns. The exemplary end width range of the magnetic region seed layer 135 ( Figure 3 The double-ended arrow marked as "m" in FIG. 1 is 10 nm to 50 microns. The exemplary end width range of the package substrate core liner 140 ( Figure 3 The double-ended arrow marked with "n" in the figure) is 10 nm to 50 microns.

[0031] Figure 4 Provided Figure 1 and 2 A cross-sectional view of an exemplary coaxial magnetic inductor structure. The dashed lines "i" and "ii" and the accompanying arrows show Figure 4 The illustrated section of the package substrate 400 includes a package substrate core 105 and includes an inductor structure having a conductive through-core via 110, a conductive region seed layer 115 (eg, Figure 2215), the adhesive layer 120 (as shown in Figure 2 220), polymer layer 125 (such as Figure 2 ), the magnetic layer 130 , the magnetic region seed layer 135 , and the package substrate core liner layer 140 .

[0032] Figure 5A and 5B A method for manufacturing a coaxial magnetic inductor structure (e.g., Figure 1 An exemplary manufacturing process of the coaxial magnetic inductor structure described above. Figure 5A , a segment 500 of a package substrate core 505 includes two through holes. The package substrate core 505 may be a glass substrate including an amorphous solid glass material as described herein. A package substrate liner 540 including, for example, TiN and a magnetic region seed layer 535 including, for example, Ru are then deposited by chemical vapor deposition (CVD) to produce structure 501. In structure 502, a dry film resist (DFR) 580 has been laminated to both surfaces of the package substrate core 505. The DFR 580 is exposed and developed for through-hole plating of magnetic material. In structure 503, a layer of magnetic material 530 has been plated by a plated magnetic via (PMV) process using CVD or wet metallization, and the DFR 580 has been stripped. In structure 504, layers 540 and 535 and magnetic material 530 have been removed from the surface of the package substrate core 505 by chemical mechanical polishing (CMP) and etching processes.

[0033] Figure 5A The manufacturing process in Figure 5B Continue in Figure 5B , structure 551 shows that an optional polymer layer 525 has been deposited. The polymer layer 525 can be deposited using CVD. Structure 552 shows that an adhesion layer 520 and a conductive region seed layer 515 have been deposited. The adhesion layer 520 and the conductive region seed layer 515 can be deposited using CVD or wet metallization. In addition, as described in the examples herein, the adhesion layer 520 and the conductive region seed layer 515 are the same material and layer. Structure 553 shows that the conductive region 510 is produced by, for example, a metal plating process. In structure 554, the metal cover layer and other materials have been removed from the surface of the package substrate core 505 using CMP and etching processes. The resulting structure 554 has both conductive non-magnetic through-core vias and magnetic (inductor) through-core vias. Additional processing such as lamination and via drilling processes is used to produce additional buildup layers (not shown).

[0034] Figure 6 Provided are methods for producing coaxial magnetic inductors (e.g., Figure 2 The manufacturing process of the coaxial magnetic inductor described in FIG. Figure 5BStarting with structure 552 (which can be manufactured as described herein), DFR 680 is laminated to the surface of package substrate core 505, exposed and developed to produce structure 653. Structure 654 shows the creation of conductive region 610 by, for example, a metal plating process and the removal of DFR 680 by, for example, a wet stripping process. The resulting structure 654 has both non-magnetic through-core vias and magnetic through-core vias.

[0035] Figure 7 A process for manufacturing a coaxial magnetic inductor in a package substrate core is shown. A package substrate core having a through hole is selected 700. The package substrate core can be a glass core including an amorphous solid glass material as described herein. The package substrate core liner and the magnetic region seed layer are deposited on the package substrate core and in the through hole 705. The magnetic region layer is deposited on the package substrate core and in the through hole 710. One or more processes (e.g., chemical mechanical polishing and / or etching) are performed to remove the package substrate core liner, the magnetic region seed layer, and the magnetic layer from the opposite surface of the package substrate core 715. An optional polymer layer is deposited 720. An adhesion layer and a conductive region seed layer are deposited 725. In the example of the coaxial inductor described herein, the adhesion layer and the conductive region seed layer are optionally the same material and layer. The conductive region material is deposited, and the adhesion layer and the conductive region seed layer are removed from the opposite surface of the package substrate core 730. Figure 7 Provides explanation Figure 5A-5B and 6 additional methods of manufacturing processes, and the details found in this article about these processes apply to Figure 7 .in addition, Figure 1-3 The materials, structures and explanations in and the disclosures attached hereto also apply to Figure 7 Describe the process.

[0036] Figure 8 An example cross section of a chip package assembly including a coaxial magnetic inductor in a chip package substrate is shown. The chip package substrate may include multiple coaxial magnetic inductors (one is shown). Figure 8 In the drawings, components and features are not necessarily shown relative to scale. Figure 8 In the Figure 2-4 , 6 and 7, however, any coaxial magnetic inductor described herein (e.g., Figure 1 , 3 -4, 5A-5B and 6 and the description attached thereto). Figure 8 The package structure includes a semiconductor chip 804, however, for ease of understanding, the structure shown does not include all packaging layers and features that may be present in the semiconductor chip 804 package. For example, Figure 8The terminal layer 870 shown in will not likely be the terminal surface of the packaged semiconductor chip in use, because most packages, for example, further encapsulate the semiconductor chip 804. In addition, the package structure may include additional semiconductor chips and chip interconnects (not shown). Figure 8 In the package structure shown, chip 804 is electrically coupled to the package via chip connector 807. Chip connector 807 can be a type of pin, rod, bump or conductive feature for bonding chip 804 to a package substrate and providing power and communication. In an example of the present invention, chip 804 is a chip including an integrated voltage regulator (e.g., FIVR). For clarity, only a portion of a complete chip package assembly is shown, and, for example, layers, build-up layers, metal interconnects, devices, and features have been omitted.

[0037] exist Figure 8 , the package structure has a board-side connector 880 that is electrically and communicatively attached to contacts on a board 885 (which may be, for example, a motherboard, a main board, a main circuit board, a printed circuit board, a circuit board, a system board, or a logic board). The board-side connector 880 may be a solder ball, a pin, a pad, or other type of electrical contact. The board-side connector 880 may be a ball grid array (BGA), a land grid array (LGA), or a pin grid array (PGA), or used with an LGA or PGA, or for coupling to a socket feature of a motherboard. The package structure also includes other layers, such as 875 and layer 876, which may be build-up layers, and metal interconnects 837. For example, additional metal interconnects, devices, and features (not shown) may be present in layers 875 and 876 or in additional layers (not shown). The coaxial magnetic inductor may be part of the power delivery system of chip 804.

[0038] Figure 8 The package structure further shows a non-magnetic conductive through-core via 865, which can be, for example, according to the process described herein and by Figure 6 and 7 The invention is used to produce a coaxial magnetic inductor in a package substrate core 805. The complete package structure may include a plurality of conductive through-core vias 865. The coaxial magnetic inductor includes a conductive through-core via 810, an optional conductive region seed layer 815, an adhesion layer 820, an optional polymer layer 825, a magnetic layer 845, a magnetic region seed layer 835, and a package substrate core adhesion layer 840. Figure 1-4 A description of these layers and features is provided.For example, the package substrate core 805 can be a glass core including an amorphous solid glass material as described herein.

[0039] Board (or main board, main circuit board, printed circuit board, circuit board, system board or logic board), such as Figure 8The board shown in provides electrical contacts, i.e., power delivery and communication routes. Many electronic components can be accommodated on the motherboard, including processors (central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), coprocessor, network processor, etc.), accelerators, memory controllers, application-specific integrated circuits (ASIC), interface controllers, chipsets, chip systems, dual in-line memory modules (DIMM) or RAM, non-volatile memory, power input and delivery connections, clock generators, BIOS (basic input / output system) chips, and interfaces and connectors for peripheral devices and memory storage devices. The motherboard may include a slot or other type of connector that accepts a DIMM or RAM card, a graphics card, or an expansion card. Additional connectors include, for example, a serial advanced technology attachment (SATA) port and a peripheral component interconnect (PCI) and PCIe (PCI Express) slot. Connectors for I / O devices such as peripheral devices may include, for example, high-definition multimedia interfaces (HDMI), Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire) and universal serial bus (USB) connection receivers for mice, keyboards, storage devices, displays, cameras, and other devices.

[0040] Fig. 9 It is shown that it can be combined with the following Figure 1-4 , 5A-5B and 6-8 in combination with the coaxial magnetic inductor device. Figure 8 As shown in the accompanying description, for example, one or more coaxial magnetic inductors may be included in a package, for example, for a processor, a microprocessor, an accelerator, a memory controller, and / or a package including multiple chips and / or multiple types of chips. The packaged chip may be a packaged chip including an integrated voltage regulator. The computing system employed may include a computer system related to Fig. 9 Describes features that are more, different, or fewer than those described.

[0041] The computing system 900 includes a processor 910 that provides processing, operation management, and execution of instructions for the system 900. The processor 910 may include any type of microprocessor, CPU (central processing unit), GPU (graphics processing unit), processing core, or other processing hardware that provides processing for the system 900, or a combination of processors or processing cores. The processor 910 controls the overall operation of the system 900 and may be or include one or more programmable general or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of these devices.

[0042] In one example, system 900 includes an interface 912 coupled to processor 910, which may represent a higher speed interface or high throughput interface for system components that require higher bandwidth connections (e.g., memory subsystem 920 or graphics interface component 940 and / or accelerator 942). Interface 912 represents interface circuitry, which may be a separate component or integrated onto a processor die. Where present, graphics interface 940 interfaces with a graphics component for providing a visual display to a user of system 900. In one example, the display may include a touch screen display.

[0043] The accelerator 942 may be a fixed function or programmable offload engine that can be accessed or used by the processor 910. For example, the accelerator in the accelerator 942 may provide data compression (DC) capabilities, cryptographic services such as public key encryption (PKE), passwords, hashing / authentication capabilities, decryption, or other capabilities or services. In some cases, the accelerator 942 may be integrated into a CPU socket (e.g., a connector to a motherboard (or circuit board, printed circuit board, mainboard, system board, or logic board) including a CPU and providing an electrical interface with the CPU). For example, the accelerator 942 may include a single-core or multi-core processor, a graphics processing unit, a logic execution unit single-level or multi-level cache, a functional unit that can be used to independently execute a program or thread, an ASIC, a neural network processor (NNP), a programmable control logic, and a programmable processing element such as a field programmable gate array (FPGA) or a programmable logic device (PLD). The accelerator 942 may provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units may be used for artificial intelligence (AI) or machine learning (ML) models.

[0044] The memory subsystem 920 represents the main memory of the system 900 and provides storage for code to be executed by the processor 910 or data values ​​to be used in executing routines. The memory subsystem 920 may include one or more memory devices 930, such as read-only memory (ROM), flash memory, one or more random access memories (RAM) (e.g., static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM)) and / or other memory devices, or a combination of these devices. The memory 930 stores and hosts an operating system (OS) 932, which provides a software platform for executing instructions in the system 900, and stores and hosts applications 934 and processes 936. In one example, the memory subsystem 920 includes a memory controller 922, which is a memory controller for generating commands and issuing commands to the memory 930. The memory controller 922 may be a physical part of the processor 910 or a physical part of the interface 912. For example, the memory controller 922 may be an integrated memory controller on a circuit integrated into the processor 910.

[0045] The system 900 may also optionally include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, and / or an interface bus. A bus or other signal line may couple components together communicatively or electrically, or both communicatively and electrically. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit or combination. A bus may include, for example, a system bus, a peripheral component interface (PCI) or PCI Express (PCIe), a hypertransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or a FireWire bus.

[0046] In one example, system 900 includes interface 914, which can be coupled to interface 912. In one example, interface 914 represents interface circuitry, which can include independent components and integrated circuits. In one example, user interface components or peripheral components or both are coupled to interface 914. Network interface 950 provides system 900 with the ability to communicate with remote devices (e.g., servers or other computing devices) through one or more networks. Network interface 950 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB or other wired or wireless standard-based or proprietary interface. Network interface 950 can transmit data to a device or remote device located in the same data center or rack, which can include sending data stored in a memory.

[0047] Some examples of network interface 950 are part of an infrastructure processing unit (IPU) or a data processing unit (DPU), or used by an IPU or DPU. An xPU may refer to at least an IPU, a DPU, a GPU, a GPGPU (general purpose computing on a graphics processing unit), or other processing unit (e.g., an accelerator device). An IPU or DPU may include a network interface with one or more programmable pipeline or fixed function processors to perform offloads of operations that may have been performed by a CPU. An IPU or DPU may include one or more memory devices.

[0048] In one example, system 900 includes one or more input / output (I / O) interfaces 960. I / O interfaces 960 may include one or more interface components (e.g., audio, alphanumeric, tactile / touch, or other interfaces) through which a user interacts with system 900. Peripheral interfaces 970 may include additional types of hardware interfaces, such as interfaces to semiconductor manufacturing equipment and / or electrostatic charge management equipment.

[0049] In one example, the system 900 includes a storage subsystem 980. The storage subsystem 980 includes a storage device 984, which can be or include any conventional media for storing data in a non-volatile manner, such as one or more magnetic, solid-state, and / or optical-based disks. The storage device 984 can generally be considered as "memory", although the memory 930 is generally an execution or operating memory for providing instructions to the processor 910. Although the storage device 984 is non-volatile, the memory 930 may include volatile memory (for example, if the power of the system 900 is interrupted, the value or state of the data is uncertain). In one example, the storage subsystem 980 includes a controller 982 that interfaces with the storage device 984. In one example, the controller 982 is a physical part of the interface 912 or the processor 910, or may include circuits or logic in both the processor 910 and the interface 914.

[0050] A power supply (not shown) provides power to the components of the system 900. More specifically, the power supply is typically interfaced with one or more power supplies in the system 900 to provide power to the components of the system 900.

[0051] The exemplary system may be implemented in various types of computing, smart phones, tablet computers, personal computers, and networking devices (e.g., switches, routers, racks, and blade servers, such as those employed in data center and / or server farm environments).

[0052] In addition to what is described herein, various modifications may be made to the disclosed content and embodiments of the present invention without departing from the scope of the present invention. Therefore, the illustrations and examples herein should be interpreted as illustrative rather than restrictive. The scope of the present invention should be measured only by reference to the appended claims.

Claims

1. A microelectronic device comprising: a package substrate core, wherein the package substrate core comprises an amorphous solid glass material, and wherein the package substrate core has through-core vias; a conductive region, the conductive region being in the through-core via; and A plurality of layers are between the conductive region and the package substrate core, wherein the plurality of layers include an adhesion layer, a magnetic layer, and a package substrate core liner layer. 2 . The microelectronic device of claim 1 , further comprising a polymer layer between the conductive region and the package substrate core.

3. The microelectronic device according to claim 1, wherein: The plurality of layers further includes a conductive region seed layer between the conductive region and the package substrate core.

4. The microelectronic device according to claim 1, wherein: The plurality of layers also includes a magnetic region seed layer.

5. The microelectronic device according to claim 1, wherein: The magnetic layer includes CoNiFeX, CoFe, CoFeX, CoW, CoFeW, NiFe or NiFeX.

6. The microelectronic device according to claim 2, wherein: The polymer layer includes an aliphatic or aromatic polymer.

7. The microelectronic device according to claim 2, wherein: The polymer layer includes polyparaxylene, polypyrimidine polymer or polyethylene polymer.

8. The microelectronic device according to claim 1, wherein: The magnetic layer has a thickness between 10 nm and 5 micrometers.

9. The microelectronic device according to claim 1, wherein: The package substrate core includes aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide or fused silicon dioxide.

10. The microelectronic device according to claim 1, wherein: The package substrate core includes aluminosilicate, borosilicate, aluminoborosilicate, silica or fused silica, and wherein the package substrate core also includes Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, Zn or a combination thereof.

11. A microelectronic assembly comprising: Semiconductor chips; a semiconductor package substrate, wherein the semiconductor chip is electrically coupled to the semiconductor package substrate, and wherein the semiconductor package substrate comprises a plurality of layers including metal interconnects; and A semiconductor package substrate core, wherein the semiconductor package substrate core is in the semiconductor package substrate, wherein a layer including metal interconnects among the multiple layers is located on at least one side of the semiconductor package substrate core; wherein the semiconductor package substrate core includes an amorphous solid glass material, wherein the semiconductor package substrate core has a through-core via, wherein the through-core via includes a conductive region and multiple layers between the conductive region and the package substrate core, and wherein the multiple layers include an adhesion layer, a polymer layer, a magnetic layer, and a package substrate core liner.

12. The microelectronic assembly of claim 11, wherein: The semiconductor chip includes an integrated voltage regulator.

13. The microelectronic assembly of claim 11, further comprising a circuit board, wherein the semiconductor package substrate is electrically coupled to the circuit board.

14. The microelectronic assembly of claim 11, wherein: The magnetic layer includes CoNiFeX, CoFe, CoFeX, CoW, CoFeW, NiFe or NiFeX.

15. The microelectronic assembly of claim 11, wherein: The polymer layer includes an aliphatic or aromatic polymer.

16. The microelectronic assembly of claim 11, wherein: The magnetic layer has a thickness between 10 nm and 5 micrometers.

17. The microelectronic assembly of claim 11, wherein: The package substrate core includes aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide or fused silicon dioxide.

18. A method for manufacturing a magnetic inductor structure, comprising: depositing a package substrate core liner into a through hole in a package substrate core, wherein the package substrate core is composed of a solid amorphous glass material; depositing a seed layer for a magnetic material into the through-holes in the package substrate core; depositing a layer of magnetic material into the through-holes in the package substrate core; depositing a polymer layer into the through-holes in the package substrate core; depositing an adhesive into the through-holes in the package substrate core; depositing a conductive region seed layer into the through-holes in the package substrate core; and Conductive material is deposited into the through-holes in the package substrate core. 19 . The method of claim 18 , further comprising removing the package substrate core liner from a surface of the package substrate core.

20. The method according to claim 18, wherein: The package substrate core includes aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide or fused silicon dioxide.

21. The method according to claim 18, wherein: The magnetic material layer includes CoNiFeX, CoFe, CoFeX, CoW, CoFeW, NiFe or NiFeX.

22. The method according to claim 18, wherein: The polymer layer includes an aliphatic or aromatic polymer.

23. The method of claim 18, further comprising removing the layer of magnetic material from a surface of the package substrate core using a chemical mechanical polishing process.

24. The method according to claim 18, wherein: The magnetic layer has a thickness between 10 nm and 5 micrometers.

25. The method of claim 18, wherein: The solid amorphous glass material includes Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, Zn or a combination thereof.

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