Pulse latch trigger circuit with scanning function

Abstract

The invention discloses a pulse latch flip-flop circuit with scanning, and the circuit comprises a data selection unit which is used for receiving a data input signal, a scanning input signal, and an enable signal, and selecting one signal from the data input signal and the scanning input signal as a first output signal in response to the enable signal; the pulse generation unit is used for receiving the clock signal and generating a pulse signal according to the clock signal, and the pulse signal is generated after the rising edge of the clock signal; the latch unit comprises a clock feed-through unit which is used for charging or discharging according to different signals of the input end and the output end of the latch unit, and the latch unit is used for receiving the first output signal and the pulse signal and latching the first output signal synchronously with the pulse signal; and generating and outputting a second output signal of the current period in response to the first output signal and a reverse signal of the second output signal of the previous period. The invention has the advantages of high speed, low time delay, low power consumption and high charging and discharging speed.

Description

Technical Field

[0001] The invention belongs to the technical field of pulse latch triggers, and in particular relates to a pulse latch trigger circuit with scanning. Background Art

[0002] A flip-flop is a storage element widely used in many digital circuit designs. Currently, digital designs tend to apply a large number of pipeline technologies and frequently use flip-flop-rich components such as register arrays, shift registers, and first-in-first-out (FIFO) structures. According to research, the power consumed by the clock system consisting of the clock distribution network and storage elements may account for half of the total energy consumption of the entire system. Therefore, flip-flops account for a considerable proportion of the total area and energy consumption of the chip. In view of this, it becomes particularly critical to design high-speed and low-power flip-flops.

[0003] The current pulse latch trigger uses a traditional three-stage inverter cascade pulse generation unit structure, such as Figure 1 The structure shown, such as Figure 1 As shown, the traditional pulse latch trigger with scan includes a data selection unit, a master latch, a slave latch, and an inverter, wherein the data selection unit selects data input or scan input through an enable signal, the master latch latches the input before the clock arrives, and the slave latch latches the output of the master latch after the clock arrives. This structure has the disadvantages of high power consumption and large delay. In addition, the charging and discharging speed is also slow. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a pulse latch trigger circuit with scanning.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a pulse latch trigger circuit with scanning, comprising: a data selection unit, a pulse generation unit and a latch unit; the data selection unit and the pulse generation unit are both connected to the latch unit;

[0007] The data selection unit is used to receive a data input signal, a scan input signal and an enable signal, and select a signal from the data input signal and the scan input signal as a first output signal in response to the enable signal;

[0008] The pulse generating unit is used to receive a clock signal and generate a pulse signal according to the clock signal, wherein the pulse signal is generated after a rising edge of the clock signal;

[0009] The latch unit includes a clock feedthrough unit for charging or discharging according to the difference between the signals at its input and output ends. The latch unit is used to receive the first output signal and the pulse signal, latch the first output signal synchronously with the pulse signal, and generate and output the second output signal of the current cycle in response to the first output signal and the inverse signal of the second output signal of the previous cycle.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] Compared with the traditional pulse latch trigger circuit with two latches (such as the traditional three-stage inverter cascade pulse generating unit structure), the pulse latch trigger circuit designed in the present invention has only one latch unit, and the data input can be later than the clock input, thereby shortening the setup time, and thus has the characteristics of high speed, low delay, and low power consumption; in addition, because the pulse latch trigger circuit designed in the present invention includes a clock feedthrough unit for charging or discharging according to the difference in signals at its input and output ends, the charging or discharging speed of the latch unit can be accelerated, and therefore the present invention also has the advantage of fast charging and discharging speed.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the structure of a conventional pulse latch trigger with scanning provided by an embodiment of the present invention;

[0014] Figure 2 It is a structural schematic diagram of a pulse latch trigger circuit with scanning provided by an embodiment of the present invention;

[0015] Figure 3 It is a specific circuit connection diagram of a pulse latch trigger circuit with scanning provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0017] Figure 2 The embodiment of the present invention provides a pulse latch trigger circuit with scanning, and the pulse latch trigger circuit with scanning is a unit trigger circuit, such as Figure 2As shown, the pulse latch trigger circuit with scanning proposed by the present invention includes: a data selection unit, a pulse generating unit (also referred to as a pulse generator) and a latch unit. The data selection unit selects data input or scan input by an enable signal, the pulse generating unit generates a narrow pulse signal at the edge of the clock signal, and the latch unit latches the input signal synchronously with the narrow pulse and keeps the output signal unchanged under the non-edge. Specifically, the data selection unit is used to receive the data input signal, the scan input signal and the enable signal, and selects a signal from the data input signal and the scan input signal as the first output signal in response to the enable signal. The pulse generating unit is used to receive the clock signal and generate a pulse signal according to the clock signal, and the pulse signal is generated after the rising edge of the clock signal. The latch unit includes a clock feedthrough unit for charging or discharging according to the signals at its input and output ends, the latch unit is used to receive the first output signal and the pulse signal, and latch the first output signal synchronously with the pulse signal, and generate and output the second output signal of the current cycle in response to the first output signal and the reverse signal of the second output signal of the previous cycle.

[0018] Figure 3 1 is a schematic diagram of a specific circuit connection of a pulse latch trigger circuit with scanning provided by the present invention. For example, the pulse latch trigger circuit with scanning can be a pulse latch trigger circuit with scanning using TSMC 65nm process. Figure 3 As shown, the data selection unit 313 includes: a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and a sixth inverter I6, wherein MP4 and MN8 constitute a first transmission gate, a first control terminal of the first transmission gate is connected to an enable input terminal SE, and the enable input terminal SE is used to output an enable signal 302, a second control terminal of the first transmission gate is connected to an output terminal of I6, an input terminal of I6 is connected to the enable input terminal SE, a first input terminal of the first transmission gate is connected to a scan input terminal SI, and the scan input terminal SI is used to output a scan input signal 301, and a second input terminal of the first transmission gate is connected to a latch unit 315. MP5 and MN9 constitute a second transmission gate, a first control terminal of the second transmission gate is connected to a first control terminal of the first transmission gate, a second control terminal of the second transmission gate is connected to a second control terminal of the first transmission gate, a first input terminal of the second transmission gate is connected to a data input terminal DI, and the data input terminal DI is used to output a data input signal 303, and a second input terminal of the second transmission gate is connected to a second input terminal of the first transmission gate.

[0019] Here, the specific principle of the data selection unit 313 is: when the enable signal 302 is at a high level, the data selection unit 313 outputs the scan input signal 301 as the first output signal 308, and when the enable signal 302 is at a low level, the data selection unit outputs the data input signal 303 as the first output signal 308. Since the data selection unit of the present invention can select the scan input signal or the data input signal through the enable signal, the requirements of the basic unit of the scan chain are met, and the basic storage unit in the design for testability (DFT) scan chain is realized.

[0020] Continue to refer to the above Figure 3 The pulse generating unit 314 includes: a third PMOS transistor MP3, a seventh NMOS transistor MN7, a first NAND gate NAND1 and a first inverter I1, wherein the gate of MP3 and the first input terminal of NAND1 are both connected to the clock input terminal CK, the clock input terminal CK is used to output the clock signal 304, the drain of MP3 is used to access the power supply VDD, the source of MP3 is simultaneously connected to the drain of MN7 and the second input terminal of the first NAND gate NAND1, the source of MN7 is grounded, the gate of MN7 is connected to the output terminal of I1, the output terminal of NAND1 is connected to the input terminal of I1, the output terminal of I1 is also simultaneously connected to the latch unit, and the output terminal of I1 is used to output the pulse signal 307.

[0021] Here, NAND1 and MP3 receive the clock signal 304, and synchronously with the rising edge of the clock signal 304, the output of NAND1 is transmitted to the input end of I1, and I1 outputs the pulse signal 307 according to the input, and MN7 receives the feedback pulse signal and pulls one of the input signals of NAND1 low. Specifically, the specific principle of the pulse generating unit 314 is: when the clock input signal 304 is low, MP3 is turned on, the X1 point is high, the input of NAND1 is low and high, so the output of NAND1 is high, so the output of I1 is low, and MN7 is turned off; when the clock signal 304 changes from low level to high level, MP3 is turned off, the input of NAND1 is all high level, NAND1 outputs low level, the output of I1 is high level, MN7 is turned on, X1 is discharged, NAND1 outputs high level, I1 outputs low level, and the pulse signal 307 ends.

[0022] In some embodiments, the latch unit includes: a first-stage charge and discharge acquisition unit, a clock feedthrough unit, a second-stage charge and discharge unit, a data holding unit, a second inverter I2 and a third inverter I3.

[0023] The first-stage charge and discharge acquisition unit is respectively connected to the output end of the data selection unit for outputting the first output signal, the output end of the pulse generation unit for outputting the pulse signal, the clock feedthrough unit, and the second-stage charge and discharge unit. The first-stage charge and discharge acquisition unit is used to latch the first output signal synchronously with the pulse signal and output the third output signal according to the Qfeedback signal of the previous cycle (that is, the reverse signal of the second output signal of the previous cycle).

[0024] Here, the pulse signal serves as a clock signal when latching the first output signal.

[0025] The clock feedthrough unit is also connected to the output end of the pulse generating unit for outputting a pulse signal, the second-stage charge and discharge unit, the second inverter I2, the data holding unit and the third inverter I3. The clock feedthrough unit is used to charge or discharge according to the signals at its own input and output ends.

[0026] Here, by adding a clock feedthrough unit between the first-stage charge and discharge acquisition unit and the second-stage charge and discharge unit, when the pulse generating unit generates a pulse signal, when the signals at both ends of the clock feedthrough unit are different, the clock feedthrough unit is charged or discharged, thereby reducing the rising delay or falling delay of the output end for outputting the second output signal.

[0027] The second-level charge and discharge unit is also connected to the pulse generating unit, the second inverter I2, the data holding unit, and the third inverter I3. The second-level charge and discharge unit is used to charge, discharge, or maintain according to the third output signal and the first output signal. At the same time, in response to the third output signal and the first output signal, it generates and outputs the second output signal of the current cycle.

[0028] Here, the second-stage charge and discharge unit uses the pulse signal generated by the pulse generating unit as a clock signal when storing the third output signal and the first output signal.

[0029] The data holding unit is used to generate an inverted signal of the second output signal of the current cycle, and when the second output signal and the first output signal of the current cycle are both at a high level, the latch unit does not perform internal discharge, and is also used to eliminate the noise of the second output signal of the current cycle, and is also used to charge or discharge the output terminal for outputting the second output signal of the current cycle.

[0030] Here, through the data holding unit, on the one hand, the influence of noise or MOS tube leakage on the second output signal of the current cycle can be eliminated, so that the second output signal of the current cycle can be stabilized; on the other hand, the output end for outputting the second output signal of the current cycle can be charged or discharged; on the other hand, when the second output signal and the first output signal of the current cycle are both at high levels, the Qfeedback signal of the current cycle can be generated, so that the latch unit does not discharge internally.

[0031] The second inverter I2 is used to transmit the first output signal to the second-stage charge and discharge unit.

[0032] The third inverter I3 is used to invert the second output signal of the current cycle to obtain and output the Qfeedback signal of the current cycle.

[0033] For example, Figure 3 This is a schematic diagram of the circuit structure of the latch unit. Figure 3 As shown, the first-stage charge-discharge acquisition unit 309 includes: a first PMOS tube MP1, a first NMOS tube MN1, a second NMOS tube MN2 and a third NMOS tube MN3; the clock feedthrough unit 310 includes a fourth NMOS tube MN4; the second-stage charge-discharge unit 311 includes: a second PMOS tube MP2, a fifth NMOS tube MN5 and a sixth NMOS tube MN6; the data holding unit 312 includes: a fourth inverter I4 and a fifth inverter I5. Specifically, as Figure 3As shown, the source of MP1 is used to access the power supply VDD, the gate of MP1 is used to access the first output signal 308 output by the data selection unit, and at the same time, the gate of MP1 is also connected to the gate of MN2, and the drain of MP1 is simultaneously connected to the drain of MN1 and the gate of MP2; the source of MN1 is connected to the drain of MN2, and the gate of MN1 is used to access the pulse signal 307 output by the pulse generation unit, and at the same time, the gate of MN1 is also connected to the gate of MN4 and the gate of MN5; the source of MN2 is connected to the drain of MN3; the source of MN3 is grounded, and the gate of MN3 is connected to the output end of I4. The drain of MN4 is simultaneously connected to the gate of MP1, the gate of MN2 and the input end of I2, and the source of MN4 is simultaneously connected to the drain of MP2, the drain of MN5, the input end of I3, and the input end of I4. The gate of MP2 is connected to the drain of MP1 and the drain of MN1 at the same time, the source of MP2 is used to access the power supply VDD, the drain of MP2 is connected to the drain of MN5 and the source of MN4 at the same time, the drain of MN5 is also connected to the data output terminal Q and the input terminal of I3 respectively, so as to output the second output signal 305 of the current cycle to the data output terminal Q, thereby outputted by the data output terminal Q, and input the second output signal 305 of the current cycle to I3, the output terminal of I3 is connected to the data reverse output terminal Qbar, so as to output the reverse signal 306 of the second output signal of the current cycle to the data reverse output terminal Qbar, thereby outputted by the data reverse output terminal Qbar. The gate of MN5 is connected to the gate of MN4 and the gate of MN1 at the same time, the source of MN5 is connected to the drain of MN6; the gate of MN6 is connected to the output terminal of I2, and the source of MN6 is grounded. The input end of I4 is connected to the output end of I5 and the drain of MP2, the output end of I4 is connected to the input end of I5, and the output end of I4 is used to output the reverse signal Qfeedback of the second output signal.

[0034] Here, the specific principle of the latch unit is as follows:

[0035] When the pulse signal 307 is at a high level, the first output signal 308 is at a high level, and the second output signal 305 of the previous cycle is at a low level, the reverse signal Qfeedback of the second output signal 305 of the previous cycle is at a high level, then the MP1 tube is turned off, MN1, MN2, and MN3 are all turned on, the X3 node is discharged to a low level, and the X3 node controls MP2 to turn on, so that the second output signal 305 of the current cycle is charged to a high level. At the same time, the clock feedthrough unit 310 is turned on (that is, MN4 is turned on), and the output end of the first output signal 308 is charged to the output end of the second output signal 305 of the current cycle;

[0036] When the pulse signal 307 is at a high level, the first output signal 308 is at a low level, and the second output signal 305 of the previous cycle is at a high level, the reverse signal Qfeedback of the second output signal 305 of the previous cycle is at a low level, MP1 is turned on, the X3 node is charged to a high level, MP2 is turned off, MN5 and MN6 are turned on, and the second output signal 305 of the current cycle is discharged to a low level. At the same time, the clock feedthrough unit 310 is turned on, and discharges from the output end of the second output signal 305 of the current cycle to the output end of the first output signal 308;

[0037] When the pulse signal 307 is at a high level, the first output signal 308 is at a high level, and the second output signal 305 of the previous cycle is at a high level, the reverse signal Qfeedback of the second output signal 305 of the previous cycle is at a low level, MN3 is turned off, and the internal node X3 remains unchanged with the second output signal 305 of the current cycle;

[0038] When the pulse signal 307 is at a high level, the first output signal 308 is at a low level, and the second output signal 305 of the previous cycle is at a low level, the second output signal 305 of the current cycle remains unchanged;

[0039] When the pulse signal 307 is at a low level, the first output signal 308 is at a high level, and the second output signal 305 of the previous cycle is at a high level, the second output signal 305 of the current cycle remains unchanged;

[0040] When the pulse signal 307 is at a low level, the first output signal 308 is at a high level, and the second output signal 305 of the previous cycle is at a low level, the second output signal 305 of the current cycle remains unchanged;

[0041] When the pulse signal 307 is at a low level, the first output signal 308 is at a low level, and the second output signal 305 of the previous cycle is at a high level, the second output signal 305 of the current cycle remains unchanged;

[0042] When the pulse signal 307 is at a low level, the first output signal 308 is at a low level, and the second output signal 305 of the previous cycle is at a low level, the second output signal 305 of the current cycle remains unchanged.

[0043] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0044] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0045] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0046] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A pulse latch trigger circuit with scanning, characterized in that: include: A data selection unit, a pulse generation unit and a latch unit; the data selection unit and the pulse generation unit are both connected to the latch unit; The data selection unit is used to receive a data input signal, a scan input signal and an enable signal, and select a signal from the data input signal and the scan input signal as a first output signal in response to the enable signal; The pulse generating unit is used to receive a clock signal and generate a pulse signal according to the clock signal, wherein the pulse signal is generated after a rising edge of the clock signal; The latch unit includes a clock feedthrough unit for charging or discharging according to the difference between the signals at its input and output ends. The latch unit is used to receive the first output signal and the pulse signal, latch the first output signal synchronously with the pulse signal, and generate and output the second output signal of the current cycle in response to the first output signal and the inverse signal of the second output signal of the previous cycle.

2. The pulse latch trigger circuit with scanning according to claim 1, characterized in that: The latch unit includes: a first-stage charge and discharge acquisition unit, the clock feedthrough unit, a second-stage charge and discharge unit, a data holding unit, a second inverter I2 and a third inverter I3; The first-stage charge and discharge acquisition unit is respectively connected to the output end of the data selection unit for outputting the first output signal, the output end of the pulse generation unit for outputting the pulse signal, the clock feedthrough unit, and the second-stage charge and discharge unit, and is used to latch the first output signal synchronously with the pulse signal according to the reverse signal of the second output signal of the previous cycle and output a third output signal; The clock feedthrough unit is also connected to the output end of the pulse generating unit for outputting the pulse signal, the second-stage charge and discharge unit, the second inverter I2, the data holding unit and the third inverter I3, and is used to charge or discharge according to the difference of the signals at its input and output ends; The second-stage charge and discharge unit is also connected to the pulse generating unit, the second inverter I2, the data holding unit, and the third inverter I3, and is used to charge or discharge or hold the first output signal according to the third output signal, and at the same time, generate and output the second output signal of the current cycle; The data holding unit is used to generate an inverted signal of the second output signal of the current cycle, and to prevent the latch unit from performing internal discharge when the second output signal of the current cycle and the first output signal are both at a high level, and is also used to eliminate the influence of noise or MOS tube leakage on the second output signal of the current cycle, and is also used to charge or discharge the output terminal for outputting the second output signal of the current cycle; The second inverter I2 is used to transmit the first output signal to the second-stage charge and discharge unit; The third inverter I3 is used to invert the second output signal of the current cycle to obtain and output the inverse signal of the second output signal of the current cycle.

3. The pulse latch trigger circuit with scanning according to claim 2, characterized in that: When the pulse signal is at a high level, the first output signal is at a high level, and the inverse signal of the second output signal of the previous cycle is at a high level, the clock feedthrough unit is turned on to charge the output end of the first output signal to the output end of the second output signal of the current cycle; When the pulse signal is at a high level, the first output signal is at a low-high level, and the inverse signal of the second output signal of the previous cycle is at a low level, the clock feedthrough unit is turned on to discharge from the output end of the second output signal of the current cycle to the output end of the first output signal.

4. The pulse latch trigger circuit with scanning according to claim 2, characterized in that: The first-stage charge and discharge acquisition unit includes: a first PMOS tube MP1, a first NMOS tube MN1, a second NMOS tube MN2 and a third NMOS tube MN3; The first PMOS transistor MP1 has a source electrode connected to the power supply VDD, a gate electrode connected to the output terminal of the data selection unit for outputting the first output signal, the gate electrode of the second NMOS transistor MN2 and the clock feedthrough unit, and a drain electrode connected to the drain electrode of the first NMOS transistor MN1 and the second-stage charge and discharge unit; The source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2, and the gate is connected to the output end of the pulse generating unit for outputting the pulse signal, the clock feedthrough unit and the second-stage charge and discharge unit; The source of the second NMOS transistor MN2 is connected to the drain of the third NMOS transistor MN3; The third NMOS transistor MN3 has a source connected to the ground and a gate connected to the data holding unit to receive the reverse signal of the second output signal of the previous cycle.

5. The pulse latch trigger circuit with scanning according to claim 4, characterized in that: The clock feedthrough unit includes a transistor connected between the first-stage charge and discharge acquisition unit and the second-stage charge and discharge unit.

6. The pulse latch trigger circuit with scanning according to claim 4 or 5, characterized in that: The clock feedthrough unit includes: a fourth NMOS tube MN4, the drain of the fourth NMOS tube MN4 is simultaneously connected to the gate of the first PMOS tube MP1, the gate of the second NMOS tube MN2 and the input end of the second inverter I2, the source is simultaneously connected to the second-stage charge and discharge unit, the data holding unit and the third inverter I3, and the gate is simultaneously connected to the output end of the pulse generating unit for outputting the pulse signal, the gate of the first NMOS tube MN1 and the second-stage charge and discharge unit.

7. The pulse latch trigger circuit with scanning according to claim 6, characterized in that: The second-stage charge-discharge unit includes: a second PMOS tube MP2, a fifth NMOS tube MN5 and a sixth NMOS tube MN6; The gate of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1, the source is used to access the power supply VDD, and the drain is connected to the drain of the fifth NMOS transistor MN5, the source of the fourth NMOS transistor MN4, the input end of the third inverter I3, and the data holding unit; The fifth NMOS transistor MN5 has a gate connected to the gate of the fourth NMOS transistor MN4, the output end of the pulse generating unit for outputting the pulse signal and the gate of the first NMOS transistor MN1, and a source connected to the drain of the sixth NMOS transistor MN6; The sixth NMOS transistor MN6 has a gate connected to the output end of the second inverter I2 and a source grounded.

8. The pulse latch trigger circuit with scanning according to claim 7, characterized in that: The data holding unit comprises: a fourth inverter I4 and a fifth inverter I5; The input end of the fourth inverter I4 is connected to the output end of the fifth inverter I5 and the drain of the second PMOS tube MP2 at the same time, the output end of the fourth inverter I4 is connected to the input end of the fifth inverter I5, and the output end of the fourth inverter I4 is used to output the reverse signal of the second output signal.

9. The pulse latch trigger circuit with scanning according to claim 1, characterized in that: The pulse generating unit includes: a third PMOS transistor MP3, a seventh NMOS transistor MN7, a first NAND gate NAND1 and a first inverter I1; The gate of the third PMOS transistor MP3 and the first input terminal of the first NAND gate NAND1 are both connected to the clock input terminal CK, the clock input terminal CK is used to output the clock signal, the drain of the third PMOS transistor MP3 is used to access the power supply VDD, and the source of the third PMOS transistor MP3 is simultaneously connected to the drain of the seventh NMOS transistor MN7 and the second input terminal of the first NAND gate NAND1; The source of the seventh NMOS transistor MN7 is grounded, and the gate is connected to the output end of the first inverter I1; The output end of the first NAND gate NAND1 is connected to the input end of the first inverter I1; The output end of the first inverter I1 is also connected to the latch unit.

10. The pulse latch trigger circuit with scanning according to claim 1, characterized in that: The data selection unit includes: a fourth PMOS tube MP4, a fifth PMOS tube MP5, an eighth NMOS tube MN8, a ninth NMOS tube MN9 and a sixth inverter I6; The fourth PMOS transistor MP4 and the eighth NMOS transistor MN8 constitute a first transmission gate, a first control terminal of the first transmission gate is connected to an enable input terminal SE, and the enable input terminal SE is used to output the enable signal, a second control terminal of the first transmission gate is connected to an output terminal of the sixth inverter I6, an input terminal of the sixth inverter I6 is connected to the enable input terminal SE, a first input terminal of the first transmission gate is connected to a scan input terminal SI, and the scan input terminal SI is used to output the scan input signal, and a second input terminal of the first transmission gate is connected to the latch unit; The fifth PMOS transistor MP5 and the ninth NMOS transistor MN9 constitute a second transmission gate, a first control end of the second transmission gate is connected to the first control end of the first transmission gate, a second control end of the second transmission gate is connected to the second control end of the first transmission gate, a first input end of the second transmission gate is connected to a data input end DI, the data input end DI is used to output the data input signal, and a second input end of the second transmission gate is connected to a second input end of the first transmission gate.

Images