Sending, receiving, returning and detecting integrated system for multiple SFP (Small Form-factor Pluggable) light sources

Abstract

The invention relates to the technical field of SFP light source data detection, in particular to a sending and receiving return detection integrated system for multiple SFP light sources, which comprises a main control unit, an SFP optical module control unit and an ROSA device return signal measurement unit, the SFP optical module control unit comprises a multi-way switch chip U16, an indicating lamp module and a plurality of SFP optical module interfaces; the indicating lamp module and the plurality of SFP optical module interfaces are respectively connected with the multi-way switch chip U16; and the indicating lamp module is used for indicating the working states of the plurality of optical modules. According to the invention, the design is ingenious, the sending control of a plurality of SFP optical modules and the detection of received data return signals are realized, and the stability and reliability of data transmission are ensured; by integrating an ROSA device return signal measurement unit, the circuit can monitor the quality of a data return signal in real time, and powerful support is provided for network optimization and maintenance.

Description

Technical Field

[0001] The present invention relates to the technical field of SFP light source data detection, and in particular to a transmission and reception return detection integrated system for multiple SFP light sources. Background Art

[0002] In the current communication field, single-mode SFP (Small Form-factor Pluggable) optical modules are widely used in data centers, enterprise networks and telecommunication networks as key components for high-speed data transmission. However, existing systems can only support the sending and receiving functions of a single SFP optical module, and lack an integrated system that can realize the sending switching and receiving data return signal detection of multiple single-mode SFP light sources. This limits the flexibility and scalability of the system and cannot meet the needs of modern communication networks for diversified and high-performance optical communication modules. Therefore, the development of an integrated system that can realize the sending control and receiving data return signal detection of multiple SFP optical modules has become an urgent problem to be solved. Summary of the invention

[0003] In view of the problems of the prior art, the present invention provides an integrated system for sending and receiving return detection of multiple SFP light sources, which has a novel structure and realizes the detection of sending control and receiving data return signals of multiple SFP optical modules, thereby ensuring the stability and reliability of data transmission; by integrating a ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, thereby providing strong support for network optimization and maintenance; the model detection integrated circuit of multiple single-mode SFP light sources of the present application has significant beneficial effects in improving communication network performance, reducing operating costs, and enhancing system flexibility.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] The present invention provides a transmission and reception return detection integrated system for multiple SFP light sources, which includes a main control unit, an SFP optical module control unit and a ROSA device return signal measurement unit;

[0006] The SFP optical module control unit includes a multi-way switch chip U16, an indicator light module and multiple SFP optical module interfaces, the indicator light module and the multiple SFP optical module interfaces are respectively connected to the multi-way switch chip U16, and the main control unit is respectively connected to the multi-way switch chip U16 and the multiple SFP optical module interfaces;

[0007] The ROSA device return signal measurement unit includes an analog-to-digital conversion chip U15, a common-mode data acquisition module and a differential-mode data acquisition module. The analog-to-digital conversion chip U15, the common-mode data acquisition module and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital conversion chip U15 is connected to the differential-mode data acquisition module.

[0008] The model of the multi-way switch chip U16 is TCA9548APWR.

[0009] The model of the analog-to-digital conversion chip U15 is 3PA1030.

[0010] Wherein, the differential mode data acquisition module includes an operational amplifier U14, an operational amplifier U18.2, a resistor R40, a resistor R41, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a resistor R48, a resistor R49, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a capacitor C41, a capacitor C42, a capacitor C44, a capacitor C45, a capacitor C46, ​​a capacitor C47, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a Zener diode D4, two Zener diodes D2 and two Zener diodes D3; one end of the resistor R45 is respectively connected to one end of the capacitor C42, one end of the capacitor C41, one end of the resistor R40, and the first pin of the operational amplifier U14, and one end of the resistor R46 ... It is connected to one end of capacitor C55, one end of resistor R53, one end of capacitor C56, one end of resistor R54, and the eighth pin of operational amplifier U14, wherein the anode of one zener diode D2 is connected to the cathode of another zener diode D2 and then connected to the other end of resistor R45, and the anode of one zener diode D3 is connected to the cathode of another zener diode D3 and then connected to the other end of resistor R46; the second pin of operational amplifier U14 is connected to one end of capacitor C44 and analog-to-digital conversion chip U15, the other end of capacitor C44 is grounded, the other end of resistor R54 is connected to one end of resistor R55 and the output pin of operational amplifier U18.2, the in-phase input end of operational amplifier U18.2 is connected to analog-to-digital conversion chip U15, and the inverting input end of operational amplifier U18.2 and the other end of resistor R55 are respectively connected to the main control unit;

[0011] The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14, the other end of resistor R40, the other end of resistor R44 and the other end of capacitor C41 are respectively connected to one end of resistor R41, the other end of resistor R41 is respectively connected to one end of capacitor C47 and one end of capacitor C49, the other end of capacitor C47 is grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, The four pins and the other end of capacitor C55 are respectively connected to one end of resistor R47, the other end of resistor R47, the other end of resistor R53 and the other end of capacitor C56 are respectively connected to one end of resistor R48, the other end of resistor R48, the other end of capacitor C49, one end of capacitor C53 and the cathode of Zener diode D4 are respectively connected to one end of resistor R49, the other end of resistor R49 and one end of capacitor C52 are respectively connected to analog-to-digital conversion chip U15, and the other end of capacitor C52 is grounded; the sixth pin of operational amplifier U14 is respectively connected to one end of capacitor C50 and one end of capacitor C51, and the other end of capacitor C50 and the other end of capacitor C51 are grounded.

[0012] The analog-to-digital conversion chip U15 is provided with an AIN pin and a VREF pin, and the AIN pin of the analog-to-digital conversion chip U15 is connected to the other end of the resistor R49; the differential mode data acquisition module also includes a resistor R57, a resistor R58, a resistor R59, a resistor R61, a capacitor C58, a capacitor C59, a capacitor C63, a capacitor C64 and an operational amplifier U18.1;

[0013] The VREF pin of the analog-to-digital conversion chip U15 is connected to one end of the resistor R61, and the other end of the resistor R61 is respectively connected to one end of the resistor R62, one end of the capacitor C63, one end of the capacitor C64 and the non-inverting input end of the operational amplifier U18.1, the output end of the operational amplifier U18.1 is connected to the non-inverting input end of U18.2, the inverting input end of the operational amplifier U18.1 is connected to one end of the resistor R59, one end of the resistor R57, and one end of the capacitor C58, the other end of the resistor R59 is grounded, the eighth pin of the operational amplifier U18.1 is connected to one end of the capacitor C59, the other end of the capacitor C59 is grounded, and the other end of the resistor R57 and the other end of the capacitor C58 are connected to the output end of the operational amplifier U18.1.

[0014] The common-mode data acquisition module includes an operational amplifier U17.1, an operational amplifier U17.2, a resistor R42, a resistor R43, a resistor R50, a resistor R51, a capacitor C43, a capacitor C48 and a capacitor C54. One end of the resistor R42 and one end of the capacitor C48 are connected to the in-phase input terminal of the operational amplifier U17.1, and the other end of the capacitor C48 is grounded. The inverting input terminal of the operational amplifier U17.1 and the output terminal of the operational amplifier U17.1 are respectively connected to one end of the resistor R43. The other end is connected to the main control unit, the fourth pin of the operational amplifier U17.1 is grounded, the eighth pin of the operational amplifier U17.1 is connected to one end of the capacitor C43, and the other end of the capacitor C43 is grounded; one end of the resistor R50 and one end of the capacitor C54 are connected to the in-phase input terminal of the operational amplifier U17.2, the other end of the capacitor C54 is grounded, the inverting input terminal of the operational amplifier U17.2 and the output terminal of the operational amplifier U17.2 are respectively connected to one end of the resistor R51, and the other end of the resistor R51 is connected to the main control unit.

[0015] Among them, the multiple SFP optical module interfaces include optical module interface SFP1, optical module interface SFP2, optical module interface SFP3 and optical module interface SFP4, each of the SFP optical module interfaces includes an SFP_DIS pin and an SFP_FAULT pin, and the indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8; the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP1 are respectively connected to LED1 and LED5, the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP2 are respectively connected to LED2 and LED6, the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP3 are respectively connected to LED3 and LED7, and the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP4 are respectively connected to LED4 and LED8.

[0016] The main control unit includes a chip U1 and a chip U2. The model of the chip U1 is AX58200, and the model of the chip U2 is STM32H730.

[0017] The model detection integrated circuit of the plurality of single-mode SFP light sources further comprises a power supply circuit, and the power supply circuit is used to supply power to the main control unit, the SFP optical module control unit and the ROSA device return signal measurement unit.

[0018] Beneficial effects of the present invention:

[0019] The present application has a novel structure and an ingenious design. The main control unit, as the core of the entire circuit, is responsible for receiving external instructions and controlling the work of the SFP optical module control unit and the ROSA device return signal measurement unit according to the instructions; the main control unit is responsible for high-speed data processing and system logic control; the switching control of multiple SFP optical module interfaces is realized through the multi-way switch chip U16, and the indicator light module displays the working status of each SFP optical module; the analog-to-digital conversion chip U15 converts the collected analog signal into a digital signal for processing by the main control unit; the differential data acquisition module realizes the collection of differential signals, and the common-mode data acquisition module is used to collect common-mode signals; the main control unit selects the corresponding SFP optical module for sending control through the multi-way switch chip U16 according to the received instructions; at the same time, the ROSA device return signal measurement unit collects the received data feedback signals, including differential signals and common-mode signals, and converts these signals into digital signals before sending them to the main control unit for processing. ; The main control unit realizes optical coupling monitoring of the differential or common mode voltage of the receiving device, as well as the multiplexing of multiple light sources and the control of the sending data mode and frequency according to the processing results; Multi-interface support: The present application adopts multiple independent SFP optical module interfaces, which improves the flexibility and scalability of the system; By using multiple independent SFP optical module interfaces, it can be used to connect multiple optical modules with different wavelengths, thereby realizing the multiplexing of multiple light sources and improving the communication capacity and efficiency of the circuit; and the circuit of the present application can realize the sending control of multiple SFP optical modules and the detection of the received data return signal, thereby ensuring the stability and reliability of data transmission; By integrating the ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, providing strong support for network optimization and maintenance; The model detection integrated circuit of multiple single-mode SFP light sources of the present application has significant beneficial effects in improving the performance of communication networks, reducing operating costs, and enhancing system flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 4 is a circuit diagram of the main control unit of the present invention.

[0021] Figure 2 The figure is a circuit diagram of the SFP optical module control unit of the present invention.

[0022] Figure 3 The circuit diagram of the return signal measurement unit of the ROSA device of the present invention.

[0023] Figure 4 It is a circuit diagram of the power supply circuit of the present invention. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of those skilled in the art, the present invention is further described below in conjunction with the embodiments and drawings, and the contents mentioned in the embodiments are not intended to limit the present invention. The present invention is described in detail below in conjunction with the drawings.

[0025] An integrated system for transmitting and receiving backhaul detection of multiple SFP light sources, such as Figures 1 to 4 As shown, it includes a main control unit, an SFP optical module control unit and a ROSA device return signal measurement unit; wherein the main control unit includes a chip U1 and a chip U2, the model of the chip U1 is AX58200, and the model of the chip U2 is STM32H730; the SFP optical module control unit includes a multi-way switch chip U16, an indicator light module and a plurality of SFP optical module interfaces, the indicator light module and the plurality of SFP optical module interfaces are respectively connected to the multi-way switch chip U16, and the main control unit is respectively connected to the multi-way switch chip U16. The switch chip U16 and multiple SFP optical module interfaces are connected; the ROSA device return signal measurement unit includes an analog-to-digital conversion chip U15, a common-mode data acquisition module and a differential-mode data acquisition module, the analog-to-digital conversion chip U15, the common-mode data acquisition module and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital conversion chip U15 is connected to the differential-mode data acquisition module; wherein the model of the multi-way switch chip U16 is TCA9548APWR; the model of the analog-to-digital conversion chip U15 is 3PA1030.

[0026] Specifically, in the embodiment of the present application, the main control unit, as the core of the entire system, is responsible for receiving external instructions and controlling the work of the SFP optical module control unit and the ROSA device return signal measurement unit according to the instructions. The main control unit includes two chips, AX58200 and STM32H730, which are responsible for high-speed data processing and system logic control respectively; the switching control of multiple SFP optical module interfaces is realized through the multi-way switch chip U16 (TCA9548APWR), and the indicator light module displays the working status of each SFP optical module; the analog-to-digital conversion chip U15 converts the collected analog signal into a digital signal for processing by the main control unit; the differential data acquisition module realizes the collection of differential signals, and the common mode data acquisition module is used to collect common mode signals; the main control unit selects the corresponding SFP optical module for sending control through the multi-way switch chip U16 according to the received instructions; at the same time, the ROSA device return signal measurement unit collects the received data return signals, including differential signals and common mode signals, and converts these signals into digital signals and sends them to the main control unit for processing; the main control unit realizes the receiver according to the processing results. Optical coupling monitoring of differential or common-mode voltage of components, as well as multiplexing of multiple light sources and control of transmission data mode and frequency; Multi-interface support: the present application adopts multiple independent SFP optical module interfaces, which improves the flexibility and scalability of the system; by using multiple independent SFP optical module interfaces, it can be used to connect multiple optical modules with different wavelengths, thereby realizing the multiplexing of multiple light sources and improving the communication capacity and efficiency of the circuit; and the circuit of the present application can realize the transmission control of multiple SFP optical modules and the detection of received data return signals, thereby ensuring the stability and reliability of data transmission; by integrating the ROSA device return signal measurement unit, the circuit can monitor the quality of the data return signal in real time, providing strong support for network optimization and maintenance; the transmission and reception return detection integrated system of multiple SFP light sources of the present application has significant beneficial effects in improving communication network performance, reducing operating costs, and enhancing system flexibility.

[0027] In the embodiment of the present application, the differential mode data acquisition module includes an operational amplifier U14, an operational amplifier U18.2, a resistor R40, a resistor R41, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a resistor R48, a resistor R49, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a capacitor C41, a capacitor C42, a capacitor C44, a capacitor C45, a capacitor C46, ​​a capacitor C47, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a Zener diode D4, two Zener diodes D2 and two Zener diodes D3; one end of the resistor R45 is respectively connected to one end of the capacitor C42, one end of the capacitor C41, one end of the resistor R40, and a first pin of the operational amplifier U14, and one end of the resistor R46 is respectively connected to one end of the capacitor C42, one end of the capacitor C41, one end of the resistor R40, and a first pin of the operational amplifier U14. The ends are respectively connected to one end of capacitor C55, one end of resistor R53, one end of capacitor C56, one end of resistor R54, and the eighth pin of operational amplifier U14, wherein the anode of one voltage zener diode D2 is connected to the cathode of another voltage zener diode D2 and then connected to the other end of resistor R45, and the anode of one voltage zener diode D3 is connected to the cathode of another voltage zener diode D3 and then connected to the other end of resistor R46; the second pin of operational amplifier U14 is connected to one end of capacitor C44 and analog-to-digital conversion chip U15, the other end of capacitor C44 is grounded, the other end of resistor R54 is connected to one end of resistor R55 and the output pin of operational amplifier U18.2, the in-phase input end of operational amplifier U18.2 is connected to analog-to-digital conversion chip U15, and the inverting input end of operational amplifier U18.2 and the other end of resistor R55 are respectively connected to the main control unit;

[0028] The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14, the other end of resistor R40, the other end of resistor R44 and the other end of capacitor C41 are respectively connected to one end of resistor R41, the other end of resistor R41 is respectively connected to one end of capacitor C47 and one end of capacitor C49, the other end of capacitor C47 is grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, The four pins and the other end of capacitor C55 are respectively connected to one end of resistor R47, the other end of resistor R47, the other end of resistor R53 and the other end of capacitor C56 are respectively connected to one end of resistor R48, the other end of resistor R48, the other end of capacitor C49, one end of capacitor C53 and the cathode of Zener diode D4 are respectively connected to one end of resistor R49, the other end of resistor R49 and one end of capacitor C52 are respectively connected to analog-to-digital conversion chip U15, and the other end of capacitor C52 is grounded; the sixth pin of operational amplifier U14 is respectively connected to one end of capacitor C50 and one end of capacitor C51, and the other end of capacitor C50 and the other end of capacitor C51 are grounded.

[0029] The analog-to-digital conversion chip U15 is provided with an AIN pin and a VREF pin, and the AIN pin of the analog-to-digital conversion chip U15 is connected to the other end of the resistor R49; the differential mode data acquisition module also includes a resistor R57, a resistor R58, a resistor R59, a resistor R61, a capacitor C58, a capacitor C59, a capacitor C63, a capacitor C64 and an operational amplifier U18.1;

[0030] The VREF pin of the analog-to-digital conversion chip U15 is connected to one end of the resistor R61, and the other end of the resistor R61 is respectively connected to one end of the resistor R62, one end of the capacitor C63, one end of the capacitor C64 and the non-inverting input end of the operational amplifier U18.1, and the other end of the resistor R62, the other end of the capacitor C63 and the other end of the capacitor C64 are respectively grounded. The output end of the operational amplifier U18.1 is connected to the non-inverting input end of U18.2, the inverting input end of the operational amplifier U18.1 is connected to one end of the resistor R59, one end of the resistor R57 and one end of the capacitor C58, and the other end of the resistor R59 is grounded. The eighth pin of the operational amplifier U18.1 is connected to one end of the capacitor C59, and the other end of the capacitor C59 is grounded. The other end of the resistor R57 and the other end of the capacitor C58 are connected to the output end of the operational amplifier U18.1.

[0031] Specifically, under the above settings, resistors R40, R41, R44, R45, R46, R47, R48, R49, R52, R53, R54, R55: these resistors are mainly used to set the gain and bias current of the operational amplifier and provide appropriate voltage division for the circuit; they are connected to the input, output and feedback loop of the operational amplifier to control the amplitude and stability of the signal; resistors R57, R58, R59, R61, R62: these resistors are related to the operational amplifier U18.1, and are used to set the resistance value of its input, output and feedback loop to control the gain and stability of the signal; resistor R61, which is used to provide a reference voltage for the VREF pin of the analog-to-digital conversion chip U15; operational amplifier U14: this operational amplifier is used to amplify and condition the differential signal. It receives differential signals from external sensors, amplifies them through its gain and feedback network, and then outputs them to the analog-to-digital conversion chip U15 for digital processing; Operational amplifiers U18.1 and U18.2: These two operational amplifiers are used to further condition the signals, such as providing additional gain, filtering, or buffering; The output of U18.1 may be used as the input of U18.2 to form a cascade amplification or filtering circuit; The output of U18.2 is ultimately connected to the analog-to-digital conversion chip U15; Analog-to-digital conversion chip U15: This chip is responsible for converting analog signals into digital signals; It receives the conditioned analog signals from the operational amplifier, and samples and quantizes them through its AIN pin, The digital signal is then output to the subsequent digital processing circuit; the VREF pin may be used to receive a reference voltage to ensure the accuracy and stability of the analog-to-digital conversion; capacitors C41, C42, C44, C45, C46, ​​C47, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C63, C64: these capacitors are mainly used for filtering, decoupling and stabilizing circuits; they form a filtering network together with resistors and operational amplifiers to eliminate high-frequency noise and interference; at the same time, they also provide the necessary decoupling and bypass capacitance for the operational amplifier and analog-to-digital conversion chip to ensure the stability and performance of the circuit.

[0032] In the embodiment of the present application, the common-mode data acquisition module includes an operational amplifier U17.1, an operational amplifier U17.2, a resistor R42, a resistor R43, a resistor R50, a resistor R51, a capacitor C43, a capacitor C48 and a capacitor C54, one end of the resistor R42 and one end of the capacitor C48 are connected to the in-phase input terminal of the operational amplifier U17.1, the other end of the capacitor C48 is grounded, the inverting input terminal of the operational amplifier U17.1 and the output terminal of the operational amplifier U17.1 are respectively connected to one end of the resistor R43, and the resistor R The other end of 43 is connected to the main control unit, the fourth pin of the operational amplifier U17.1 is grounded, the eighth pin of the operational amplifier U17.1 is connected to one end of the capacitor C43, and the other end of the capacitor C43 is grounded; one end of the resistor R50 and one end of the capacitor C54 are connected to the in-phase input terminal of the operational amplifier U17.2, the other end of the capacitor C54 is grounded, the inverting input terminal of the operational amplifier U17.2 and the output terminal of the operational amplifier U17.2 are respectively connected to one end of the resistor R51, and the other end of the resistor R51 is connected to the main control unit.Specifically, the input end of the operational amplifier U17.1: resistor R42 and capacitor C48 are connected in series to the non-inverting input end of the operational amplifier U17.1; here, capacitor C48 plays the role of AC coupling, allowing AC signals to pass through and blocking DC signals; resistor R42 is used to limit the input current; the reverse input end of the operational amplifier U17.1 is connected to its output end through resistor R43 to form a negative feedback loop; this connection method enables the operational amplifier to work in a voltage follower mode, that is, the output voltage follows the change of the input voltage, but has a higher input impedance and a lower output impedance; the output end of the operational amplifier U17.1 is connected to the main control unit through resistor R43; here, resistor R43 not only plays a current limiting role, but is also used to transmit the output voltage of the operational amplifier to the main control unit for further processing; the circuit structure of the operational amplifier U17.2 is similar to that of U17.1, but it processes another common-mode signal; resistor R50 and capacitor C54 are connected in series to the non-inverting input end of the operational amplifier U17.2, and capacitor C54 also plays the role of AC coupling. ; The inverting input terminal of the operational amplifier U17.2 is connected to its output terminal through resistor R51 to form a negative feedback loop, so that U17.2 also works in voltage follower mode; the output terminal of the operational amplifier U17.2 is connected to the main control unit through resistor R51; capacitor C43 is connected to the eighth pin of the operational amplifier U17.1 (usually the power pin or the reference voltage pin, depending on the model of the operational amplifier) ​​and grounded; used to provide a stable power supply voltage or reference voltage, or to filter out high-frequency noise on the power line; processing of common-mode signals: in this module, operational amplifiers U17.1 and U17.2 process two common-mode signals respectively; common-mode signals refer to the same signals that appear on the differential signal line pair at the same time; these signals may be introduced by the external environment, such as power line noise, ground potential differences, etc.; through the voltage follower effect of the operational amplifier, these common-mode signals are amplified (actually voltage following) and transmitted to the main control unit; in the main control unit, these signals can be used to monitor the common-mode noise level of the system, or for subsequent digital signal processing to eliminate common-mode interference. Function of the main control unit: The main control unit receives the output signals from operational amplifiers U17.1 and U17.2, and performs further digital signal processing, such as filtering, amplification, A / D conversion, etc., to extract useful information or eliminate unwanted noise; the common-mode data acquisition module processes two common-mode signals respectively through two operational amplifiers, and transmits the processed signals to the main control unit for further processing; it helps to monitor and eliminate common-mode noise in the system and improve the accuracy and reliability of data acquisition.

[0033] In an embodiment of the present application, the multiple SFP optical module interfaces include an optical module interface SFP1, an optical module interface SFP2, an optical module interface SFP3 and an optical module interface SFP4, each of the SFP optical module interfaces includes an SFP_DIS pin and an SFP_FAULT pin, and the indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8; the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP1 are respectively connected to LED1 and LED5, the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP2 are respectively connected to LED2 and LED6, the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP3 are respectively connected to LED3 and LED7, and the SFP_DIS pin and SFP_FAULT pin of the optical module interface SFP4 are respectively connected to LED4 and LED8. Specifically, the circuit includes three parts: I2C data monitoring, data transmission control, and light source transmission enable and indication; each channel is independent of each other, and the monitoring interface needs to be independent of each other as well; circuit working principle: TXD+ / TXD- form complementary differential or same level to realize differential or common mode data output, and the frequency is realized by different reload values ​​and comparison values ​​of two complementary channels controlled by MCU EPWM; LED1 to LED4 indicate whether the indicator transmission function is normal; SFP_DIS signal is controlled by MCU to realize data transmission enable and stop, and LED5 to LED6 indicate whether the enable is working normally; the monitoring interface uses I2C analog switch, and a single I2C signal is switched from I2C2 to one of the four channels, so as to facilitate the isolation of optical modules with the same device address and realize multiple module monitoring; by observing the status of LED, the user can quickly understand the working status of each SFP optical module interface; for example, if an LED remains on, it may mean that the corresponding optical module has been disabled or has failed; it helps system administrators to quickly identify and solve problems related to optical modules, thereby improving the reliability and maintainability of the system.

[0034] In an embodiment of the present application, the model detection integrated circuit of the multiple single-mode SFP light sources also includes a power supply circuit, which is used to power the main control unit, the SFP optical module control unit and the ROSA device return signal measurement unit. Specifically, the power supply circuit mainly uses a 24V power supply to power the present application, including the SFP power supply, the main control unit and the analog power supply. Chips U3, U6, U8, and U11 are a BUCK step-down module; one of the MCU power supplies is reduced to 4.5V by U3 and then reduced to 3.3V by U4 linear regulator to provide power to the AX58200 processor; the other one is reduced to 4.5V by U3 and then reduced to 3.3V by U5 linear regulator to provide power to the STM32H730 processor, which can effectively reduce overall power consumption, heat generation, and wave fluctuations; the SFP power supply is provided by two DCDC power supplies, and each DCDC power supply provides power to a separate linear regulator to ensure that each SFP power supply provides a stable 3.3V constant voltage source with a maximum of 800mA; after 24V input, D1 (transient suppression tube) and F1 (self-recovery fuse) are added to ensure that the input current does not exceed 1.1A and the input voltage does not exceed 26V.

[0035] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention is disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent changes and modifications made to the above embodiments according to the technology of the present invention are within the scope of the technical solution of the present invention without departing from the content of the technical solution of the present invention.

Claims

1. An integrated system for transmitting and receiving backhaul detection of multiple SFP light sources, characterized in that: It includes a main control unit, an SFP optical module control unit and a ROSA device return signal measurement unit; The SFP optical module control unit includes a multi-way switch chip U16, an indicator light module and multiple SFP optical module interfaces, the indicator light module and the multiple SFP optical module interfaces are respectively connected to the multi-way switch chip U16, and the main control unit is respectively connected to the multi-way switch chip U16 and the multiple SFP optical module interfaces; the indicator light module is used to indicate the working status of multiple optical modules; The ROSA device return signal measurement unit includes an analog-to-digital conversion chip U15, a common-mode data acquisition module and a differential-mode data acquisition module. The analog-to-digital conversion chip U15, the common-mode data acquisition module and the differential-mode data acquisition module are respectively connected to the main control unit, and the analog-to-digital conversion chip U15 is connected to the differential-mode data acquisition module.

2. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The model of the multi-way switch chip U16 is TCA9548APWR.

3. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The model of the analog-to-digital conversion chip U15 is 3PA1030.

4. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The differential mode data acquisition module includes an operational amplifier U14, an operational amplifier U18.2, a resistor R40, a resistor R41, a resistor R44, a resistor R45, a resistor R46, a resistor R47, a resistor R48, a resistor R49, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a capacitor C41, a capacitor C42, a capacitor C44, a capacitor C45, a capacitor C46, ​​a capacitor C47, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a Zener diode D4, two Zener diodes D2 and two Zener diodes D3; one end of the resistor R45 is respectively connected to one end of the capacitor C42, one end of the capacitor C41, one end of the resistor R40 and the first pin of the operational amplifier U14; one end of the resistor R46 is respectively connected to One end of the capacitor C55, one end of the resistor R53, one end of the capacitor C56, one end of the resistor R54, and the eighth pin of the operational amplifier U14 are connected, the anode of one of the voltage-stabilizing diodes D2 is connected to the cathode of another voltage-stabilizing diode D2 and then connected to the other end of the resistor R45, the anode of one of the voltage-stabilizing diodes D3 is connected to the cathode of another voltage-stabilizing diode D3 and then connected to the other end of the resistor R46; the second pin of the operational amplifier U14 is connected to one end of the capacitor C44 and the analog-to-digital conversion chip U15, the other end of the capacitor C44 is grounded, the other end of the resistor R54 is connected to one end of the resistor R55 and the output pin of the operational amplifier U18.2, the in-phase input end of the operational amplifier U18.2 is connected to the analog-to-digital conversion chip U15, and the inverting input end of the operational amplifier U18.2 and the other end of the resistor R55 are respectively connected to the main control unit; The other end of capacitor C42 is connected to one end of resistor R44 and the fifth pin of operational amplifier U14, the other end of resistor R40, the other end of resistor R44 and the other end of capacitor C41 are respectively connected to one end of resistor R41, the other end of resistor R41 is respectively connected to one end of capacitor C47 and one end of capacitor C49, the other end of capacitor C47 is grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, the third pin of operational amplifier U14 is connected to one end of capacitor C45, one end of capacitor C46 and one end of resistor R52, the other end of resistor R52 is connected to the seventh pin of operational amplifier U14, the other end of capacitor C45 and the other end of capacitor C46 are grounded, The four pins and the other end of capacitor C55 are respectively connected to one end of resistor R47, the other end of resistor R47, the other end of resistor R53 and the other end of capacitor C56 are respectively connected to one end of resistor R48, the other end of resistor R48, the other end of capacitor C49, one end of capacitor C53 and the cathode of Zener diode D4 are respectively connected to one end of resistor R49, the other end of resistor R49 and one end of capacitor C52 are respectively connected to analog-to-digital conversion chip U15, and the other end of capacitor C52 is grounded; the sixth pin of operational amplifier U14 is respectively connected to one end of capacitor C50 and one end of capacitor C51, and the other end of capacitor C50 and the other end of capacitor C51 are grounded.

5. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 4, characterized in that: The analog-to-digital conversion chip U15 is provided with an AIN pin and a VREF pin, and the AIN pin of the analog-to-digital conversion chip U15 is connected to the other end of the resistor R49; the differential mode data acquisition module also includes a resistor R57, a resistor R58, a resistor R59, a resistor R61, a capacitor C58, a capacitor C59, a capacitor C63, a capacitor C64 and an operational amplifier U18.1; The VREF pin of the analog-to-digital conversion chip U15 is connected to one end of the resistor R61, and the other end of the resistor R61 is respectively connected to one end of the resistor R62, one end of the capacitor C63, one end of the capacitor C64 and the non-inverting input end of the operational amplifier U18.1, the output end of the operational amplifier U18.1 is connected to the non-inverting input end of U18.2, the inverting input end of the operational amplifier U18.1 is connected to one end of the resistor R59, one end of the resistor R57, and one end of the capacitor C58, the other end of the resistor R59 is grounded, the eighth pin of the operational amplifier U18.1 is connected to one end of the capacitor C59, the other end of the capacitor C59 is grounded, and the other end of the resistor R57 and the other end of the capacitor C58 are connected to the output end of the operational amplifier U18.

1.

6. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The common-mode data acquisition module includes an operational amplifier U17.1, an operational amplifier U17.2, a resistor R42, a resistor R43, a resistor R50, a resistor R51, a capacitor C43, a capacitor C48 and a capacitor C54. One end of the resistor R42 and one end of the capacitor C48 are connected to the in-phase input end of the operational amplifier U17.1, and the other end of the capacitor C48 is grounded. The inverting input end of the operational amplifier U17.1 and the output end of the operational amplifier U17.1 are respectively connected to one end of the resistor R43, and the other end of the resistor R43 is connected to the ground. One end is connected to the main control unit, the fourth pin of the operational amplifier U17.1 is grounded, the eighth pin of the operational amplifier U17.1 is connected to one end of the capacitor C43, and the other end of the capacitor C43 is grounded; one end of the resistor R50 and one end of the capacitor C54 are connected to the in-phase input terminal of the operational amplifier U17.2, the other end of the capacitor C54 is grounded, the inverting input terminal of the operational amplifier U17.2 and the output terminal of the operational amplifier U17.2 are respectively connected to one end of the resistor R51, and the other end of the resistor R51 is connected to the main control unit.

7. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The multiple SFP optical module interfaces include an optical module interface SFP1, an optical module interface SFP2, an optical module interface SFP3 and an optical module interface SFP4, each of the SFP optical module interfaces includes an SFP_DIS pin and an SFP_FAULT pin, and the indicator light module includes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8; the SFP_DIS pin and the SFP_FAULT pin of the optical module interface SFP1 are respectively connected to LED1 and LED5, the SFP_DIS pin and the SFP_FAULT pin of the optical module interface SFP2 are respectively connected to LED2 and LED6, the SFP_DIS pin and the SFP_FAULT pin of the optical module interface SFP3 are respectively connected to LED3 and LED7, and the SFP_DIS pin and the SFP_FAULT pin of the optical module interface SFP4 are respectively connected to LED4 and LED8.

8. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The main control unit includes a chip U1 and a chip U2. The model of the chip U1 is AX58200, and the model of the chip U2 is STM32H730.

9. The integrated system for transmitting and receiving backhaul detection of multiple SFP light sources according to claim 1, characterized in that: The model detection integrated circuit of the plurality of single-mode SFP light sources further comprises a power supply circuit, and the power supply circuit is used to supply power to the main control unit, the SFP optical module control unit and the ROSA device return signal measurement unit.

Images