Image acquisition card and image acquisition system

Abstract

The invention discloses an image acquisition card and an image acquisition system. The image acquisition card comprises a control signal interface, a Camera Link signal interface, a PCIE interface, a first signal processing circuit, a second signal processing circuit and a control unit, the control signal interface is electrically connected with the control unit through the first signal processing circuit; the Camera Link signal interface is electrically connected with the control unit through the second signal processing circuit; the PCIE interface is connected with the control unit; the control signal interface is used for receiving an image equipment control signal, and the first signal processing circuit is used for isolated transmission of the image equipment control signal; the Camera Link signal interface is used for being connected with image equipment, and the second signal processing circuit is used for signal conversion and signal transmission between the image equipment and the control unit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of image technology, and in particular to an image acquisition card and an image acquisition system. Background Art

[0002] The digital interfaces of industrial cameras mainly include the following categories: Camera Link interface, IEEE 1394 interface, USB interface, network interface, and CoaXPress interface. The Camera Link interface is specially developed for the special application requirements of industrial cameras (large image data volume and high bandwidth requirements).

[0003] Traditional image cards use relatively simple or low-speed interface standards. These interfaces have obvious bottlenecks in data transmission rate and low processing bandwidth, making it difficult to meet the needs of fast transmission of high-resolution and high-frame-rate image data. Some products do not support the complete Camera Link protocol and are not suitable for today's high-resolution industrial cameras. In terms of signal processing circuits, traditional designs usually lack the ability to fine-tune processing for different types of signals. There are often no effective isolation measures for image device control signals, making it easy for external interference signals to penetrate into the system, affecting the accuracy and stability of the control signals, and causing abnormal operation of image acquisition equipment, such as inaccurate exposure time and incorrect gain settings. Summary of the invention

[0004] The present invention provides an image acquisition card and an image acquisition system, so as to achieve the purpose of solving at least one defect in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides an image acquisition card, comprising:

[0006] Control signal interface, Camera Link signal interface, PCIE interface, first signal processing circuit, second signal processing circuit, control unit;

[0007] The control signal interface is electrically connected to the control unit through the first signal processing circuit;

[0008] The Camera Link signal interface is electrically connected to the control unit through the second signal processing circuit;

[0009] The PCIE interface is connected to the control unit;

[0010] The control signal interface is used to receive an image device control signal, and the first signal processing circuit is used for isolated transmission of the image device control signal;

[0011] The Camera Link signal interface is used to connect to an image device, and the second signal processing circuit is used for signal conversion and signal transmission between the image device and the control unit.

[0012] Optionally, the control unit includes an FPGA and a memory.

[0013] Optionally, the first signal processing circuit includes an optocoupler isolator, and the optocoupler isolator is used for isolated transmission of the image device control signal.

[0014] Optionally, the first signal processing circuit includes a first signal processing module, a second signal processing module, and a third signal processing module;

[0015] The first signal processing module is used for processing the acquisition signal of the image device;

[0016] The second signal processing module is used for processing the image device control signal;

[0017] The third signal processing model is used for driving signal processing of the image device.

[0018] Optionally, the control signal interface adopts an SDR15 terminal.

[0019] Optionally, the Camera Link signal interface includes a first CL interface and a second CL interface.

[0020] Optionally, the first CL interface and the second CL interface use SDR26 terminals.

[0021] Optionally, the PCIE interface adopts a PCIE x4 interface.

[0022] Optionally, the FPGA is configured with 2 DDR3 memories.

[0023] In a second aspect, an embodiment of the present invention further provides an image acquisition system, comprising any image acquisition card described in the embodiment of the present invention.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention proposes an image acquisition card, which is designed to receive image device control signals by using a control signal interface, and effectively prevents the influence of external interference signals on the control unit through isolated transmission of the first signal processing circuit, thereby ensuring the accurate transmission of the control signal. The design uses a second signal processing circuit to convert the data in the Camera Link standard format into a data format suitable for processing by the control unit, thereby improving the data processing efficiency. The standard Camera Link signal interface and PCIE interface are adopted, which can be compatible with a variety of image devices and host computers. The internal logic of the configuration control unit can be flexibly programmed, so that the image acquisition card can be easily expanded in function, such as adding support for new image device control signals, upgrading data processing algorithms, etc., to meet the ever-evolving image acquisition technology needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural block diagram of an image acquisition card in an embodiment;

[0026] Figure 2 is a schematic diagram of an FPGA chip in an embodiment;

[0027] Figure 3 is a schematic diagram of a DDR3 chip in an embodiment;

[0028] Figure 4 is a schematic diagram of a second signal processing circuit in an embodiment;

[0029] Figure 5 is a schematic diagram of a first signal processing module in an embodiment;

[0030] Figure 6 is a PCIE interface circuit diagram in an embodiment;

[0031] Figure 7 It is a structural block diagram of another image acquisition card in the embodiment. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0033] Embodiment 1

[0034] Figure 1 is a structural block diagram of the image acquisition card in the embodiment, refer to Figure 1 , the image acquisition card includes:

[0035] Control signal interface 100, Camera Link signal interface 200, PCIE interface 300, first signal processing circuit 400, second signal processing circuit 500, control unit 600;

[0036] The control signal interface 100 is electrically connected to the control unit 600 through the first signal processing circuit 400;

[0037] The Camera Link signal interface 200 is electrically connected to the control unit 600 via the second signal processing circuit 500;

[0038] The PCIE interface 300 is connected to the control unit 600;

[0039] The control signal interface 100 is used to receive the image device control signal, and the first signal processing circuit 400 is used for the isolated transmission of the image device control signal;

[0040] The Camera Link signal interface 200 is used to connect to an image device, and the second signal processing circuit 500 is used for signal conversion and signal transmission between the image device and the control unit 600 .

[0041] Exemplarily, in this solution, the control signal interface 100 is electrically connected to the control unit 600 through the first signal processing circuit 400, and the control signal interface 100 is used to receive the image device control signal, wherein the image device control signal can be manually input or automatically input by a designated device;

[0042] In this solution, the image device control signal may include an image device start / stop control signal, an exposure control signal, a gain adjustment signal, an IO control signal, an encoder signal, and the like.

[0043] In this solution, the first signal processing circuit 400 is used to realize isolated transmission of the image device control signal, and effectively prevents the influence of external interference signals on the control unit by electrically isolating the input control signal from the internal circuit, while ensuring the accurate transmission of the image device control signal.

[0044] Exemplarily, in this solution, the Camera Link signal interface 200 is electrically connected to the control unit 600 via the second signal processing circuit 500. The Camera Link signal interface 200 is used to connect to an image device to achieve transmission of image data, synchronization signals, etc.;

[0045] The second signal processing circuit 500 is mainly used for signal conversion and signal transmission between the image device and the control unit 600, and converts the data in the Camera Link standard format into a data format that can be processed by the control unit 600;

[0046] For example, the second signal processing circuit 500 may be used to convert the LVDS signal output by the image device into a signal of a specified type (eg, a TTL signal) that the control unit 600 may receive;

[0047] Alternatively, convert the 80-bit Camera Link data to a 32-bit internal data bus format to improve data processing efficiency;

[0048] The second signal processing circuit 500 may also be used to convert a control signal of a specified type (such as a TTL signal) output by the control unit 600 for the image device into an LVDS signal that can be received by the image device;

[0049] In this solution, according to design requirements, the second signal processing circuit 500 may have functions such as signal filtering and signal amplification;

[0050] The second signal processing circuit 500 may include a high-speed operational amplifier, which amplifies the weak signal received by the Camera Link signal interface to meet the requirements of subsequent circuit processing;

[0051] The second signal processing circuit 500 may further include a filtering module, which filters out high-frequency noise or low-frequency interference in the signal to ensure the purity of the image data signal.

[0052] Exemplarily, in this solution, the PCIE interface 300 is connected to the control unit 600, and the image acquisition card is connected to the host computer through the PCIE interface 300, wherein the transmission bandwidth of the PCIE interface 300 can be as high as 8GT / s, which can realize high-speed image data transmission to the host computer.

[0053] Exemplarily, in this solution, the control unit 600 plays a core control role in the image acquisition card, and its internal logic can be flexibly programmed as needed. The control unit 600 is configured to coordinate the signal flow between the control signal interface, the Camera Link signal interface 200 and the PCIE interface 300, and control the image data acquisition, processing and transmission process;

[0054] For example, when the control signal interface receives the capture start signal of the image device, the control unit 600 starts the second signal processing circuit 500 to process the image data transmitted from the Camera Link signal interface 200, and transmits the processed image data to the host computer through the PCIE interface 300.

[0055] Exemplarily, in this solution, the hardware of the image acquisition card can be selected according to the design and use requirements. For example, the control signal interface 100 can use a standard DB9 interface, the Camera Link signal interface can use a standard CameraLink connector, and the PCIE interface can use a PCI Express Gen3 standard interface chip;

[0056] The control unit 600 may use FPGA, and the FPGA chip may be selected from the Xilinx Virtex-7 series to meet the complex control and processing requirements of the image acquisition card.

[0057] Exemplarily, in this solution, the control unit 600 may be configured to include a control signal processing module, a Camera Link signal processing module, a PCIE transmission module, and a status monitoring module;

[0058] The control signal processing module is responsible for analyzing the control signal transmitted from the first signal processing circuit and performing corresponding operations according to different control signals, such as setting parameters of the Camera Link signal processing module, starting or stopping image data acquisition, etc.;

[0059] The Camera Link signal processing module realizes the functions of caching, checking, error correction and data format conversion of the image data transmitted from the second signal processing circuit;

[0060] The PCIE transmission module realizes PCIE interface communication with the host computer and transmits the processed image data to the host computer according to the PCIE protocol;

[0061] The status monitoring module monitors the working status of each interface and circuit of the image acquisition card in real time, such as monitoring the signal strength of the CameraLink signal interface, the transmission error rate of the PCIE interface, etc. When an abnormal situation is detected, an alarm message is sent to the host computer through an internal interrupt signal, and corresponding measures are taken, such as reinitializing related circuits or adjusting data processing parameters.

[0062] Exemplarily, in this solution, when an image acquisition card is used to acquire image data, a control signal, such as an initialization signal, an acquisition parameter setting signal, etc., is first sent to the image acquisition card through the control signal interface 100;

[0063] These signals enter the control unit after being isolated and transmitted by the first signal processing circuit 400. The control unit 600 performs corresponding initialization settings on the image acquisition card according to the received control signals, and controls the image device to start working according to the preset parameters.

[0064] After the image device starts to collect image data, it transmits the image data, synchronization signal, etc. to the second signal processing circuit 500 through the Camera Link signal interface 200. After the second signal processing circuit 500 processes these signals, it transmits the processed image data to the control unit 600.

[0065] The control unit 600 caches and preliminarily processes the received image data, for example, performs operations such as image data verification and error correction, and then transmits the processed image data to the host computer through the PCIE interface 300;

[0066] After the host computer receives the image data, it can perform further image processing, analysis, and storage operations.

[0067] This embodiment proposes an image acquisition card, which is designed to use a control signal interface to receive image device control signals. Through the isolated transmission of the first signal processing circuit, the influence of external interference signals on the control unit is effectively prevented, and the accurate transmission of the control signal is ensured. The design uses a second signal processing circuit to convert the data in the Camera Link standard format into a data format suitable for processing by the control unit, thereby improving the data processing efficiency. The standard Camera Link signal interface and PCIE interface are adopted, which can be compatible with a variety of image devices and host computers. The internal logic of the configuration control unit can be flexibly programmed, so that the image acquisition card can be easily expanded in function, such as adding support for new image device control signals, upgrading data processing algorithms, etc., to meet the ever-evolving image acquisition technology needs.

[0068] exist Figure 1 On the basis of the illustrated solution, in one possible implementation scheme, the control unit includes an FPGA and a memory.

[0069] Exemplarily, in this solution, the control unit adopts an FPGA chip, which can meet the complex control and processing requirements of the image acquisition card based on the rich logic resources, high-speed clock resources and a large number of interface resources possessed by the FPGA chip.

[0070] Exemplarily, in this solution, the memory may be DDR3, and its storage capacity may be selected according to the demand (eg, 512MB to 4GB). DDR3 has a high read and write speed, which can meet the image acquisition card's demand for fast data storage and reading.

[0071] Exemplarily, in this solution, the memory can be configured to store the configuration information of the FPGA chip. When the image acquisition card is started, the FPGA chip reads the initial configuration data from the area and completes its own initialization settings, such as setting the initial state of each functional module, defining the working mode of the interface, etc.;

[0072] The memory may also be configured as a cache area for image data, for temporarily storing image data transmitted from the Camera Link signal processing module;

[0073] For example, during the image acquisition process, when the camera acquires images at a higher frame rate, the image data is first stored in the cache area, and then the FPGA chip processes and transmits the data according to a certain algorithm and sequence to avoid data loss due to the data processing speed not keeping up with the acquisition speed.

[0074] Figure 2 is a schematic diagram of the FPGA chip in the embodiment, Figure 3 is a schematic diagram of a DDR3 chip in an embodiment, refer to Figure 2 and Figure 3 ,In this solution, the signal used by FPGA can be XC7K160T-2FFG676, and FPGA can be configured with onboard DDR3 ,memory;

[0075] In this solution, the pin definitions of the FPGA chip and the DDR3 chip are the same as those recorded in the corresponding manuals. The configured peripheral circuits belong to the typical applications of the corresponding chips, and their specific contents will not be described in detail.

[0076] Based on any of the foregoing solutions, in one possible implementation, the first signal processing circuit includes an optocoupler isolator, and the optocoupler isolator is used for isolated transmission of image device control signals.

[0077] Exemplarily, in this solution, the first signal processing circuit may include an input protection circuit and a signal conditioning circuit in addition to the optocoupler isolator;

[0078] The input protection circuit is located at the input end of the circuit and can be composed of a transient suppression diode and a resistor. The transient suppression diode can quickly respond and suppress the overvoltage pulse that may appear on the input signal line;

[0079] The signal conditioning circuit is connected to the input end of the optocoupler isolator, and its main function is to pre-process the input image device control signal to meet the input requirements of the optocoupler isolator;

[0080] The signal conditioning circuit may include a filter network composed of capacitors, inductors and resistors, which can filter out high-frequency noise and clutter in the signal to improve the quality of the signal;

[0081] When the control signal processed by the input protection circuit and the signal conditioning circuit is input to the input end of the optocoupler isolator, the light-emitting diode inside the optocoupler isolator emits light, and its light signal is received by the phototransistor and converted into an electrical signal, thereby outputting the isolated control signal at the output end.

[0082] Figure 4 is a schematic diagram of the second signal processing circuit in the embodiment, refer to Figure 4 In one possible implementation, the second signal processing circuit uses capacitors C1, C2, inductor U2, and resistor R2 to form a filter network;

[0083] The input signal is isolated by the optocoupler TLP291 and transmitted to the input pin FPGAIN1 of the FPGA.

[0084] On the basis of any of the foregoing solutions, in one possible implementation, the first signal processing circuit includes a first signal processing module, a second signal processing module, and a third signal processing module;

[0085] The first signal processing module is used for processing the acquisition signal of the image device, the second signal processing module is used for processing the control signal of the image device, and the third signal processing module is used for processing the driving signal of the image device.

[0086] Exemplarily, in this solution, the first signal processing module is used to realize the reception of image data, converting the LVDS signal of the CameraLink standard into a TTL signal that can be received by the FPGA. Specifically, the signals that can be output by the first signal processing module include an image data output signal, a data synchronization output signal, and a clock signal;

[0087] In this solution, the second signal processing module is used to output a control signal for the image device. Specifically, the second signal processing module can convert the TTL level output by the FPGA into an image device control signal in LVDS format;

[0088] In this solution, the third signal processing module is used to realize serial communication between the imaging device and the FPGA. The serial communication signal includes a driving signal output from the FPGA to the imaging device and a serial receiving signal output from the imaging device to the FPGA. The third signal processing module is used to realize high-low level conversion of the driving signal and the serial receiving signal.

[0089] Figure 5 is a schematic diagram of the first signal processing module in the embodiment, refer to Figure 5 In one possible implementation, the first signal processing module may use a DS90CR288 chip, and the DS90CR288 chip is configured to receive the LVDS signal of the Camera Link interface and output a 3.3V digital signal to the FPGA;

[0090] The DS90CR288 chip supports signal conversion up to 85MHz. Three DS90CR288 chips fully support all Camera Link transmission modes (Lite / Base / Medium / Full / 80-Bit).

[0091] Exemplarily, in this solution, the models of the second signal processing module and the third signal processing module can be selected according to demand. For example, the second signal processing module can use a DS90LV047 chip, and the third signal processing module can use a DS90LV019 chip.

[0092] Based on any of the foregoing solutions, in one possible implementation, the control signal interface uses an SDR15 terminal.

[0093] Exemplarily, in this solution, the electrical characteristics of the SDR15 terminal enable it to support high-speed signal transmission, and its transmission rate can be as high as 1.25 Gbps, which can meet the requirements of the image acquisition card for fast control signal response.

[0094] Based on any of the foregoing solutions, in one possible implementation, the Camera Link signal interface includes a first CL interface and a second CL interface.

[0095] For example, in a complex image acquisition system, a single Camera Link interface often cannot meet the scenarios of connecting multiple image devices or having different data transmission requirements;

[0096] In this solution, the Camera Link signal interface is designed to include a first CL interface and a second CL interface, so that the image acquisition card can be used in some multi-camera visual inspection systems that need to connect cameras of different types or different resolutions at the same time, or in scenarios where image data needs to be diverted for processing.

[0097] Exemplarily, in this solution, the designs of the first CL interface and the second CL interface may be the same or different, and the first CL interface and the second CL interface may be configured to work in coordination;

[0098] In this solution, the first CL interface adopts the standard Camera Link full-configuration interface design, which has 26 pins and can achieve high-speed and large-capacity data transmission;

[0099] The pin definition of the first CL interface follows the Camera Link standard, including data transmission pins for transmitting the original image data; synchronization signal pins for ensuring that the image acquisition card can accurately receive and process the frame and line information of the image data; control signal pins for transmitting some basic control signals of the camera, such as exposure control signal feedback and gain control signal feedback;

[0100] The second CL interface can be designed based on the Camera Link basic configuration interface, which has 14 pins and is mainly used to transmit some auxiliary data or data with low bandwidth requirements. Some pins of this interface are used to transmit camera status information data, such as camera temperature information, working mode information, etc.

[0101] In this solution, the image acquisition card is configured with two Camera Link signal interfaces, which enables the image acquisition card to connect to multiple different types of image devices at the same time, greatly expanding the application scope of the image acquisition card. The parallel data transmission of the two interfaces and the coordinated processing of the control unit improve the processing speed and transmission efficiency of image data. In some application scenarios with high requirements for data real-time performance, such as image detection in high-speed automated production lines, image data can be quickly and accurately acquired and processed, improving production efficiency and product quality.

[0102] Based on the solution that the aforementioned Camera Link signal interface includes a first CL interface and a second CL interface, in one feasible implementation scheme, the first CL interface and the second CL interface use SDR26 terminals.

[0103] Exemplarily, in this solution, the structures and pin definitions of the first CL interface and the second CL interface are the same, and the pin definition of the first CL interface complies with the Camera Link standard.

[0104] Exemplarily, in this solution, the first CL interface and the second CL interface can be used independently as a complete CameraLink signal interface, or the first CL interface and the second CL interface can be used in coordination;

[0105] For example, the first CL interface transmits main image data at a rate of 1.5 Gbps, and the second CL interface transmits auxiliary data at a rate of 0.5 Gbps, and both transmit data simultaneously;

[0106] Alternatively, the first CL interface and the second CL interface can be connected to different types of cameras, and synchronously operate the cameras connected to them;

[0107] When it is necessary to perform accurate time stamp marking or image fusion processing on the images captured by the main and auxiliary cameras, the control unit can accurately adjust the processing order and time reference of the image data according to the synchronization signals of the first CL interface and the second CL interface.

[0108] Figure 6 is a PCIE interface circuit diagram in the embodiment, see Figure 6 Based on any of the aforementioned solutions, in one possible implementation scheme, the PCIE interface adopts a PCIE x4 interface.

[0109] In this solution, according to the actual bandwidth requirements, a x4-channel PCIE interface is selected to achieve high-speed and real-time transmission of image data from the acquisition card to the host computer.

[0110] Based on the aforementioned solution in which the control unit includes an FPGA and a memory, in one possible implementation scheme, the FPGA is configured with two DDR3 memories.

[0111] In this solution, by configuring two DDR3 memories, the data storage capacity of the image acquisition card is increased, which can meet the cache requirements of a large amount of image data. At the same time, the data management functions of the two DDR3 memories of FPGA, such as data cache management algorithm and dynamic allocation of storage space, enable data to be reasonably stored and efficiently used.

[0112] Figure 7 This is another structural block diagram of an image acquisition card in the embodiment, refer to Figure 7 Based on any of the above solutions, in one possible implementation scheme, the image acquisition card includes:

[0113] Control signal interface 100, first CL interface 201, second CL interface 202, PCIE interface 300, first signal processing circuit 400, second signal processing circuit 500, FPGA 601, DDR3-1 602, DDR3-2 603, PCIE interface 300;

[0114] The control signal interface 100 is connected to the FPGA 601 through the first signal processing circuit 400, the first CL interface 201 and the second CL interface 202 are connected to the FPGA 601 through the second signal processing circuit 500, the PCIE interface 300 is connected to the FPGA 601, and the FPGA 601 is configured with DDR3-1 602 and DDR3-2 603.

[0115] refer to Figure 2 to Figure 6 ,In this solution, the model of FPGA601 used is XC7K160T-2FFG676, which belongs to the 28nm Kintex series of Xilinx ,with 2 512MB DDR3 memories on board, and connected to the PC through the PCIE X4 ,interface;

[0116] The software of FPGA 601 is divided into two parts: image processing unit and external signal processing unit. The image processing unit inputs the original image signal from the first CL interface 201 and the second CL interface 202 (SDR26 terminal) of the acquisition card, processes the source image according to the user configuration and stores it in the memory. The PC accesses the memory of FPGA 601 through the PCIE interface 300 to obtain the image data;

[0117] The external signal processing unit inputs the external signal from the control signal interface 100 (DR15 terminal) of the acquisition card, and the FPGA 601 processes the external signal into a trigger signal of the camera according to the user configuration and sends it to the camera in real time;

[0118] External signals generally include encoders, IO control, start / stop control, etc. The external signals are transmitted to FPGA601 after being optically isolated by the first signal processing circuit 400. The main function is to facilitate the user's controller or encoder control board to control the connected camera;

[0119] The second signal processing circuit 500 includes a DS90CR288 chip, which is responsible for receiving the LVDS signal of the Camera Link interface and outputting a 3.3V digital signal to the FPGA;

[0120] The PCIE interface 300 is responsible for the transmission between the acquisition card and the PC, using the PCIE2.0 X4 mode, supporting a maximum transmission speed of 2000MB / s. The FPGA side uses an internal XDMA module to access the DDR3 memory through the Xilinx AXI bus.

[0121] In this solution, when the image acquisition card is working, FPGA601 obtains the user trigger configuration information, selects the external signal source according to the user trigger mode, generates the standard trigger signal according to the user configuration after the signal source is delayed, filtered, multiplied, and divided, and selects the output channels CC1 to CC4 of the Camera Link camera according to the user configuration, and outputs the trigger signal to the camera;

[0122] FPGA 601 obtains user image configuration information, recovers clock and line field signals according to user CL mode, collects original pixel signals of complete CL image, intercepts required effective pixels according to user CL mode, remaps and arranges pixels according to user tap mode, and caches image data for memory. PC accesses and obtains memory data in DDR3 through PCIE interface 300.

[0123] In this solution, the image acquisition card complies with the Camera Link v2.0 standard (compatible with v1.1), supports PCI Express Gen2 (compatible with Gen1.1), supports a maximum image transfer rate of 850 MB / S, supports a maximum pixel clock of 85 MHz, supports data formats of 8 / 10 / 12 / 14 / 16 bits, supports monochrome, Bayer, and color linear and area array cameras, supports all Camera Link protocol transmission modes (Lite / Base / Medium / Full / 80-Bit), supports standard and custom Tap arrangements, and supports external trigger signal input control.

[0124] Embodiment 2

[0125] This embodiment provides an image acquisition system, including any image acquisition card recorded in the first embodiment. The implementation method and beneficial effects of the image acquisition card are the same as the corresponding contents recorded in the first embodiment, and the specific contents are not repeated here.

[0126] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An image acquisition card, characterized in that: include: Control signal interface, Camera Link signal interface, PCIE interface, first signal processing circuit, second signal processing circuit, control unit; The control signal interface is electrically connected to the control unit through the first signal processing circuit; The Camera Link signal interface is electrically connected to the control unit through the second signal processing circuit; The PCIE interface is connected to the control unit; The control signal interface is used to receive an image device control signal, and the first signal processing circuit is used for isolated transmission of the image device control signal; The Camera Link signal interface is used to connect to an image device, and the second signal processing circuit is used for signal conversion and signal transmission between the image device and the control unit.

2. The image acquisition card according to claim 1, characterized in that: The control unit includes an FPGA and a memory.

3. The image acquisition card according to claim 1, characterized in that: The first signal processing circuit includes an optocoupler isolator, and the optocoupler isolator is used for isolated transmission of the image device control signal.

4. The image acquisition card according to claim 1, characterized in that: The first signal processing circuit includes a first signal processing module, a second signal processing module, and a third signal processing module; The first signal processing module is used for processing the acquisition signal of the image device; The second signal processing module is used for processing the image device control signal; The third signal processing model is used for driving signal processing of the image device.

5. The image acquisition card as claimed in claim 1, characterized in that: The control signal interface uses an SDR15 terminal.

6. The image acquisition card according to claim 1, characterized in that: The Camera Link signal interface includes a first CL interface and a second CL interface.

7. The image acquisition card as claimed in claim 6, characterized in that: The first CL interface and the second CL interface use SDR26 terminals.

8. The image acquisition card as claimed in claim 1, characterized in that: The PCIE interface adopts a PCIE x4 interface.

9. The image acquisition card as claimed in claim 2, characterized in that: The FPGA is configured with 2 DDR3 memories.

10. An image acquisition system, characterized in that: The invention comprises the image acquisition card as described in any one of claims 1 to 9.

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