Gate stack structure FeFET and preparation method thereof

Abstract

The invention provides a gate stack structure FeFET and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The FeFET structure comprises a silicon substrate, a source laminated layer, a drain laminated layer, a gate metal electrode, a passivation layer and a contact metal electrode, the gate laminated layer comprises an aluminum oxide channel interface layer and a double-layer hafnium zirconium oxide ferroelectric layer, and a thin aluminum oxide middle interface layer is inserted between the double-layer ferroelectric layer to effectively inhibit continuous growth of crystal grains in the ferroelectric layer. A write pulse with a larger amplitude and a shorter width is applied to the gate region of the FeFET structure, so that the consistency and durability of the FeFET device are synergistically optimized; the preparation process of the FeFET is mature, can be quickly applied to large-scale circuit design of the FeFET, and has a wide application prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-nanoelectronics, and in particular relates to a novel gate stack structure FeFET and a preparation method thereof. Background Art

[0002] With the advent of the big data era, cutting-edge technologies such as artificial intelligence, the Internet of Things, autonomous driving, and cloud computing are developing rapidly. The amount of global data is growing exponentially, and the requirements for data storage and processing are becoming more and more stringent. In the process of data processing, the frequent data transmission between computing units and various storage units has become a bottleneck for further improving computing performance, and it also brings significant power consumption problems. Traditional memory is unable to achieve non-volatility, high storage density, and high-speed data access at the same time, which greatly limits the efficient storage and processing of massive data. In the face of this challenge, it is urgent to develop new storage technologies that have the characteristics of high-speed reading and writing, high integration density, and low energy consumption, and can provide non-volatile storage solutions to meet the future needs of efficient processing of massive data.

[0003] Among the many candidates, hafnium oxide-based ferroelectric field effect transistors (FeFETs) use non-volatile ferroelectric polarization for storage, and have the advantages of ultra-low power consumption, high speed, good miniaturization, etc., and due to the partial flipping characteristics of the ferroelectric layer, it has the ability of multi-level storage. It is considered to be one of the most promising embedded non-volatile storage technologies in the future and may occupy an important position in the future memory architecture. Although FeFET has many advantages, its further development and practical application still face many technical challenges. First of all, the device consistency problem of FeFET has always been a key difficulty in research and development. The hafnium oxide-based ferroelectric film in FeFET has the characteristics of polycrystalline multi-domain and multi-phase coexistence and the random flipping effect of ferroelectric domains, which leads to random phase fluctuations and random dynamic flipping characteristics in the film, making the device consistency of FeFET poor. When the FeFET device is miniaturized, the device consistency of FeFET will further deteriorate due to the reduction in the number of grains in the film and the greater film fluctuations. In addition, another key problem of FeFET is its limited durability, which generally does not exceed 10 6 In FeFETs with multi-level storage, the durability problem becomes more prominent due to the smaller storage window between each state.

[0004] In past studies, optimization has been conducted for the device consistency or durability challenges of FeFET, but the optimized performance has not yet fully met the demand and there is still much room for improvement. In addition, most of the work only optimizes one aspect of device consistency and durability, lacking the coordinated optimization of the two. However, in order to fully tap the potential of FeFET's multi-level storage and good miniaturization, especially for high-density storage applications, the problems of device consistency and durability must be solved at the same time, because any unresolved problem will become a key bottleneck in the application of FeFET devices. In addition, the optimization of FeFET's device structure and operation scheme are indispensable for the coordinated optimization of FeFET reliability mentioned above, and a comprehensive optimization design solution is required to achieve highly consistent and durable FeFET devices. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention proposes a novel gate stack structure FeFET and a preparation method thereof, which is synergistically optimized with the write pulse to simultaneously optimize the device consistency and durability of the FeFET.

[0006] First, in terms of gate stack structure design, unlike the conventional single-layer hafnium zirconium oxide (HZO, in which the ratio of hafnium atoms to zirconium atoms is 1:1) as a ferroelectric layer, the present invention proposes to insert a thin aluminum oxide intermediate interface layer in the middle of the single-layer hafnium zirconium oxide ferroelectric layer to form a double ferroelectric layer structure of HZO+HZO, thereby increasing the storage window of FeFET and optimizing the device consistency and durability of FeFET. Secondly, in terms of write pulse optimization, the present invention proposes to use a pulse with a larger amplitude but a smaller width for writing, which can more effectively optimize the device consistency of FeFET and improve durability compared to using a write pulse with a smaller amplitude but a larger width.

[0007] The formed double hafnium zirconium oxide ferroelectric layer has a larger coercive electric field and polarization strength than a single-layer hafnium zirconium oxide ferroelectric layer of the same thickness, thereby increasing the storage window of FeFET, effectively reducing the overlap between different states, and helping to better distinguish different states. The inserted aluminum oxide intermediate interface layer can effectively inhibit the continuous growth of grains in the ferroelectric layer, thereby reducing the grain size in the ferroelectric layer, ensuring that the FeFET device still has a large number of ferroelectric grains after miniaturization, thereby inhibiting the fluctuation of the ferroelectric layer and optimizing the device consistency of FeFET. In addition, the inserted aluminum oxide intermediate interface layer can inhibit the movement and large-scale aggregation of defects in the ferroelectric layer, avoid the formation of a leakage path that runs through the entire ferroelectric layer, effectively avoid the breakdown effect of FeFET, and thus optimize the durability of FeFET.

[0008] Specifically, the technical solution of the present invention is as follows:

[0009] A gate stack structure FeFET, comprising a silicon substrate, a source, a drain, a gate stack, a gate metal electrode, a passivation layer and a contact metal electrode; the surface area of ​​the silicon substrate is divided into an inactive area, a source and drain area, a gate area, a source and drain area and an inactive area in sequence, the inactive area is a silicon dioxide layer, the source and drain materials of the source and drain area are located in the silicon substrate and flush with the surface of the silicon substrate, the gate area is a gate stack structure and a gate metal electrode thereon, the gate stack structure is a patterned aluminum oxide channel interface layer and a double-layer hafnium zirconium oxide (HZO+HZO) ferroelectric layer from bottom to top, the double-layer hafnium zirconium oxide iron The ferroelectric layer is composed of two hafnium zirconium oxide ferroelectric layers of uniform thickness and an aluminum oxide intermediate interface layer located between the two hafnium zirconium oxide ferroelectric layers. The passivation layer covers the gate metal electrode, the source and drain regions and the silicon dioxide layer in the non-active region for electrical isolation and contamination prevention. The contact metal electrode is connected to the source, drain and gate metal electrodes through the through holes in the passivation layer. A write pulse with a larger amplitude and a shorter width is applied to the gate region of the FeFET structure to synergistically optimize the consistency and durability of the FeFET device. The amplitude of the write pulse is greater than the flipping voltage of most ferroelectric domains in the ferroelectric layer.

[0010] Furthermore, the silicon substrate may be a p-type silicon substrate for n-type FeFET and an n-type silicon substrate for p-type FeFET; the p-type substrate may be a silicon substrate doped with lower concentration of boron, and the n-type substrate may be a silicon substrate doped with lower concentration of arsenic or phosphorus.

[0011] Furthermore, in the FeFET, the aluminum oxide channel interface layer is grown by atomic layer deposition and has a thickness of 1 to 3 nm.

[0012] Furthermore, in the FeFET, each layer of hafnium zirconium oxide in the double-layer hafnium zirconium oxide ferroelectric layer is grown by atomic layer deposition, with a thickness of 6 to 10 nm, and the ratio of the number of hafnium atoms to that of zirconium atoms is 1:1.

[0013] Furthermore, in the FeFET, the aluminum oxide middle interface layer in the double-layer hafnium zirconium oxide ferroelectric layer is grown by atomic layer deposition and has a thickness of 1 to 2 nm.

[0014] Furthermore, in the FeFET, the gate metal electrode material should have a relatively small resistivity, a certain thermal stability and mechanical strength, and should also form a certain stress on the ferroelectric layer to induce stable ferroelectricity; materials such as TiN, TaN or W can be selected.

[0015] Furthermore, in the FeFET, the passivation layer may be made of silicon oxide material with a thickness of 300nm to 700nm.

[0016] Furthermore, in the FeFET, the contact metal electrode may be made of materials such as Al, Cr, Cu, Ti, Pt, etc. The contact metal should have a low resistivity and form a good ohmic contact with the source and drain to reduce the contact resistance.

[0017] The present invention also provides a method for preparing the above-mentioned gate stack structure FeFET, comprising the following steps:

[0018] (1) A thick silicon dioxide layer is grown on the entire silicon substrate by wet oxidation or chemical vapor deposition (CVD), and then the active area is defined by photolithography. The silicon oxide layer in the active area is removed by dry etching and wet etching to expose the underlying silicon substrate;

[0019] (2) using a diluted hydrofluoric acid solution to remove the natural oxide layer on the surface of the active silicon substrate;

[0020] (3) Depositing an aluminum oxide channel interface layer on the entire wafer using an atomic layer deposition method;

[0021] (4) using the atomic layer deposition method to grow a double layer of hafnium zirconium oxide ferroelectric layer on the whole wafer, first depositing a layer of hafnium zirconium oxide HZO ferroelectric layer, then a thin layer of aluminum oxide intermediate interface, and finally depositing another layer of hafnium zirconium oxide HZO ferroelectric layer;

[0022] (5) Physical vapor deposition (PVD) method to grow gate metal electrode materials on the entire wafer;

[0023] (6) defining the gate region by photolithography, using photoresist as a barrier layer, and removing the gate metal electrode material and gate stack structure material in the non-gate region by dry etching;

[0024] (7) Performing self-aligned ion implantation on the entire wafer to form source and drain regions, with the area between the source and drain being the channel region;

[0025] (8) Rapid thermal annealing (RTP) is performed on the entire wafer to simultaneously activate the ferroelectricity of the ferroelectric layer and the ions injected into the source and drain regions;

[0026] (9) growing a silicon dioxide passivation layer over the entire wafer by chemical vapor deposition (CVD);

[0027] (10) in the silicon dioxide passivation layer, defining the contact hole regions of the gate metal electrode, source, and drain regions by photolithography, removing the passivation layer in the contact hole region by dry etching and wet etching to form a through hole, and then removing the photoresist;

[0028] (11) growing a contact metal electrode on the entire wafer by physical vapor deposition (PVD), wherein the contact metal fills the through hole and covers the surface above the passivation layer;

[0029] (12) defining the pattern of the contact metal electrode by photolithography, using the photoresist as a barrier layer, removing the contact metal in the remaining area by dry etching, overetching to the passivation layer, and then removing the photoresist;

[0030] (13) Finally, the alloy is annealed to form an ohmic contact between the contact metal and the source and drain.

[0031] Furthermore, the double-layer hafnium zirconium oxide ferroelectric layer and the aluminum oxide channel interface layer deposited by atomic layer deposition in step (3) and step (4) can be grown in the same atomic layer deposition step, and the atomic ratio in the materials can be controlled by controlling the cycle ratio of different materials. The ratio of hafnium atoms to zirconium atoms in the finally formed hafnium zirconium oxide ferroelectric layer is 1:1, so as to ensure good ferroelectricity.

[0032] Furthermore, in the steps (3) and (4), the aluminum oxide boundary channel surface layer and the double-layer hafnium zirconium oxide ferroelectric layer are grown by atomic layer deposition, and trimethylaluminum (TMA), tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water can be used as precursors of aluminum, hafnium, zirconium and oxygen, respectively.

[0033] Furthermore, the step (5) can be performed by depositing the gate metal electrode material on the entire wafer by evaporation, sputtering or other physical vapor deposition methods.

[0034] Furthermore, in step (6), after defining the gate region pattern by electron beam lithography, photoresist is used as a barrier layer and dry etching is performed to remove the gate metal electrode material in the non-gate region and the underlying gate stack structure material.

[0035] Furthermore, in the self-aligned ion implantation of step (7), ion implantation is performed on the entire wafer using appropriate energy and dosage to ensure that the formed source and drain can provide enough carriers without damaging other structures.

[0036] Furthermore, the temperature and time of the rapid thermal annealing process in step (8) need to simultaneously meet the conditions for mixed ferroelectric layer activation and source-drain activation, and need to be flexibly adjusted according to the ferroelectric layer material, gate material, implanted ion type and dosage, with a rough range of: annealing temperature of 500-900°C, and annealing time of 10-120s.

[0037] Furthermore, in step (13), the alloy annealing temperature is 400-450° C. and the time is 30 minutes.

[0038] The technical effects of the present invention are as follows:

[0039] 1. The gate stack structure FeFET of the present invention is used to coordinately optimize the device consistency of the FeFET with a write pulse having a larger amplitude and a shorter width.

[0040] By inserting a thin layer of aluminum oxide (aluminum oxide intermediate interface layer) in the hafnium zirconium oxide ferroelectric layer, a double-layer hafnium zirconium oxide ferroelectric structure is formed, replacing the conventional single-layer hafnium zirconium oxide ferroelectric layer as an optimized gate stack structure. First, compared with a single-layer hafnium zirconium oxide ferroelectric layer of the same thickness, the double-layer hafnium zirconium oxide ferroelectric layer formed has a thinner thickness due to the barrier of the aluminum oxide thin layer inserted in the middle, so that it has better ferroelectricity, which is manifested as a larger polarization intensity and a larger coercive electric field. Therefore, the FeFET with a double-layer hafnium zirconium oxide ferroelectric layer as the ferroelectric layer has a larger storage window, so that different storage states in multi-level storage can be more effectively distinguished. Secondly, after inserting a thin layer of aluminum oxide in the middle of the hafnium zirconium oxide ferroelectric layer, the aluminum oxide thin layer can hinder the continuous growth of grains in the upper and lower hafnium zirconium oxide layers during the ferroelectric annealing crystallization process, so the grain size in each layer of the hafnium zirconium oxide ferroelectric layer is reduced. Compared with a single-layer hafnium zirconium oxide ferroelectric layer, the FeFET with a double-layer hafnium zirconium oxide as the ferroelectric layer has more grains in the ferroelectric layer after the size is reduced, thereby reducing the impact of fluctuations such as the randomness of the phase of a single grain and the grain orientation on the overall properties of the ferroelectric layer, effectively suppressing the fluctuation of the FeFET under the condition of size miniaturization, thereby optimizing the device consistency of the FeFET.

[0041] Compared with a write pulse with a smaller amplitude and a longer width, a write pulse with a larger amplitude and a shorter width is used to write to the FeFET. Since the pulse amplitude is greater than the flipping voltage of most ferroelectric domains in the ferroelectric layer during writing, the random flipping effect of the ferroelectric domains in the ferroelectric layer when the write voltage is close to the flipping voltage can be reduced. Therefore, the fluctuation caused by the random flipping behavior of the ferroelectric domains is reduced, and the consistency of the FeFET device can be further optimized.

[0042] 2. The gate stack structure FeFET of the present invention is used to synergistically optimize the device durability of the FeFET with a write pulse having a larger amplitude and a shorter width.

[0043] Compared with the conventional single-layer hafnium zirconium oxide ferroelectric layer, the aluminum oxide intermediate interface layer inserted in the middle of the optimized double-layer hafnium zirconium oxide ferroelectric layer can effectively prevent defects such as oxygen vacancies from moving and aggregating in large quantities in the ferroelectric layer, inhibiting the formation of leakage paths throughout the entire ferroelectric layer, thereby effectively avoiding the premature dielectric breakdown effect of FeFET during stress cycling and optimizing the durability of FeFET. In terms of write pulse optimization, the write pulse with a larger amplitude and shorter width is used. Due to the shorter pulse width, during the writing process, since the gate stack, especially the channel interface layer, is subjected to stress for a shorter time, the interface traps with a longer capture time constant do not have time to capture charges from the channel. Therefore, the charge captured during the writing process is reduced, and the accumulated interface trap charge during the cycle is reduced, and the durability of FeFET is further optimized.

[0044] 3. The gate stack structure FeFET preparation method proposed in the present invention has a mature preparation process, is compatible with the CMOS process of advanced nodes, and can be effectively applied to FeFET applications at advanced nodes. The materials, equipment, and techniques used in the preparation method are widely used in mature CMOS manufacturing technology and can be effectively compatible with integrated circuit manufacturing technology at advanced nodes. The optimized write pulse will not bring additional hardware cost and design burden to the peripheral circuit design of FeFET, and can be quickly applied to large-scale circuit design of FeFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 4 is a cross-sectional schematic diagram of a double-layer hafnium zirconium oxide ferroelectric layer FeFET according to an embodiment of the present invention.

[0046] Figure 2 Schematic diagram of the process steps of a double-layer hafnium zirconium oxide ferroelectric FeFET according to an embodiment of the present invention, wherein:

[0047] (a) is a cross-sectional view of a silicon substrate in which silicon dioxide is first grown on the entire wafer by chemical vapor deposition, the active area pattern is defined by ultraviolet lithography, and the silicon dioxide in the active area is removed by dry etching and wet etching;

[0048] (b) is a cross-sectional view after an aluminum oxide channel interface layer and a double-layer hafnium zirconium oxide ferroelectric layer are grown on the whole wafer by atomic layer deposition (ALD) based on (a);

[0049] (c) is a cross-sectional view after a gate metal electrode is grown by physical vapor deposition on the basis of (b);

[0050] (d) is a cross-sectional view after the gate region pattern is defined by photolithography and the gate metal electrode and gate stack material in the non-gate region are removed by dry etching based on (c);

[0051] (e) is a cross-sectional view after forming source and drain regions by self-aligned ion implantation based on (d) using photoresist and gate region as barrier layers and annealing;

[0052] (f) is a cross-sectional view after a silicon dioxide passivation layer is grown by chemical vapor deposition on the basis of (e);

[0053] (g) is a cross-sectional view of (f) in which the contact hole pattern is first defined by UV lithography, then the silicon dioxide in the contact hole is removed by dry etching and wet etching, and then the contact metal is grown by physical vapor deposition.

[0054] (h) is a cross-sectional view after the contact electrode pattern is defined by UV lithography and the contact metal material in the remaining area is removed by dry etching based on (g).

[0055] Figure 1 and Figure 2 middle:

[0056] 1——Silicon substrate 2——Silicon dioxide in non-active area

[0057] 3——Aluminum oxide channel interface layer 4——Lower hafnium zirconium oxide ferroelectric layer

[0058] 5——aluminum oxide middle interface layer 6——upper hafnium zirconium oxide ferroelectric layer

[0059] 7——Gate metal electrode 8——Drain

[0060] 9——Source 10——Silicon dioxide passivation layer

[0061] 11 - Contact with Metal

[0062] Figure 3 (a) and (b) are respectively the I of the single-layer hafnium zirconium oxide ferroelectric layer and the double-layer hafnium zirconium oxide ferroelectric layer FeFET of the embodiment of the present invention at four states of 11, 10, 01, and 00 d -V g Graph.

[0063] Figure 4 (a) and (b) are statistical distribution diagrams of threshold voltage extracted in each state of the single-layer hafnium zirconium ferroelectric layer and double-layer hafnium zirconium ferroelectric layer FeFET of the embodiment of the present invention, respectively.

[0064] Figure 5 (a) and (b) are statistical distribution diagrams of threshold voltage of a double-layer hafnium zirconium oxide ferroelectric layer FeFET according to an embodiment of the present invention after being written using a write pulse with a smaller amplitude and a larger width and a write pulse with a larger amplitude and a smaller width, respectively.

[0065] Figure 6 These are the durability test results of the FeFET of the embodiments of the present invention, (a) is the durability result of the single-layer hafnium zirconium oxide ferroelectric layer FeFET; (b) is the durability result of the double-layer hafnium zirconium oxide ferroelectric layer FeFET written with a write pulse with a smaller amplitude and a larger width; (c) is the durability result of the double-layer hafnium zirconium oxide ferroelectric layer FeFET written with a write pulse with a larger amplitude and a smaller width. DETAILED DESCRIPTION

[0066] The present invention will be further described below by way of examples in conjunction with the accompanying drawings.

[0067] like Figure 1As shown, the double-layer hafnium zirconium oxide ferroelectric layer FeFET of this embodiment includes a silicon substrate 1, a non-active region silicon dioxide 2, an aluminum oxide channel interface layer 3, a lower hafnium zirconium oxide ferroelectric 4, an aluminum oxide intermediate interface layer 5, an upper hafnium zirconium oxide ferroelectric layer 6, a gate metal electrode 7, a drain 8, a source 9, a silicon dioxide passivation layer 10 and a contact metal electrode 11. Among them, the aluminum oxide channel interface layer 3 is located on the silicon substrate 1, the lower hafnium zirconium oxide ferroelectric layer 4 is located on the aluminum oxide channel interface layer 3, the aluminum oxide intermediate interface layer 5 is located between the lower hafnium zirconium oxide ferroelectric layer 4 and the upper hafnium zirconium oxide ferroelectric layer 6, the gate metal electrode 7 is located on the upper hafnium zirconium oxide ferroelectric layer 6, the drain 8 and the source 9 are located on both sides below the gate stack in the silicon substrate 1, and the contact metal 11 is connected to the gate metal electrode 7, the drain 8 and the source 9 through contact holes, respectively.

[0068] The process steps of the FeFET preparation method are as follows: Figure 2 As shown, specifically including:

[0069] 1) A 400 nm thick silicon dioxide layer 2 is grown on a silicon substrate 1 by chemical vapor deposition, and then the pattern of the active area is defined by photolithography. Then, using photoresist as a barrier layer, dry etching and wet etching are used to remove the silicon dioxide layer in the active area to expose the silicon substrate 1 in the active area, as shown in FIG. Figure 2 As shown in (a);

[0070] 2) using a diluted hydrofluoric acid solution or a hydrofluoric acid buffer solution to remove the natural oxide layer on the surface of the active silicon substrate 1, and then using an atomic layer deposition (ALD) method to deposit a 3nm thick aluminum oxide channel interface layer 3, an 8nm thick lower hafnium zirconium oxide ferroelectric layer 4, a 1nm thick aluminum oxide middle interface layer 5, and an 8nm thick upper hafnium zirconium oxide ferroelectric layer 6 on the entire wafer, wherein the atomic ratio of hafnium atoms to zirconium atoms in the two hafnium zirconium oxide ferroelectric layers 4 and 6 is 1:1, such as Figure 2 As shown in (b);

[0071] 3) A 50 nm thick TiN gate metal electrode 7 is grown on the whole wafer by physical vapor deposition, such as Figure 2 As shown in (c);

[0072] 4) Define the gate region by photolithography, then use photoresist as a barrier layer and use dry etching to remove the gate metal electrode 7 and the underlying gate stack structure in the non-gate region, such as Figure 2 As shown in (d);

[0073] 5) Perform ion implantation on the entire wafer. Use phosphorus ions with an energy of 33keV and a surface dose of 10 15 cm -2In the gate region, due to the presence of photoresist and gate stack structure blocking, ions will not be injected into the gate structure, while ions on both sides of the gate stack structure are injected into the silicon substrate 1 to form drain 8 and source 9 regions. Subsequently, the whole wafer is subjected to rapid thermal annealing treatment at a temperature of 700°C for 60 seconds to simultaneously activate the ferroelectricity of the ferroelectric layer and the injected ions in the source and drain regions, such as Figure 2 As shown in (e);

[0074] 5) A silicon dioxide passivation layer 10 (thickness of about 500 nm) is grown on the entire wafer by chemical vapor deposition, such as Figure 2 As shown in (f);

[0075] 6) Define the through-hole pattern of the gate metal electrode 7, drain 8, and source 9 regions by photolithography, and form through-holes in the silicon dioxide passivation layer 10 by combining dry etching and wet etching to ensure over-etching, and then remove the photoresist. Then grow the contact metal 11 (about 1 μm) on the whole wafer by physical vapor deposition, and the contact metal 11 fills the through-holes and covers the surface of the silicon dioxide passivation layer 10, as shown in FIG. Figure 2 As shown in (g)

[0076] 7) Define the pattern of the contact metal electrode by photolithography, use the photoresist as a barrier layer, and use dry etching to remove the contact metal in the remaining area, ensuring that the etching reaches the silicon dioxide passivation layer 10, and then remove the photoresist, such as Figure 2 As shown in (h);

[0077] 8) Finally, alloy annealing is performed to form ohmic contact between the contact metal and the source and drain.

[0078] At this point, the FeFET with the gate stack structure can be obtained.

[0079] A comparative device, namely a single-layer hafnium zirconium oxide ferroelectric layer FeFET, was prepared by a method similar to the above, wherein the ferroelectric layer was a single-layer hafnium zirconium oxide ferroelectric layer with a thickness of 16 nm, and the other steps were the same.

[0080] Figure 3 (a) and (b) are respectively the I of the single-layer hafnium zirconium oxide ferroelectric layer and the double-layer hafnium zirconium oxide ferroelectric layer FeFET of the embodiment of the present invention at four states of 11, 10, 01, and 00 d -V g The curves were obtained by testing 32 devices to obtain the device consistency of FeFET. -3 The threshold voltage is extracted at A. The storage window of the single-layer FeFET is 0.8V, while the storage window of the double-layer FeFET is 1.0V, which is larger than that of the single-layer FeFET. And the I d -Vg The curve is more concentrated than that of single-layer hafnium zirconium oxide ferroelectric layer FeFET, indicating that its device consistency is better.

[0081] Figure 4 (a) and (b) are the statistical distributions of the threshold voltages extracted from the single-layer hafnium zirconium oxide ferroelectric layer and the double-layer hafnium zirconium oxide ferroelectric layer FeFET of the embodiment of the present invention in four states: 11, 10, 01, and 00. By fitting each threshold voltage distribution with a Gaussian distribution and extracting its corresponding standard deviation, the average standard deviations of the two FeFETs can be calculated respectively. The average standard deviation of the single-layer hafnium zirconium oxide ferroelectric layer FeFET is 0.042V, while the average standard deviation of the double-layer hafnium zirconium oxide ferroelectric layer FeFET is 0.027V. The average standard deviation of the double-layer hafnium zirconium oxide ferroelectric layer FeFET is smaller, proving that the double-layer hafnium zirconium oxide ferroelectric layer FeFET after gate stack optimization has better device consistency.

[0082] Figure 5 (a) and (b) are the threshold voltage statistical distributions of the double-layer hafnium zirconium oxide ferroelectric layer FeFET of the embodiment of the present invention after being written using a write pulse with a smaller amplitude and a larger width and a write pulse with a larger amplitude and a smaller width. Similarly, after Gaussian distribution fitting of the threshold voltage distribution of each state of 11, 10, 01, and 00, the average standard deviations after writing using the two write pulses were calculated to be 0.036V and 0.027V, respectively. The average standard deviation of writing using a write pulse with a larger amplitude and a smaller width is smaller, indicating that the device consistency after writing is better.

[0083] Figure 6 The durability test results of FeFET of the embodiment of the present invention are shown in Figure 2. (a) is the durability test result of single-layer hafnium zirconium oxide ferroelectric layer FeFET. 7 (b) shows the durability of the double-layer hafnium zirconium oxide ferroelectric FeFET using a write pulse with a smaller amplitude and a larger width. Its durability is improved to more than 10 8 The double-layer hafnium zirconium oxide ferroelectric layer after the gate stack optimization effectively suppressed the breakdown effect of FeFET and optimized the durability. (c) is the durability result of the double-layer hafnium zirconium oxide ferroelectric layer FeFET using a write pulse with a larger amplitude and a smaller width. Its durability is optimized to more than 10 9 The optimized write pulse with larger amplitude and smaller width can effectively suppress the accumulation of interface trap charge during the cycle and improve the durability.

[0084] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A gate stack structure FeFET, characterized in that: The invention comprises a silicon substrate, a source, a drain, a gate stack, a gate metal electrode, a passivation layer and a contact metal electrode; the surface area of ​​the silicon substrate is divided into a non-active area, a source and drain area, a gate area, a source and drain area and a non-active area in sequence, the non-active area is a silicon dioxide layer, the source and drain materials of the source and drain area are located in the silicon substrate and are flush with the surface of the silicon substrate, the gate area is a gate stack structure and a gate metal electrode thereon, the gate stack structure is a patterned aluminum oxide channel interface layer and a double-layer hafnium zirconium oxide (HZO+HZO) ferroelectric layer from bottom to top, the double-layer hafnium zirconium oxide ferroelectric layer is composed of two layers of thickness The FeFET structure is composed of a hafnium zirconium oxide ferroelectric layer with consistent thickness and an aluminum oxide intermediate interface layer located between the two hafnium zirconium oxide ferroelectric layers, a passivation layer covers the gate metal electrode, the source and drain regions, and the silicon dioxide layer in the non-active region for electrical isolation and contamination prevention, and the contact metal electrode is connected to the source, drain and gate metal electrodes through the through holes in the passivation layer; a write pulse with a larger amplitude and a shorter width is applied to the gate region of the FeFET structure to synergistically optimize the consistency and durability of the FeFET device, and the amplitude of the write pulse is greater than the flipping voltage of most ferroelectric domains in the ferroelectric layer.

2. The gate stack structure FeFET according to claim 1, characterized in that: In the FeFET, the thickness of the aluminum oxide channel interface layer is 1 to 3 nm.

3. The gate stack structure FeFET according to claim 1, characterized in that: In the FeFET, the thickness of each hafnium zirconium oxide layer in the double-layer hafnium zirconium oxide ferroelectric layer is 6-10 nm, and the atomic ratio of hafnium atoms to zirconium atoms is 1:

1.

4. The gate stack structure FeFET according to claim 1, characterized in that: In the FeFET, the thickness of the aluminum oxide middle interface layer in the double-layer hafnium zirconium oxide ferroelectric layer is 1 to 2 nm.

5. The gate stack structure FeFET according to claim 1, characterized in that: In the FeFET, the gate metal electrode material should have a small resistivity, certain thermal stability and mechanical strength, and also need to form a certain stress on the ferroelectric layer to induce stable ferroelectricity; TiN, TaN or W materials are selected.

6. A method for preparing a gate stack structure FeFET, characterized in that: The following steps are involved: (1) A thick silicon dioxide layer is grown on the entire silicon substrate by wet oxidation or chemical vapor deposition, and then the active area is defined by photolithography. The silicon oxide layer in the active area is removed by dry etching and wet etching to expose the underlying silicon substrate; (2) using a diluted hydrofluoric acid solution to remove the natural oxide layer on the surface of the active silicon substrate; (3) Depositing an aluminum oxide channel interface layer on the entire wafer using an atomic layer deposition method; (4) using the atomic layer deposition method to grow a double layer of hafnium zirconium oxide ferroelectric layer on the whole wafer, first depositing a layer of hafnium zirconium oxide HZO ferroelectric layer, then a thin layer of aluminum oxide intermediate interface, and finally depositing another layer of hafnium zirconium oxide HZO ferroelectric layer; (5) Physical vapor deposition method to grow gate metal electrode materials on the entire wafer; (6) defining the gate region by photolithography, using photoresist as a barrier layer, and removing the gate metal electrode material and gate stack structure material in the non-gate region by dry etching; (7) Performing self-aligned ion implantation on the entire wafer to form source and drain regions, with the area between the source and drain being the channel region; (8) performing a rapid thermal annealing process on the entire wafer to simultaneously activate the ferroelectricity of the ferroelectric layer and the ions injected into the source and drain regions; (9) growing a silicon dioxide passivation layer on the entire wafer by chemical vapor deposition; (10) in the silicon dioxide passivation layer, defining the contact hole regions of the gate metal electrode, source, and drain regions by photolithography, removing the passivation layer in the contact hole region by dry etching and wet etching to form a through hole, and then removing the photoresist; (11) growing a contact metal electrode on the entire wafer by physical vapor deposition, wherein the contact metal fills the through hole and covers the surface above the passivation layer; (12) defining the pattern of the contact metal electrode by photolithography, using the photoresist as a barrier layer, removing the contact metal in the remaining area by dry etching, overetching to the passivation layer, and then removing the photoresist; (13) Finally, the alloy is annealed to form an ohmic contact between the contact metal and the source and drain.

7. The method for preparing a gate stack structure FeFET according to claim 6, characterized in that: In the steps (3) and (4), the double-layer hafnium zirconium oxide ferroelectric layer and the aluminum oxide channel interface layer are grown in the same step of atomic layer deposition. The atomic ratio in the materials is controlled by controlling the ratio of the number of cycles of different materials. The ratio of hafnium atoms to zirconium atoms in the finally formed hafnium zirconium oxide ferroelectric layer is 1:1, so as to ensure good ferroelectricity.

8. The method for preparing a gate stack structure FeFET according to claim 6, characterized in that: In the steps (3) and (4), an aluminum oxide boundary channel surface layer and a double-layer hafnium zirconium oxide ferroelectric layer are grown by atomic layer deposition, and trimethylaluminum (TMA), tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water are used as precursors of aluminum, hafnium, zirconium and oxygen, respectively.

9. The method for preparing a gate stack structure FeFET according to claim 6, characterized in that: The step (5) deposits gate metal electrode material on the entire wafer by evaporation, sputtering or other physical vapor deposition methods.

10. The method for preparing a gate stack structure FeFET according to claim 6, characterized in that: The annealing temperature of step (8) is 500-900° C., and the annealing time is 10-120 seconds; the alloy annealing temperature of step (13) is 400-450° C., and the time is 30 minutes.

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