Display panel and display device
By providing no overlap between the first gate and the second gate in the thin film transistor and the active layer in the first region, the problem of excessive electric field intensity in the active layer edge is solved, and the working stability and functional accuracy of the transistor are improved.
Patent Information
- Application Number
- CN202411645983.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-03-21
AI Technical Summary
In thin film transistors, due to the poor smoothness of the edge structure of the active layer, the electric field intensity in the edge area is relatively large, which is easy to turn on in advance, affecting the working stability and functional accuracy of the transistor.
By providing at least one of the first gate and the second gate of the thin film transistor has no overlap with the active layer in the first region, the first region is affected by the electric field, thereby reducing the risk of early opening of the edge of the active layer.
It effectively reduces the risk of electric field strength at the edge of the active layer, improves the working stability and switching characteristics of thin film transistors, avoids the camel effect, and ensures the functional accuracy of the transistor.
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Figure CN119677168A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] In the application of thin film transistors, in order to improve the efficiency of thin film transistors in generating current, a top-bottom double gate structure is usually adopted for thin film transistors. However, when voltage is applied to the top and bottom double gates of the transistor at the same time, due to the preparation process of the active layer of the transistor, the structural smoothness of the edge area of the active layer is poor, which makes the electric field strength at the edge of the active layer larger, so that the edge of the active layer attracts more electrons, which will cause the edge area of the transistor device to open first, making the active layer of the transistor unable to conduct evenly. In addition, after performing voltage-temperature performance tests, it was found that the switching characteristic curve of the transistor showed a hump effect, that is, the transistor was turned on prematurely. The above problems easily lead to the inability to accurately perform the functions of the transistor and the poor stability during the application of the transistor. Summary of the invention
[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.
[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a substrate;
[0005] A thin film transistor, wherein the thin film transistor is located on one side of the substrate; the thin film transistor comprises an active layer, a first gate, and a second gate, wherein the active layer is located between the film layer where the first gate is located and the film layer where the second gate is located;
[0006] The active layer of the thin film transistor includes a first region, which is adjacent to an edge of the active layer; in a direction perpendicular to the plane where the substrate is located, at least one of the first gate and the second gate of the thin film transistor has no overlap with the active layer at least partially located in the first region.
[0007] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.
[0008] In an embodiment of the present application, in a direction perpendicular to the plane of the substrate, at least one of the first gate and the second gate of the thin film transistor has no overlap with the active layer at least partially located in the first region. At this time, the first region of the thin film transistor overlaps with the first gate or the second gate in a direction perpendicular to the substrate, which is beneficial to reducing the influence of the first region by the partial electric field provided by the first gate and the second gate at the same time, thereby helping to reduce the risk of the edge of the active layer being affected by a large field strength, and helping to reduce the risk of the active layer in the first region being turned on prematurely, thereby improving the operating stability of the thin film transistor in the display panel, and further ensuring the operating stability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0010] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;
[0011] Figure 2 A schematic plan view of a thin film transistor provided for an embodiment of the application;
[0012] Figure 3 A schematic plan view of another thin film transistor provided in an embodiment of the present application;
[0013] Figure 4 A schematic plan view of a thin film transistor in a related technology provided in an embodiment of the present application;
[0014] Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic diagram of the cross section along the A-A' direction;
[0015] Figure 6 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0016] Figure 7 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0017] Figure 8 A schematic plan view of another thin film transistor provided in an embodiment of the present application;
[0018] Fig. 9 A schematic plan view of another thin film transistor provided in an embodiment of the present application;
[0019] Fig.10 A schematic plan view of another thin film transistor provided in an embodiment of the present application;
[0020] Fig.11 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0021] Fig.12 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0022] Fig.13 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0023] Fig.14 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0024] Fig.15 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0025] Fig.16 A schematic plan view of another thin film transistor improved according to the embodiment of the present application;
[0026] Fig.17 A schematic plan view of another thin film transistor according to an embodiment of the present application
[0027] Fig.18 A schematic plan view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0029] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.
[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0032] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.
[0033] It should be understood that although the terms first, second, etc. may be used to describe gates, regions, gaps, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish gates, regions, gaps, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first gate may also be referred to as the second gate, and similarly, the second gate may also be referred to as the first gate. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.
[0034] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 2 A schematic plan view of a thin film transistor provided in an embodiment of the application, Figure 3 A schematic plan view of another thin film transistor provided in an embodiment of the present application, Figure 4 A schematic plan view of a thin film transistor in a related technology provided in an embodiment of the present application, Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic diagram of the cross section along the A-A' direction.
[0035] The present application embodiment provides a display panel A10, such as Figure 1 As shown, the display panel A10 includes a substrate 10 and a thin film transistor 20. Figure 2 , Figure 3 As shown, the thin film transistor 20 is located on one side of the substrate 10 , and includes an active layer 201 , a first gate 202 , and a second gate 203 . The active layer 201 is located between the film layer where the first gate 202 is located and the film layer where the second gate 203 is located.
[0036] Combination Figure 4 , Figure 5As shown, in the related art, setting the thin film transistor 20 as a dual-gate structure is conducive to improving the efficiency of the thin film transistor 20 in generating current. However, when two gates are used to simultaneously receive voltage to drive the thin film transistor 20, due to the preparation process of the thin film transistor 20, the active layer 201 of the thin film transistor 20 has edges and corners along the edge of the source S to the drain D of the transistor, so that the above-mentioned edge position, that is, the active layer 201 in the first region 201A has a strong ability to gather electrons, so that when the edge of the active layer 201 is acted on by the first gate 202 and the second gate 203 at the same time, the electric field strength received by the edge position of the active layer 201 is also large, which causes the risk of premature opening at the edge position of the active layer 201. This will cause the working stability of the transistor to be poor, which is not conducive to its accurate completion of the switching work. Therefore, when the thin film transistor 20 is set to be driven by two gates at the same time, improving the opening uniformity of the active layer 201 of the thin film transistor 20 is conducive to improving the working stability of the thin film transistor 20.
[0037] The active layer 201 of the thin film transistor 20 includes a first region 201A. The first region 201A is adjacent to the edge of the active layer 201. It should be noted that the edge of the active layer 201 mentioned here specifically refers to the edge in the direction from the source electrode to the drain electrode of the thin film transistor 20, which is consistent with the edge described in the above-mentioned related technical content. Then, the first region 201A is located near the edge of the active layer 201, and when the thin film transistor 20 is driven by the first gate 202 and the second gate 203 at the same time, the active layer 201 located in the first region 201A is simultaneously subjected to the electric field provided by the first gate 202 and the second gate 203, so that the edge portion of the active layer 201 in the first region 201A is subjected to a larger electric field strength due to structural reasons, and then the active layer 201 portion of the first region 201A may be at risk of being turned on prematurely.
[0038] In the embodiments of the present application, Figure 2 , Figure 3 As shown, in the direction perpendicular to the plane where the substrate 10 is located, there is no overlap between the first gate 202 and the second gate 202 of the thin film transistor 20 and the active layer 201 at least partially located in the first region 201A. At this time, the first region 201A of the thin film transistor 20 overlaps with the first gate 202 or the second gate 203 in the direction perpendicular to the substrate 10, which is beneficial to reduce the influence of the partial electric field provided by the first gate 202 and the second gate 203 on the first region 201A at the same time, thereby helping to reduce the risk of the edge of the active layer 201 being affected by a large field strength, and helping to reduce the risk of the active layer 201 in the first region 201A being turned on prematurely, thereby improving the working stability of the thin film transistor 20 in the display panel A10, and further ensuring the working stability of the display panel A10.
[0039] In one embodiment of the present application, continue to refer to Figure 2 , Figure 3 As shown, the second gate 203 is located on the side of the active layer 201 facing the substrate 10. Optionally, the second gate 203 is a bottom gate of the thin film transistor 20. Optionally, the second gate 203 is a non-transparent metal structure, and can also be a light shielding structure to prevent light from the substrate 10 from entering the thin film transistor 20.
[0040] In the embodiments of the present application, Figure 2 As shown, the second gate 203 is arranged along a direction perpendicular to the plane where the display panel A10 is located, and there is no overlap between the second gate 203 and the active layer 201 located at least partially in the first region 201A. Optionally, the first gate 202 and the second gate 203 receive the same voltage at the same time. When there is no overlap between the second gate 203 and at least part of the first region 201A, the overlapping area between the first region 201A and the second gate 203 is reduced. At this time, there is a part of the first gate 201A that only overlaps with the first gate 202, and the electric field strength of the first region 201A is mostly from the electric field provided by the first gate 202, which reduces the concentration of electrons in the first region 201A, thereby reducing the risk of premature opening of the first region 201A, reducing the difference in opening speed between the first region 201A and other regions of the active layer 201, and improving the working stability and accuracy of the thin film transistor 20.
[0041] Figure 6 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0042] In one embodiment of the present application, Figure 6As shown, along the direction perpendicular to the plane where the display panel A10 is located, there is no overlap between the second gate 203 and the active layer 201 located in the first region 201A, and the first gate 202 overlaps with the active layer 201 located in the first region 201A. Optionally, when there is no overlap between the second gate 203 and the active layer 201 located in the first region 201A provided in the embodiment of the present application, the second gate 203 is not provided at the position overlapping with the first region 201A in the film layer where the second gate 203 is located. At this time, when the first gate 202 and the second gate 203 receive voltage at the same time, the electric field influence on the first region 201A is almost entirely from the first gate 202, which greatly reduces the electric field strength at the edge of the active layer 201, thereby reducing the ability of electrons to move toward the edge, thereby reducing the risk of premature opening of the first region 201A. It should be noted that, although the area other than the first area 201A in the active layer 201 is still driven by the first gate 202 and the second gate 203, the shape of this part of the area is relatively flat, and the electric field strength it receives is relatively uniform, so the opening degree of the area other than the first area 201A in the active layer 201 is relatively uniform. Although the edge of the active layer 201 is only driven by the first gate 202, due to its poor shape regularity, the electric field strength it receives is also greater than when other areas are only driven by the first gate 202. Therefore, when the number of gates overlapped by the first area 201A of the active layer 201 and other areas is different, the difference between the electric field strength of the first area 201A of the active layer 201 and other areas is also small, so that the opening speed of the entire surface of the active layer 201 is relatively uniform.
[0043] Figure 7 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0044] In one embodiment of the present application, Figure 7 As shown, along the direction perpendicular to the plane where the display panel A10 is located, the second gate 203 has no overlap with a portion of the active layer 201 located in the first region 201A, and the first gate 202 overlaps with the active layer 201 located in the first region 201A.
[0045] In the embodiment of the present application, the overlap between the first region 201A and the second gate 203 is reduced, and the first gate 202 and the first region 201A are all overlapped, while part of the first region 201A overlaps with the second gate 203, and part of the first region 201A does not overlap with the second gate 203. This is beneficial for adaptively adjusting the field intensity provided by the second gate 203 to the first region 201A on the basis of achieving the reduction of the field intensity provided by the second gate 203 to the first region 201A, thereby adjusting the range of the electric field intensity at the edge of the active layer 201. Optionally, according to the turn-on field intensity that the thin film transistor 20 can adapt to, the overlap area between the second gate 203 and the first region 201A is adjusted, so as to adjust the electric field intensity at the first region 201A to be similar to the electric field intensity in other regions, thereby improving the uniformity of the conduction and opening of the active layer 201.
[0046] Figure 8 A schematic plan view of another thin film transistor provided in an embodiment of the present application.
[0047] In one embodiment of the present application, Figure 8 As shown, setting the second gate 203 to a sawtooth structure is conducive to reducing the area of the second gate 203, and setting the second gate 203 to a more regular structure provides a feasible solution for the implementation of the present application. When the second gate 203 is a sawtooth structure, there is a position between the second gate 203 and the first area 201A that exposes the first area 201A, thereby reducing the risk of the first area 201A being subjected to a larger electric field strength. In addition, the sawtooth width and other dimensions of the second gate 203 can be adaptively adjusted, so as to more accurately and standardizedly adjust the electric field strength that the second gate 203 can provide to the first area 201A, thereby improving the standardization and feasibility of the implementation of this solution.
[0048] Fig. 9 A schematic plan view of another thin film transistor provided in an embodiment of the present application.
[0049] In one embodiment of the present application, Fig. 9 As shown, the active layer 201 in the first region 201A is arranged to have a sawtooth structure.
[0050] In the embodiment of the present application, the active layer 201 in the first region 201A is also set to a sawtooth structure, which is conducive to extending the edge length of the active layer 201, so that when the first region 201A starts to transmit current in advance, this setting is conducive to reducing the speed of current transmission, thereby delaying the opening speed of the active layer 201 in the first region 201A. In addition, when the second gate 203 and the active layer 201 located in the first region 201A are both sawtooth structures, the overlapping area between the active layer 201 in the first region 201A and the second gate 203 is further reduced. It is also conducive to providing a feasible solution for adaptively adjusting the overlapping area between the active layer 201 in the first region 201A and the second gate 203, which is conducive to further reducing the difference between the electric field strength received by the active layer 201 in the first region 201A and the electric field strength received by other regions in the active layer 201, and more accurately improving the working performance of the thin film transistor 20.
[0051] Fig.10 A schematic plan view of another thin film transistor provided in an embodiment of the present application.
[0052] In one embodiment of the present application, Figure 8-Figure 10 As shown, the plurality of saw teeth of the second gate 203 are sequentially arranged along the first direction X1 , and a first gap W1 is included between two adjacent saw teeth in the first direction X1 .
[0053] At least part of the plurality of sawteeth of the active layer 201 in the first region 201A corresponds to the first gap W1 in the direction toward the second gate 203. At this time, part of the sawteeth of the active layer 201 in the first region 201A only overlaps with the first gate 202.
[0054] In the embodiment of the present application, a plurality of sawteeth of the active layer 201 in the first region 201A are arranged to correspond to the first gap W1, which is beneficial to improving the structural regularity of the thin film transistor 20 on the basis of reducing the overlapping area between the second gate 203 and the active layer 201 in the first region 201A, thereby further ensuring the working performance of the thin film transistor 20.
[0055] In one embodiment of the present application, continue to refer to Figure 3 As shown, along a direction perpendicular to the plane where the display panel A10 is located, there is no overlap between the first gate 202 and the active layer 201 at least partially located in the first region 201A.
[0056] In the embodiment of the present application, the first gate 202 is arranged to have no overlap with the active layer 201 at least partially located in the first region 201A, which is beneficial to reducing the overlapping area between the first gate 202 and the first region 201A, so that the electric field strength received by the first region 201A is smaller, which is beneficial to reducing the risk of the first region 201A being turned on before other regions, thereby improving the working stability of the thin film transistor 20.
[0057] Fig.11 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0058] In one embodiment of the present application, Fig.11 As shown, along the direction perpendicular to the plane where the display panel A10 is located, there is no overlap between the first gate 202 and the active layer 202 located in the first region 201A, and the second gate 203 overlaps with the active layer 201 located in the first region 201A. Optionally, the first gate 202 is not provided in the portion of the film layer where the first gate 202 is located that overlaps with the first region 201A, so that there is no overlap between the first gate 202 and the active layer 202 located in the first region 201A. This is conducive to ensuring that the driving field strength received by the first region 201A comes only from the second gate 203 to a certain extent, reducing the electric field strength at the edge of the active layer 201, thereby reducing the risk of the first region 201A turning on the output current first. In addition, the above embodiment mentions that the second gate 203 is located on the side of the active layer 201 facing the substrate 10, which can be reused as a light shielding structure. Then, at this time, the second gate 203 is set to overlap with the active layer 201 located in the first region 201A, and the first gate 202 is responsible for reducing the field strength of the first region 201A, which is beneficial to ensure the structural integrity of the second gate 203, so that its shading effect can be better realized, and the performance stability of the thin film transistor 20 is further improved.
[0059] Fig.12 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0060] In one embodiment of the present application, Fig.12 As shown, along the direction perpendicular to the plane where the display panel A10 is located, the first gate 202 has no overlap with a portion of the active layer 201 located in the first region 201A, and the second gate 203 overlaps with the active layer 201 located in the first region 201A.
[0061] In the embodiment of the present application, the overlap between the first region 201A and the first gate 202 is reduced, and the second gate 203 and the first region 201A are all overlapped, while part of the first region 201A overlaps with the first gate 202, and part of the first region 201A does not overlap with the first gate 202. This is beneficial for adaptively adjusting the field intensity provided by the first gate 202 to the first region 201A on the basis of achieving the reduction of the field intensity provided by the first gate 202 to the first region 201A, thereby adjusting the range of the electric field intensity at the edge of the active layer 201. Optionally, according to the turn-on field intensity that the thin film transistor 20 can adapt to, the overlap area between the first gate 203 and the first region 201A is adjusted, so as to adjust the electric field intensity at the first region 201A to be similar to the electric field intensity in other regions, thereby improving the uniformity of the conduction and opening of the active layer 201.
[0062] Fig.13 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0063] In one embodiment of the present application, Fig.13 As shown, the first grid 202 is set to a sawtooth structure, and similar to setting the second grid 203 to a sawtooth structure, the first grid 202 can also be set to a sawtooth structure, which is conducive to reducing the area of the first grid 202, and setting the first grid 202 to a structure with a regular shape is conducive to improving the convenience of preparing the first grid 202, and is also conducive to improving the adaptability and adjustability of the overlapping area between the first grid 202 and the first region 201A. When the first grid 202 is a sawtooth structure, there is a position between the first grid 202 and the first region 201A that exposes the first region 201A, thereby reducing the risk of the first region 201A being subjected to a large electric field strength. In addition, the sawtooth width and other dimensions of the first grid 202 can be adaptively adjusted, so as to more accurately and normatively adjust the electric field strength that the first grid 202 can provide to the first region 201A, thereby improving the standardization and feasibility of the implementation of this solution.
[0064] Fig.14 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0065] In one embodiment of the present application, Fig.14As shown, the active layer 201 in the first region 201A is also provided with a sawtooth structure. At this time, the area of the active layer 201 in the first region 201A decreases, which is conducive to reducing the overlapping area between the active layer 201 in the first region 201A and the first gate 202 and the second gate 203. And the first gate 202 is also a sawtooth structure, and the overlapping part between the active layer 201 and the first gate 202 is further reduced, which is conducive to more significantly reducing the electric field strength of the edge of the active layer 201, and further reducing the risk of premature opening of the active layer 201 in the first region 201A.
[0066] Fig.15 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0067] In one embodiment of the present application, Figure 13-Figure 15 As shown, the plurality of saw teeth of the first gate 202 are sequentially arranged along the first direction X1, and a second gap W2 is included between two adjacent saw teeth in the first direction X1.
[0068] Among them, Fig.15 As shown, at least part of the plurality of sawteeth of the active layer 201 in the first region 201A corresponds to the second gap W2 in the direction toward the first gate 202. At this time, part of the sawteeth of the active layer 201 in the first region 201A only overlaps with the second gate 203.
[0069] In the embodiment of the present application, on the one hand, the active layer 201 in the first region 201A is set to a sawtooth structure, which is conducive to extending the edge length of the active layer 201, so that when the first region 201A starts to transmit current in advance, this setting is conducive to reducing the speed of current transmission, thereby delaying the opening speed of the first region 201A. In addition, the multiple sawteeth of the active layer 201 in the first region 201A are set to correspond to the second gap W2, which is conducive to further reducing the overlapping area between the first region 201A and the first gate 202, thereby reducing the electric field strength of the active layer 201 in the first region 201A, thereby reducing the opening speed of the active layer 201 in the first region 201A.
[0070] Fig.16 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0071] In one embodiment of the present application, Fig.16As shown, the first gate 202 and the second gate 203 are both sawtooth structures, and the sawteeth of the first gate 202 and the second gate 203 are arranged along the first direction X1, and the sawteeth of two adjacent first gates 202 in the first direction X1 include a first gap W1, and the sawteeth of two adjacent second gates 203 in the first direction X1 include a second gap W2;
[0072] In the embodiment of the present application, the first gap W1 and the second gap W2 are arranged so as not to overlap, and the first gap W1 and the second gap W2 are arranged alternately in the first direction X1. This is conducive to making a part of the active layer 201 in the first region 201A overlap only with the first gate 202 and a part of the active layer 201 overlap only with the second gate 203, so that different positions of the active layer 201 in the first region 201A are only affected by the electric field of one of the gates to a certain extent, which is conducive to reducing the electric field strength of the active layer 201 in the first region 201A, and also making the field strength of the edge of the active layer 201 have a certain uniformity, so that the electron density absorbed by the active layer 201 at different positions in the first region 201A is more uniform, which is conducive to further improving the working performance of the thin film transistor 20.
[0073] In one embodiment of the present application, continue to refer to Fig.16 As shown, the first region 201A includes first sub-regions 201A1 and second sub-regions 201A2 that are alternately arranged in the first direction X1.
[0074] In the embodiment of the present application, the active layer 202 located in the first sub-region 201A1 overlaps with the first gap W1 and overlaps with the sawtooth of the first gate 202, and the active layer 202 located in the second sub-region 201A2 overlaps with the second gap W2 and overlaps with the sawtooth of the second gate 203, which is beneficial to ensure that the active layer 201 in the first region 201A has a gate that overlaps with it, thereby ensuring the ability of the active layer 201 to transmit current.
[0075] Fig.17 A schematic plan view of another thin film transistor improved according to the embodiment of the present application.
[0076] In one embodiment of the present application, Fig.17 As shown, the thin film transistor 20 further includes a source S and a drain D respectively located on opposite sides of the first gate 202 in the first direction X1. The active layer 201 further includes a second region 201B, which is located on a side of the first region 201A away from the edge of the active layer 201. The structure of the active layer 201 in the second region 201B is relatively flat, and the electric field strength received by this part is uniform, and the corresponding turn-on speed uniformity of the active layer 201 in the second region 201B is also relatively high.
[0077] The edge of the active layer 201 adjacent to the first region 201A in the direction from source S to drain D extends by a length L1, and the portion of the active layer 201 in the second region 201B extends by a length L2, L1>L2.
[0078] In the embodiment of the present application, the extension length L1 of the edge of the active layer 201 adjacent to the first region 201A in the direction from the source S to the drain D is set to be greater than the extension length L2 of the active layer 201 in the second region 201B in the direction from the source S to the drain D, which is beneficial to increase the transmission distance of the current in the first region 201A, thereby reducing the speed at which the active layer 201 in the first region 201A transmits the current after being turned on, thereby achieving the purpose of shortening the difference in the turning-on speed of the active layer 202 in the first region 201A and the active layer 202 in the second region 201B.
[0079] Optionally, the active layer 202 in the first region 201A may have a sawtooth structure or a wavy structure.
[0080] Fig.18 A schematic plan view of a display device provided in an embodiment of the present application.
[0081] The present application embodiment provides a display device A20, such as Fig.18 As shown, the display device includes the display panel A10 provided in the above embodiment. The display device A20 can be a computer, a television, a mobile phone or other device used for display.
[0082] In the display device A20, in a direction perpendicular to the plane where the substrate 10 is located, at least one of the first gate 202 and the second gate 202 of the thin film transistor 20 has no overlap with the active layer 201 at least partially located in the first region 201A. At this time, the first region 201A of the thin film transistor 20 overlaps with the first gate 202 or the second gate 203 in a direction perpendicular to the substrate 10, which is beneficial to reduce the influence of the first region 201A by the partial electric field provided by the first gate 202 and the second gate 203 at the same time, thereby helping to reduce the risk of the edge of the active layer 201 being affected by a large field strength, and helping to reduce the risk of the first region 201A being turned on prematurely, thereby improving the working stability of the thin film transistor 20 in the display panel A10, and further ensuring the working stability of the display panel A10.
[0083] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. A display panel, characterized in that: include: substrate; A thin film transistor, wherein the thin film transistor is located on one side of the substrate; the thin film transistor comprises an active layer, a first gate, and a second gate, wherein the active layer is located between the film layer where the first gate is located and the film layer where the second gate is located; The active layer of the thin film transistor includes a first region, which is adjacent to an edge of the active layer; in a direction perpendicular to the plane where the substrate is located, at least one of the first gate and the second gate of the thin film transistor has no overlap with the active layer at least partially located in the first region.
2. The display panel according to claim 1, characterized in that: The second gate is located on a side of the active layer facing the substrate; along a direction perpendicular to the plane where the display panel is located, there is no overlap between the second gate and at least a portion of the active layer located in the first region.
3. The display panel according to claim 2, characterized in that: Along a direction perpendicular to the plane where the display panel is located, the second gate has no overlap with the active layer located in the first region, and the first gate overlaps with the active layer located in the first region.
4. The display panel according to claim 2, characterized in that: Along a direction perpendicular to the plane where the display panel is located, the second gate has no overlap with a portion of the active layer located in the first region, and the first gate overlaps with the active layer located in the first region.
5. The display panel according to claim 4, characterized in that: The second gate has a sawtooth structure.
6. The display panel according to claim 5, characterized in that: The active layer located in the first region has a sawtooth structure.
7. The display panel according to claim 6, characterized in that: The plurality of saw teeth of the second grid are sequentially arranged along a first direction, and a first gap is included between two adjacent saw teeth in the first direction; At least part of the plurality of sawteeth of the active layer located in the first region corresponds to the first gap in a direction toward the second gate.
8. The display panel according to claim 1, characterized in that: Along a direction perpendicular to the plane where the display panel is located, there is no overlap between the first gate and at least a portion of the active layer located in the first region.
9. The display panel according to claim 8, characterized in that: Along a direction perpendicular to the plane where the display panel is located, the first gate has no overlap with the active layer located in the first region, and the second gate overlaps with the active layer located in the first region.
10. The display panel according to claim 8, characterized in that: Along a direction perpendicular to the plane where the display panel is located, the first gate has no overlap with a portion of the active layer located in the first region, and the second gate overlaps with the active layer located in the first region.
11. The display panel according to claim 10, characterized in that: The first gate has a sawtooth structure.
12. The display panel according to claim 11, characterized in that: The active layer located in the first region has a sawtooth structure.
13. The display panel according to claim 12, characterized in that: The plurality of saw teeth of the first grid are sequentially arranged along a first direction, and a second gap is provided between two adjacent saw teeth in the first direction; At least part of the plurality of sawteeth of the active layer located in the first region corresponds to the second gap in a direction toward the first gate.
14. The display panel according to claim 1, characterized in that: The first grid and the second grid are both sawtooth structures, and the sawteeth of the first grid and the second grid are arranged along a first direction, and a first gap is included between the sawteeth of two adjacent first grids in the first direction, and a second gap is included between the sawteeth of two adjacent second grids in the first direction; The first gap and the second gap do not overlap, and the first gap and the second gap are alternately arranged in the first direction.
15. The display panel according to claim 14, characterized in that: The first region includes first sub-regions and second sub-regions alternately arranged in the first direction; The active layer in the first sub-region overlaps with the first gap and the sawtooth of the first gate, and the active layer in the second sub-region overlaps with the second gap and the sawtooth of the second gate.
16. The display panel according to claim 1, characterized in that: The thin film transistor further includes a source electrode and a drain electrode respectively located on opposite sides of the first gate electrode in a first direction; the active layer further includes a second region, and the second region is located on a side of the first region away from an edge of the active layer; The edge of the active layer adjacent to the first region extends for a length L1 in the direction from the source to the drain; the portion of the active layer located in the second region extends for a length L2 from the source to the drain; L1>L2.
17. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-16.