SIC MOSFET device and preparation method thereof

Abstract

The invention discloses an SIC MOSFET device and a preparation method thereof. The device comprises an N-type epitaxial silicon carbide layer, a high-K material suspension layer, a gate trench, a P body region, an N-type active region, a connecting hole, a high-K material dielectric layer, a top silicon dioxide layer and a metal layer. The high-K material suspension layer is arranged in the N-type epitaxial silicon carbide layer; the P body region and the N-type active region are arranged in the top region of the N-type epitaxial silicon carbide layer; a gate trench and a connecting hole are formed in the N-type epitaxial silicon carbide layer and extend to the lower part of the P body region; the gate trench is arranged right above the high-K material suspension layer; the gate trench is internally provided with a gate oxide layer and is filled with a polycrystalline silicon gate; the connecting hole is filled with a high-K material dielectric layer; the top silicon dioxide layer is arranged on the surfaces of the N-type active region and the gate trench; and the metal layer is filled in the connecting hole and covers the top silicon dioxide layer. The gate oxide in the trench can be protected from being influenced by a high electric field, the withstand voltage of the device is improved, the Miller capacitance and the output capacitance are reduced, and the switching loss of the device is reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a SIC MOSFET device and a preparation method thereof. Background Art

[0002] SiC is widely used due to its excellent properties such as wide bandgap, high breakdown voltage, high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity. SiC MOSFET devices are mainly divided into planar and trench types. Trench power SiC MOSFET devices have lower on-resistance and greater current density due to the lack of JFET effect. They have the advantages of high integration, low on-resistance, small reverse capacitance, fast switching speed, and low switching loss. However, trench power SiC MOSFET devices have the problem of large electric field at the bottom of the trench and easy breakdown or injection of interface states, which limits their long-term application reliability. For high reliability and high voltage application scenarios, the current mainstream products still use planar SiC MOSFET devices.

[0003] The current planar SiC MOSFET has a low channel density, and due to the existence of JFET resistance, there is a problem of too high on-resistance. Since SiC trench MOSFET has no JFET effect, it has a lower on-resistance and a higher current density, which can effectively increase the channel density. However, due to the large electric field at the bottom of the trench structure, it is easy to be broken down or injected into the interface state, which limits its long-term application reliability. In addition, the current trench SiC MOSFET uses trench bottom injection or Dummy trench injection to protect the gate oxide from reverse high electric field depletion, thereby protecting the gate oxide. However, the ion diffusion in SIC materials is difficult, and the ion activation rate is also very low. The method of protecting the gate oxide by ion injection has extremely high process requirements, and due to the existence of Dummy trenches, the channel utilization rate will also be reduced, thereby increasing the on-resistance of the device. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a SIC MOSFET device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions: In a first aspect, an embodiment of the present invention provides a SIC MOSFET device, comprising: N-type epitaxial silicon carbide layer, high-K material suspension layer, gate trench, P body region, N-type active region, connection hole, high-K material dielectric layer, top silicon dioxide layer and metal layer for source electrode interconnection; wherein, The high-K material suspension layer is arranged inside the N-type epitaxial silicon carbide layer; the P body region and the N-type active region are stacked and arranged in the top layer region of the N-type epitaxial silicon carbide layer, and the N-type active region layer is located above the P body region; the gate trench and the connection hole are arranged in the N-type epitaxial silicon carbide layer and extend to a position below the P body region; the gate trench is located directly above the high-K material suspension layer; the inner wall of the gate trench is provided with a gate oxide layer and the groove is filled with a polysilicon gate; the high-K material dielectric layer is arranged in the bottom region of the connection hole; the top silicon dioxide layer is arranged on the surface of the N-type active region and the gate trench; the metal layer is filled in the connection hole and covers the upper region of the top silicon dioxide layer.

[0005] In a second aspect, an embodiment of the present invention provides a method for preparing a SIC MOSFET device, the method comprising: Selecting N-type epitaxial silicon carbide wafer; Depositing a layer of high-K material on the N-type epitaxial silicon carbide wafer, and removing the high-K material in a partial area by photolithography and dry etching processes to form a high-K material suspension layer; Growing N-type epitaxial silicon carbide material again on the surface of the current device and covering the high-K material suspension layer, the grown N-type epitaxial silicon carbide material and the previous N-type epitaxial silicon carbide sheet together constitute an N-type epitaxial silicon carbide layer; A gate trench is defined in the N-type epitaxial silicon carbide layer above the high-K material suspension layer by using photolithography and dry etching processes, and a gate oxide layer is deposited on the inner wall of the gate trench, and a polysilicon gate is formed by filling the trench; Forming a P-body region and an N-type active region in the top region of the N-type epitaxial silicon carbide layer by an ion implantation process; wherein the P-body region and the N-type active region are arranged from bottom to top, and the lower surface position of the P-body region is higher than the lower surface position of the gate trench; Defining a connection hole in the N-type epitaxial silicon carbide layer by using photolithography and dry etching processes, so that the connection hole extends to a position below the P body region, and retaining the top silicon dioxide layer during the dry etching process; Depositing a layer of high-K material in the bottom area of ​​the connection hole to form a high-K material dielectric layer; A metal layer is deposited in the connection hole and on the surface of the top silicon dioxide layer to form source electrode interconnection, thereby obtaining a SIC MOSFET device.

[0006] Beneficial effects of the present invention: In the solution provided by the embodiment of the present invention, a high-K material suspension layer is formed by introducing a high-K material into the N-type epitaxial silicon carbide layer, and the high-K material is evenly distributed in the bottom region of the gate trench to form a suspended high-K dielectric layer, which can protect the gate oxide layer at the bottom of the gate trench from the influence of the reverse high electric field during withstand voltage. At the same time, a high-K material dielectric layer is also introduced at the bottom of the connection hole to protect the gate oxide layer at the corner of the gate trench from the influence of the reverse high electric field; by introducing high-K materials in these two ways, the gate oxide can be protected from the influence of the high electric field, which can effectively protect the gate oxide, improve the life of the gate oxide, improve the reliability of the device, and increase the withstand voltage of the device, and there is no need to use dummy grooves to sacrifice the current capacity of the device; because the introduction of high-K materials also reduces the Crss (Miller capacitance) and Coss (output capacitance) of the SIC MOSFET, the switching speed of the device is accelerated, and the switching loss of the device is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of the structure of a SIC MOSFET device provided by an embodiment of the present invention; Figure 2 A schematic diagram of a process for preparing a SIC MOSFET device provided by an embodiment of the present invention; Figure 3(a) to Figure 3(i) A schematic diagram of the process of manufacturing a SIC MOSFET device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0008] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0009] In a first aspect, an embodiment of the present invention provides a SIC MOSFET device, such as Figure 1 As shown, the SIC MOSFET device may include: N-type epitaxial silicon carbide layer, high-K material suspension layer, gate trench, P body region, N-type active region, connection hole, high-K material dielectric layer, top silicon dioxide layer and metal layer for source electrode interconnection; wherein, The high-K material suspension layer is arranged inside the N-type epitaxial silicon carbide layer; the P body region and the N-type active region are stacked and arranged in the top layer region of the N-type epitaxial silicon carbide layer, and the N-type active region layer is located above the P body region; the gate trench and the connection hole are arranged in the N-type epitaxial silicon carbide layer and extend to a position below the P body region; the gate trench is located directly above the high-K material suspension layer; the inner wall of the gate trench is provided with a gate oxide layer and the groove is filled with a polysilicon gate; the high-K material dielectric layer is arranged in the bottom region of the connection hole; the top silicon dioxide layer is arranged on the surface of the N-type active region and the gate trench; the metal layer is filled in the connection hole and covers the upper region of the top silicon dioxide layer.

[0010] In the embodiment of the present invention, the high-K material is a high-k material, which refers to a high dielectric constant material. In this field, the high-k material is relative to SiO2 (silicon dioxide). As long as the dielectric constant is greater than the dielectric constant of SiO2 3.9, it is generally called a high-k material. The embodiment of the present invention does not limit which high-k material is used.

[0011] See also Figure 1 It can be seen that the high-K material suspension layer is located at a lower position inside the N-type epitaxial silicon carbide layer; a gate trench is arranged directly above each high-K material suspension layer, and there is a spacing between the high-K material suspension layer and the gate trench directly above it. The depth of the gate trench exceeds the lower edge of the P body region; the depth of the contact hole (CT hole for short) can be equal to or less than the depth of the gate trench, but also exceeds the lower edge of the P body region; this is because the bottom of the gate trench exceeds the bottom of the P body region, the channel can form an inversion layer to conduct current; the bottom of the contact hole exceeds the bottom of the P body region, the high-K material can effectively protect the electric field of the gate oxide on the side wall of the gate trench. A stacked structure formed by the P body region and the N-type active region is separated between the contact hole and the gate trench; the upper surface of the high-K material dielectric layer in the contact hole is higher than the lower upper surface of the P body region but does not exceed the upper surface of the P body region.

[0012] In the embodiment of the present invention, a high-K material suspension layer is formed by introducing a high-K material into the N-type epitaxial silicon carbide layer, and the high-K material is evenly distributed in the bottom region of the gate trench to form a suspended high-K dielectric layer, which can protect the gate oxide layer at the bottom of the gate trench from the influence of the reverse high electric field during withstand voltage. At the same time, a high-K material dielectric layer is also introduced at the bottom of the connection hole to protect the gate oxide layer at the corner of the gate trench from the influence of the reverse high electric field; by introducing the high-K material in these two ways, the gate oxide can be protected from the influence of the high electric field, which can effectively protect the gate oxide, improve the life of the gate oxide, improve the reliability of the device, and do not need to use a dummy trench to sacrifice the current capacity of the device.

[0013] The parameters such as the size of each part of the SIC MOSFET device can be set as required, and optional implementation methods are given below as examples.

[0014] The thickness of the N-type epitaxial silicon carbide layer is greater than 2 μm. The doping concentration of the N-type epitaxial silicon carbide layer can be e 16 cm -3 ~e 17 cm -3 .

[0015] The thickness of the high-K material suspension layer may be 0.3-0.5 μm.

[0016] The thickness of the high-K material dielectric layer may be 0.4-0.5 μm.

[0017] The depth of the gate trench and the connection hole may be 1 μm. In the embodiment of the present invention, the depth of the gate trench is greater than the depth of the P body region, and the depth of the P body region is greater than the depth of the N-type active region, so that a channel inversion layer can be formed by applying a voltage through the gate trench.

[0018] The distance between the gate trench and the underlying high-K material suspension layer may be 0.3-0.5 μm.

[0019] The polysilicon gate is N-type doped, and the doping concentration can be e 16 cm -3 ~e 19 cm -3 .

[0020] The doping element of the P body region is aluminum, and the doping concentration can be e 15 cm -3 ~e 17 cm -3 , the depth can be 0.6-0.7 μm; The doping element of the N-type active region is nitrogen, and the doping concentration can be e 15 cm -3 ~e 17 cm -3 , the depth can be 0.2~0.3μm.

[0021] The material of the metal layer may be aluminum.

[0022] The SIC MOSFET device provided by the present invention can effectively protect the gate oxide of the trench from being affected by the large electric field during reverse withstand voltage, thereby improving the robustness and reliability of the gate oxide, improving the breakdown withstand voltage of the device, and reducing the leakage of the gate oxide of the device.

[0023] In a second aspect, an embodiment of the present invention further provides a method for preparing a SIC MOSFET device, such as Figure 2 As shown, the method may include: S1, select N-type epitaxial silicon carbide wafer; This step is shown in FIG. 3( a ). The thickness of the N-type epitaxial silicon carbide wafer can be selected as required, and the doping concentration can be e 16 cm -3 ~e 17 cm -3 .

[0024] S2, depositing a layer of high-K material on the N-type epitaxial silicon carbide wafer, and removing the high-K material in a partial area by photolithography and dry etching processes to form a high-K material suspension layer; Please refer to FIG. 3( b ) first, the thickness of the high-K material deposited on the N-type epitaxial silicon carbide wafer may be 0.3-0.5 μm.

[0025] After removing the high-K material in some areas by photolithography and dry etching, the high-K material suspension layer formed is shown in FIG3(c), which shows three high-K material suspension layers evenly spaced and having the same size. Please refer to the relevant technical understanding for the photolithography and dry etching processes, and the specific process parameters are not limited here.

[0026] S3, growing N-type epitaxial silicon carbide material again on the surface of the current device and covering the high-K material suspension layer, the grown N-type epitaxial silicon carbide material and the previous N-type epitaxial silicon carbide sheet together constitute an N-type epitaxial silicon carbide layer; This step is shown in FIG. 3( d ). The thickness of the grown N-type epitaxial silicon carbide material can be 1.3 to 1.5 μm, and needs to completely cover the high-K material suspension layer. The doping concentration is the same as S1, which can be e 16 cm -3 ~e 17 cm -3 .

[0027] The N-type epitaxial silicon carbide material grown this time and the previous N-type epitaxial silicon carbide wafer together constitute an N-type epitaxial silicon carbide layer.

[0028] S4, defining a gate trench in the N-type epitaxial silicon carbide layer above the high-K material suspension layer by using photolithography and dry etching processes, depositing a gate oxide layer on the inner wall of the gate trench, and forming a polysilicon gate by filling the trench; Please refer to FIG. 3( e ) for understanding this step. The process parameters of the photolithography and dry etching processes are not limited here. The depth of the gate trench can be 1 μm. However, it is necessary to ensure that there is a spacing between the gate trench and the underlying high-K material suspension layer, wherein the spacing between the gate trench and the underlying high-K material suspension layer can be 0.3-0.5 μm.

[0029] The thickness of the gate oxide layer deposited on the inner wall of the gate trench can be set as required; the gate oxide layer can be silicon dioxide.

[0030] The polysilicon gate filled in the gate trench is N-type doped, and the doping concentration can be e 16 cm -3 ~e 19 cm -3 .

[0031] S5, forming a P body region and an N type active region in the top region of the N-type epitaxial silicon carbide layer by an ion implantation process; Please refer to FIG. 3( f ) for understanding this step. The P body region and the N-type active region are formed by ion implanting the N-type epitaxial silicon carbide layer. The P body region and the N-type active region are arranged from bottom to top. The lower surface of the P body region is higher than the lower surface of the gate trench. The doping element of the P body region may be aluminum, and the doping concentration may be e 15 cm -3 ~e 17 cm -3 , the depth can be 0.6-0.7 μm; The doping element of the N-type active region may be nitrogen, and the doping concentration may be e 15 cm -3 ~e 17 cm -3 , the depth can be 0.2~0.3μm.

[0032] The remaining process parameters of the ion implantation process are not limited here.

[0033] S6, defining a connection hole in the N-type epitaxial silicon carbide layer by using photolithography and dry etching processes, so that the connection hole extends to a position below the P body region, and retaining the top silicon dioxide layer during the dry etching process; Please refer to Figure 3(g) for understanding this step. Using photolithography and dry etching processes, connection holes are defined at intervals in the area next to the gate trench. The depth of the connection hole can be the same as the depth of the gate trench, that is, the depth of the connection hole can be 1μm, or the depth of the connection hole can be slightly less than the depth of the gate trench, but its depth must exceed the depth of the P body region.

[0034] It can be understood that in the process of forming the connection hole, in order to protect the gate trench, the N-type epitaxial silicon carbide layer needs to first deposit a layer of silicon dioxide layer (i.e., the top silicon dioxide layer), and then perform photolithography and dry etching. The embodiment of the present invention only etches away the top silicon dioxide layer in the area corresponding to the connection hole, thereby forming a connection hole downward. Therefore, after this step, except for the position of the connection hole, the rest of the top silicon dioxide layer is still retained.

[0035] S7, depositing a layer of high-K material in the bottom area of ​​the connection hole to form a high-K material dielectric layer; Please refer to FIG. 3(h) for understanding this step. The high-K material deposited in the bottom area of ​​the connection hole may have a thickness of 0.4 to 0.5 μm. The upper surface of the high-K material dielectric layer formed is higher than the lower surface of the P body region but lower than the upper surface of the P body region.

[0036] S8, depositing a metal layer in the connection hole and on the surface of the top silicon dioxide layer to form source electrode interconnection, thereby obtaining a SIC MOSFET device.

[0037] Please refer to FIG. 3( i ) for understanding this step. The material of the metal layer may be aluminum.

[0038] At this point, the device preparation is completed.

[0039] The method for preparing the SIC MOSFET device provided in the embodiment of the present invention has no restrictions on the process, so it has high compatibility and low process implementation cost. Specifically, by growing N-SiC epitaxy, a high-K dielectric material is introduced, and the high-K dielectric material is evenly distributed in the bottom region of the gate trench to form a suspended high-K dielectric layer, which can protect the gate oxide layer at the bottom of the gate trench from the influence of the reverse high electric field during withstand voltage, and can effectively improve the reverse withstand voltage level of the device. At the same time, a high-K dielectric layer is also introduced at the bottom of the CT hole to protect the gate oxide layer at the corner of the gate trench from the influence of the reverse high electric field. By introducing high-K dielectric materials in these two ways, the gate oxide can be effectively protected from the influence of the high electric field when the device is reverse biased. However, the gate oxide is not protected by injection, which can effectively protect the gate oxide, increase the life of the gate oxide, and improve the reliability of the device. The current capacity of the device does not need to be sacrificed through the Dummy trenches on both sides of the gate, which improves the current flow capacity and is easier to implement. Compared with the introduction of ion implantation in SIC, the process difficulty is greatly reduced. At the same time, due to the introduction of high-K dielectric materials in the epitaxial layer, the Crss (Miller capacitance) and Coss (output capacitance) of the SIC MOSFET can be reduced, the switching speed of the device is accelerated, and the switching loss of the device is reduced.

[0040] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A SIC MOSFET device, characterized in that: include: N-type epitaxial silicon carbide layer, high-K material suspension layer, gate trench, P body region, N-type active region, connection hole, high-K material dielectric layer, top silicon dioxide layer and metal layer for source electrode interconnection; wherein, The high-K material suspension layer is arranged inside the N-type epitaxial silicon carbide layer; the P body region and the N-type active region are stacked and arranged in the top region of the N-type epitaxial silicon carbide layer, and the N-type active region layer is located above the P body region; the gate trench and the connection hole are arranged in the N-type epitaxial silicon carbide layer and extend to a position below the P body region; The gate trench is located directly above the high-K material suspension layer; a gate oxide layer is provided on the inner wall of the gate trench and the trench is filled with a polysilicon gate; the high-K material dielectric layer is provided in the bottom area of ​​the connection hole; the top silicon dioxide layer is provided on the surface of the N-type active area and the gate trench; the metal layer is filled in the connection hole and covers the upper area of ​​the top silicon dioxide layer.

2. The SIC MOSFET device according to claim 1, characterized in that: The doping concentration of the N-type epitaxial silicon carbide layer is e 16 cm -3 ~e 17 cm -3 .

3. The SIC MOSFET device according to claim 1, characterized in that: The thickness of the high-K material suspension layer is 0.3-0.5 μm.

4. The SIC MOSFET device according to claim 1, characterized in that: The thickness of the high-K material dielectric layer is 0.4-0.5 μm.

5. The SIC MOSFET device according to claim 1, characterized in that: The gate trench and the connection hole have a depth of 1 μm.

6. The SIC MOSFET device according to claim 1, characterized in that: The distance between the gate trench and the underlying high-K material suspension layer is 0.3-0.5 μm.

7. The SIC MOSFET device according to claim 1, characterized in that: The polysilicon gate is N-type doped with a doping concentration of e 16 cm -3 ~e 19 cm -3 .

8. The SIC MOSFET device according to claim 1, characterized in that: The doping element of the P body region is aluminum, and the doping concentration is e 15 cm -3 ~e 17 cm -3 , with a depth of 0.6 to 0.7 μm; the doping element of the N-type active region is nitrogen, and the doping concentration is e 15 cm -3 ~e 17 cm -3 , the depth is 0.2~0.3μm.

9. The SIC MOSFET device according to claim 1, characterized in that: The material of the metal layer is aluminum.

10. A method for preparing a SIC MOSFET device, characterized in that: include: Selecting N-type epitaxial silicon carbide wafer; Depositing a layer of high-K material on the N-type epitaxial silicon carbide wafer, and removing the high-K material in a partial area by photolithography and dry etching processes to form a high-K material suspension layer; Growing N-type epitaxial silicon carbide material again on the surface of the current device and covering the high-K material suspension layer, the grown N-type epitaxial silicon carbide material and the previous N-type epitaxial silicon carbide sheet together constitute an N-type epitaxial silicon carbide layer; A gate trench is defined in the N-type epitaxial silicon carbide layer above the high-K material suspension layer by using photolithography and dry etching processes, and a gate oxide layer is deposited on the inner wall of the gate trench, and a polysilicon gate is formed by filling the trench; Forming a P-body region and an N-type active region in the top region of the N-type epitaxial silicon carbide layer by an ion implantation process; wherein the P-body region and the N-type active region are arranged from bottom to top, and the lower surface position of the P-body region is higher than the lower surface position of the gate trench; Defining a connection hole in the N-type epitaxial silicon carbide layer by using photolithography and dry etching processes, so that the connection hole extends to a position below the P body region, and retaining the top silicon dioxide layer during the dry etching process; Depositing a layer of high-K material in the bottom area of ​​the connection hole to form a high-K material dielectric layer; A metal layer is deposited in the connection hole and on the surface of the top silicon dioxide layer to form source electrode interconnection, thereby obtaining a SICMOSFET device.

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