High-speed serial data transmission method and system, electronic equipment and medium

Abstract

The invention provides a high-speed serial data transmission method and system, electronic equipment and a medium. Effective data and training codes are alternately set for any LVDS link data in a specific period; the serially transmitted LVDS link data is serial link data, and the serial link data is converted into parallel link data after being subjected to serial-parallel conversion. The method comprises the following steps: a receiving end receives and outputs effective data of each parallel link data to complete effective data receiving; the receiving end receives the training code of each piece of parallel link data; based on the training code, judging a bit alignment state of the valid data; if the effective data and the training codes are not aligned, bit shifting is adopted, so that the effective data and the training codes are in a bit alignment state, and all LVDS link data receiving is completed. According to the method, bit alignment errors are dynamically corrected under the condition that ESD interference exists in high-speed serial data transmission, it is guaranteed that data transmission is automatically recovered after external interference disappears, and the stability of data transmission is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a high-speed serial data transmission method, system, electronic equipment and medium. Background Art

[0002] With the continuous development of high-speed image transmission technology, the requirements for the stable reception capability of high-speed serial data interfaces are also increasing. Usually, in order to improve the anti-interference ability of data transmission, high-speed serial data transmission is usually implemented using LVDS interface.

[0003] In order to ensure that the serial data can be stably received by the data processing system, it is necessary to perform link training on the serial data, that is, to complete the two-step operation of data alignment and bit alignment. Data alignment is to ensure that the clock can stably sample the data by adjusting the input delay of different channels; bit alignment is to align the received serial-to-parallel converted data with the preset training code through bit shifting after data alignment to ensure the correct bit alignment of the serial-to-parallel converted data. After the link completes data alignment and bit alignment, it can be considered that the link training is completed and LVDS high-speed serial data can be received.

[0004] In the traditional LVDS link training method of image sensors, the link is considered locked only after data alignment and bit alignment are completed during the power-on initialization phase of the receiving end, that is, valid data is received. It is assumed that subsequent data transmission is always in a stable state, valid data can be received, and the link alignment state is not judged during valid data reception.

[0005] In actual usage scenarios, the data transmission link may be affected by ESD interference, causing the link bit alignment in LVDS to fail and the system to be unable to recover by itself. If it is not processed, subsequent data transmission will be misaligned.

[0006] Patent CN118648263A discloses a data processing method and a data processing device. The method is applicable to the transmitting end, and periodically obtains P bits from the data stream after cascade FEC encoding, and inserts an alignment mark of W bits in length, so that there are alignment marks of W bits in length in every P+W bits in the data stream. After the receiving end performs frame synchronization (i.e., frame synchronization of P+w bits), also known as the mark locking operation, on the received data, the inner code word synchronization can be guaranteed, and the frame synchronization and inner code word synchronization operations of the receiving end are simplified, and the implementation complexity is relatively low. The content recorded in this patent is applicable to the transmitting end, which is different from the applicable object of this solution and the technical means are different.

[0007] Patent CN102741823B discloses comma alignment with scrambled data, the method comprising a control device generating a data stream that facilitates the implementation and determination of alignment in a device. The data stream comprises a random portion of N Y-bit characters followed by a sequence of Z-bit alignment characters, where N, Y and Z are integers. Another exemplary method comprises a control device receiving and checking the data stream. The method also comprises generating an alignment signal when determining the alignment of recovered data in a device. The content described in the patent is applicable to the transmitting end, which is different from the applicable object of this solution and the technical means are different.

[0008] Patent CN 116149598 A records a real-time alignment method for multi-link data. The patent uses the row start or frame start flag as the basis for alignment, and can also use the difference between the data sent in the sensor empty state and the valid data as the basis for alignment. When each row or frame of data arrives, it will be re-aligned according to the delay between the current links to ensure the real-time alignment. This patent solves the technical problem that due to PCB design, even after data bit alignment, the row data or frame data of different links in one frame of image data are still not aligned, which is different from the technical problem solved by this solution. Summary of the invention

[0009] The present invention provides a high-speed serial data transmission method, system, electronic device and medium, which can solve at least one of the above technical problems.

[0010] To achieve the above object, the present invention proposes a high-speed serial data transmission method, wherein any LVDS link data is alternately provided with valid data and training codes in a specific cycle; the serially transmitted LVDS link data is serial link data, and the serial link data is converted into parallel link data after serial-to-parallel conversion, comprising: The receiving end receives and outputs the valid data of each parallel link data, completing the reception of valid data; The receiving end receives the training code of each parallel link data; based on the training code, the bit alignment status of the valid data is determined; if it is not aligned, bit shifting is used to make the valid data and the training code both in the bit alignment state, completing the reception of all LVDS link data.

[0011] Furthermore, before the receiving end receives and outputs valid data of each parallel link data to complete the reception of valid data, it also includes: After the receiving end is powered on and initialized, a training code is used to perform link training on the link where the LVDS link data is located, so that the LVDS link data of all links remain aligned.

[0012] Furthermore, the link training includes: adjusting the delay values ​​of the serial link data of different links based on the data alignment state of the serial link data so that the phases of the serial link data of different links are aligned; and performing serial-to-parallel conversion and bit shifting on the serial link data after the phase alignment based on the bit alignment state of the serial link data after the phase alignment so that the adjusted bits of several parallel link data are aligned.

[0013] Furthermore, judging the bit alignment state of valid data based on the training code includes: judging whether the code type of the training code received at the same time is consistent with the code type of the preset training code; if they are consistent, the valid data is considered to be in a bit aligned state; otherwise, it is considered to be in a misaligned state.

[0014] Based on the same inventive concept, the present application also proposes a high-speed serial data transmission system, wherein any specific period of LVDS link data is alternately provided with valid data and training codes, and the serially transmitted LVDS link data is serial link data, which is converted into parallel link data after serial-to-parallel conversion, including: The link training module uses the training code to perform link training on the link where the LVDS link data is located after the receiving end is powered on and initialized, so that the LVDS link data of all links remain aligned; The receiving end receives and outputs the valid data of each parallel link data to complete the reception of valid data; receives the training code of each parallel link data; based on the training code, determines the bit alignment status of the valid data; if it is not aligned, bit shifting is used to make the valid data and the training code in the bit alignment state to complete the reception of all LVDS link data.

[0015] Furthermore, it also includes: a buffer or a processing module, which is used to receive the valid data output by the valid data receiving unit.

[0016] Furthermore, the link training includes: adjusting the delay values ​​of the serial link data of different links based on the data alignment state of the serial link data so that the phases of the serial link data of different links are aligned; and performing serial-to-parallel conversion and bit shifting on the serial link data after the phase alignment based on the bit alignment state of the serial link data after the phase alignment so that the adjusted bits of several parallel link data are aligned.

[0017] Furthermore, judging the bit alignment state of valid data based on the training code includes: judging whether the code type of the training code received at the same time is consistent with the code type of the preset training code; if they are consistent, the valid data is considered to be in a bit aligned state; otherwise, it is considered to be in a misaligned state.

[0018] On the other hand, the present invention further proposes an electronic device, comprising a processor and a memory, wherein the memory is used to store a computer program, the computer program comprises program instructions, and the processor is configured to call the program instructions to execute the method as described above.

[0019] In yet another aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method as described above is implemented.

[0020] The beneficial effects of the present invention are: The present invention provides a high-speed serial data transmission method. During the transmission of a training code, a receiving end determines whether a bit alignment error occurs by comparing the code pattern of the received training code with the code pattern of a preset training code.

[0021] If it is judged to be misaligned, the received valid data will be bit-shifted until the received training code is consistent with the preset training code pattern, then it is considered that the valid data and the training code are in the aligned state, that is, the link is restored to the bit-aligned state. In this way, even if a bit error occurs during data transmission due to ESD interference, it can be automatically recovered during the transmission interval of valid data.

[0022] The present invention can ensure that bit alignment errors are dynamically corrected during data transmission intervals, ensure that data transmission recovers automatically after external interference disappears, and improve the stability of data transmission.

[0023] The present invention utilizes the training code during the effective data transmission interval to judge and dynamically correct the dynamic bit alignment state, thereby ensuring the stability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a flowchart of a dynamic bit alignment method; Figure 2 This is a schematic diagram of the format of LVDS link data; Figure 3 It is a schematic diagram of the format of LVDS link data in this embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0026] like Figure 1 As shown, the present invention provides a high-speed serial data transmission method.

[0027] Any LVDS link data alternately sets valid data and training codes in a specific cycle. The LVDS link data transmitted serially is serial link data, and the serial link data is parallel link data after serial-to-parallel conversion.

[0028] like Figure 2 As shown, in this embodiment, the transmission format of the LVDS link data transmitted in a serial communication manner is “...-training code-valid data-training code-valid data-...”.

[0029] Based on the unique format of LVDS link data, the bit alignment status of valid data is determined through the training code sent during the link period, without the need to set additional alignment codes or other flag codes.

[0030] The method specifically comprises: After the receiving end is powered on and initialized, a training code is used to perform link training on the link where the LVDS link data is located, so that the LVDS link data of all links remain aligned.

[0031] Link training includes: adjusting the delay values ​​of serial link data of different links based on the data alignment state of serial link data so that the phases of serial link data of different links are aligned; and performing serial-to-parallel conversion and bit shifting on the serial link data after phase alignment based on the bit alignment state of the serial link data after phase alignment so that the adjusted bits of several parallel link data are aligned.

[0032] Based on the training code, the bit alignment state of the valid data is judged, including: judging whether the code type of the training code received at the same time is consistent with the code type of the preset training code; if consistent, it is considered that the valid data is in a bit aligned state; otherwise, it is considered to be in a misaligned state.

[0033] The receiving end receives and outputs the valid data of each parallel link data, completing the reception of valid data; The receiving end receives the training code of each parallel link data; based on the training code, the bit alignment status of the valid data is determined; if it is not aligned, bit shifting is used to make the received valid data and training code in the bit alignment state, completing the reception of all LVDS link data.

[0034] Based on the same inventive concept, the present application also proposes a high-speed serial data transmission system, which is applicable to the above method, comprising: The link training module uses the training code to perform link training on the link where the LVDS link data is located after the receiving end is powered on and initialized, so that the LVDS link data of all links remain aligned; The receiving end receives and outputs the valid data of each parallel link data to complete the reception of valid data; receives the training code of each parallel link data; based on the training code, determines the bit alignment status of the valid data; if it is not aligned, bit shifting is used to make the valid data and the training code in the bit alignment state to complete the reception of all LVDS link data.

[0035] It also includes: a buffer or a processing module, which is used to receive the valid data output by the valid data receiving unit.

[0036] In this embodiment, the receiving end is an FPGA and the sending end is an image sensor.

[0037] In this embodiment, in the serial link data output by the image sensor, the training code is "1000_1111_1110"; the valid data is a number of pixel grayscale data, such as Figure 3 shown.

[0038] When the FPGA is powered on and initialized, and link training is started for the serial link data, a number of parallel data can be obtained, and the format of any parallel data is "training code-pixel grayscale data".

[0039] The link training process includes: Determine whether the data phase of the serial link data is aligned. If not, adjust the link input delay value to determine whether the adjusted data phase is aligned; until the link data phases of all links are aligned, enter the training code bit alignment determination.

[0040] The serial link data after phase alignment is converted into parallel data. If the training code bits of the parallel data are not aligned, bit shifting is used to determine whether the adjusted training code is aligned. Once the training code is aligned, parallel data transmission begins.

[0041] If ESD interference occurs during the transmission of parallel data, a bit alignment error may occur in any parallel data; at this time, the other parallel data behind it are all in an error state and inconsistent with the transmitted data.

[0042] The receiving end first receives the valid data of the parallel data, and stores the valid data in a buffer area or outputs it to other image processing modules.

[0043] When the receiving end receives the training code of the parallel data again, it determines whether a bit alignment error occurs by comparing whether the code pattern of the received training code is consistent with the code pattern of the preset training code.

[0044] If it is judged to be misaligned, for example, when the received training code is "0001_1111_1101", it is considered that the bit alignment state is wrong. At this time, a bit shift operation will be performed on the received valid data until the received training code is restored to "1000_1111_1110". It is then considered that the subsequent pixel grayscale data and the training code are in the aligned state, that is, the link is restored to the bit aligned state.

[0045] The training codes in the subsequent received parallel data are judged one by one to ensure that the received valid data is consistent with the sent data, until all parallel data are received.

[0046] On the other hand, the present invention further proposes an electronic device, comprising a processor and a memory, wherein the memory is used to store a computer program, the computer program comprises program instructions, and the processor is configured to call the program instructions to execute the method as described above.

[0047] In yet another aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method as described above is implemented.

[0048] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed serial data transmission method, in which any LVDS link data is alternately provided with valid data and training codes in a specific cycle; The LVDS link data transmitted in serial is serial link data, which is converted into parallel link data after serial-to-parallel conversion, and is characterized by including: The receiving end receives and outputs the valid data of each parallel link data, completing the reception of valid data; The receiving end receives the training code of each parallel link data; based on the training code, the bit alignment status of the valid data is determined; if it is not aligned, bit shifting is used to make the valid data and the training code both in the bit alignment state, completing the reception of all LVDS link data.

2. The high-speed serial data transmission method according to claim 1, characterized in that: The receiving end receives and outputs valid data of each parallel link data to complete the reception of valid data, and before that, it also includes: After the receiving end is powered on and initialized, a training code is used to perform link training on the link where the LVDS link data is located, so that the LVDS link data of all links remain aligned.

3. The high-speed serial data transmission method according to claim 2, characterized in that: The link training includes: adjusting the delay values ​​of serial link data of different links based on the data alignment state of the serial link data so that the phases of the serial link data of different links are aligned; and performing serial-to-parallel conversion and bit shifting on the serial link data after the phase alignment based on the bit alignment state of the serial link data after the phase alignment so that the adjusted bits of several parallel link data are aligned.

4. The high-speed serial data transmission method according to claim 1, characterized in that: The bit alignment state of the valid data is determined based on the training code, including: determining whether the code type of the training code received at the same time is consistent with the code type of the preset training code; if consistent, the valid data is considered to be in a bit aligned state; otherwise, it is considered to be in a misaligned state.

5. A high-speed serial data transmission system, wherein any specific period of LVDS link data is alternately provided with valid data and training codes, the serially transmitted LVDS link data is serial link data, and the serial link data is parallel link data after serial-to-parallel conversion, characterized in that: include: The link training module uses the training code to perform link training on the link where the LVDS link data is located after the receiving end is powered on and initialized, so that the LVDS link data of all links remain aligned; The receiving end receives and outputs the valid data of each parallel link data, completing the reception of valid data; receives the training code of each parallel link data; Based on the training code, the bit alignment status of the valid data is determined; if it is not aligned, bit shifting is used to make the valid data and the training code both in the bit alignment state, completing the reception of all LVDS link data.

6. The high-speed serial data transmission system according to claim 5, characterized in that: Also includes: The buffer or processing module is used to receive the valid data output by the valid data receiving unit.

7. The high-speed serial data transmission system according to claim 5, characterized in that: The link training includes: adjusting the delay values ​​of serial link data of different links based on the data alignment state of the serial link data so that the phases of the serial link data of different links are aligned; and performing serial-to-parallel conversion and bit shifting on the serial link data after the phase alignment based on the bit alignment state of the serial link data after the phase alignment so that the adjusted bits of several parallel link data are aligned.

8. The high-speed serial data transmission system according to claim 5, characterized in that: The bit alignment state of the valid data is determined based on the training code, including: determining whether the code type of the training code received at the same time is consistent with the code type of the preset training code; if consistent, the valid data is considered to be in a bit aligned state; otherwise, it is considered to be in a misaligned state.

9. An electronic device, comprising a processor and a memory, characterized in that: The memory is used to store a computer program, the computer program includes program instructions, and the processor is configured to call the program instructions to execute the method according to any one of claims 1-4.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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