Computer interlocking system of distributed communication network topological structure

Abstract

The invention discloses a computer interlocking system of a distributed communication network topological structure, and relates to the technical field of communication, the computer interlocking system comprises an indoor interlocking system and an outdoor interlocking control system, the indoor interlocking system comprises an interlocking machine, a control display machine and an interlocking side communication gateway; the outdoor interlocking control system comprises a plurality of target controllers, and each target controller comprises an IO side communication gateway and an IO execution module. The interlocking machine and the control display machine are connected through the Ethernet, and the interlocking machine and the interlocking side communication gateway are connected through a serial port; the interlocking side communication gateway Ethernet can be expanded to at most 20 IO side nodes through external network switch equipment and passive optical fiber splitter equipment, communication connection is established between the interlocking side communication gateway Ethernet and 20 IO side communication gateways, the IO side communication gateways are connected with IO execution modules through CAN buses, and the CAN bus of each IO side communication gateway supports at most 30 IO execution modules; according to the computer interlocking system, the data transmission capacity and the transmission rate are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a computer interlocking system with a distributed communication network topology structure. Background Art

[0002] At present, most traditional interlocking systems are centralized control systems. When the station is expanded or the track line is changed, it is necessary to dig trenches and bury pipelines again, and to electrically connect the outdoor actuators with the control room system. This operation is difficult and costly. When the station scale is complex, a large number of devices are used, and the various cables between indoors and outdoors are more complicated, which is very unfavorable to the electromagnetic environment and affects the data transmission capacity and efficiency. Summary of the invention

[0003] Based on the technical problems existing in the background technology, the present invention proposes a computer interlocking system with a distributed communication network topology structure to solve the problem of complicated wiring and improve the data transmission capacity and transmission rate.

[0004] The present invention proposes a computer interlocking system with a distributed communication network topology structure, comprising an indoor interlocking system and an outdoor interlocking control system, wherein the indoor interlocking system comprises an interlocking machine, a control and display machine, and an interlocking side communication gateway; the outdoor interlocking control system comprises a plurality of target controllers, each of which comprises an IO side communication gateway and an IO execution module;

[0005] The interlocking machine and the control and display machine are connected via Ethernet, and the interlocking machine and the interlocking side communication gateway are connected via a serial port;

[0006] The interlocking side communication gateway Ethernet can be expanded to a maximum of 20 IO side nodes through external network switch equipment and passive optical fiber splitter equipment, and establish communication connections with 20 IO side communication gateways respectively;

[0007] The IO side communication gateway is connected to the IO execution module through the CAN bus. The CAN bus of each IO side communication gateway supports up to 30 IO execution modules.

[0008] Furthermore, the indoor interlocking system also includes a maintenance computer, which is connected to the interlocking side communication gateway and the IO side communication gateway through Ethernet to share an Ethernet bus.

[0009] Furthermore, the interlocking machine includes an interlocking main system and an interlocking backup system, and the interlocking main system and the interlocking backup system are redundantly arranged.

[0010] Furthermore, the communication gateway includes an interlocking side communication gateway and an IO side communication gateway. The communication gateway MCU has no hot reset status register, and a power-on delay circuit is added to the hardware circuit. When the reset flag is determined during MCU initialization, the output state of the power-on delay circuit is combined to determine whether the IO execution module is normally powered on and reset initialized or hot reset initialized. The power-on delay circuit shares a power supply with the MCU, starts timing and outputs a low level at the power-on moment, and the output state of the power-on delay circuit is changed to a fixed high level after a time greater than T6, and the state does not change when the communication gateway module is not powered off.

[0011] Furthermore, the interlocking machine receives the operation command from the control and display machine, and sends it to the interlocking side communication gateway according to the virtual address. The interlocking side communication gateway converts the operation command through the address mapping table, and sends it to the IO side communication gateway through the Ethernet port according to the actual module address. The IO side communication gateway then sends it to the IO execution module to control the on-site equipment.

[0012] The IO side communication gateway reads the data signal status of the field equipment from the IO execution module, and sends the safety data to the interlocking side communication gateway via Ethernet. The interlocking side communication gateway reports the collected data signal status to the interlocking machine, and parses the control command of the interlocking machine according to the address mapping label, recompresses it and broadcasts it to the IO side communication gateway to control the IO execution module. At the same time, the IO side communication gateway sends the non-safety data to the maintenance computer via Ethernet. The interlocking side communication gateway and the maintenance computer use the Ethernet interface to realize the fault information reporting of the interlocking side communication gateway.

[0013] Furthermore, the address mapping table is obtained and processed as follows:

[0014] When the number of target controllers is less than or equal to 12, the virtual communication machine address and the simulation module address are the same, and there is no mapping transformation relationship. The interlocking side communication gateway directly sends the operation command to the IO side communication gateway; when the number of target controllers is greater than 12, the distributed actual module addresses and the centralized virtual addresses are organized into an address mapping table table1 and an index table index_table1 of table1. The address mapping table table1 stores the virtual communication address, virtual module address, target controller address and actual module address of the device;

[0015] The converted virtual communication machine address and virtual module address are written into the interlocking system configuration data. The interlocking machine reads the interlocking system configuration data, and sends the address mapping table table1 and the index table index_table1 of table1 to the interlocking side communication gateway through the serial port after compression during the registration process;

[0016] The interlocking side communication gateway obtains the virtual address through the actual module address according to the address mapping table table1 and the index table index_table1, or obtains the actual module address through the virtual address according to the address mapping table table1 and the index table index_table1.

[0017] Furthermore, RS422-1 and RS422-2 of the interlocking side communication gateway are connected to the interlocking machine main system and the interlocking machine standby system respectively, RS422-1 data is forwarded via Ethernet NET1, and RS422-2 data is forwarded via Ethernet NET2;

[0018] The Ethernet NET1 and NET2 of the interlocking side communication gateway and the Ethernet NET1 and NET2 of the IO side communication gateway are connected using the Ethernet communication protocol;

[0019] The communication gateway on the interlocking side packages the message sent by the interlocking machine and broadcasts it to 20 target controllers; after receiving the response data from the 20 nodes of the target controller, it composes up to 12 virtual communication machine messages and forwards them to the interlocking machine.

[0020] Furthermore, the data transmission process of the interlocking side communication gateway is:

[0021] When any RS422 serial port of the interlocking communication gateway receives data, the interlocking communication gateway CPU1 processes the data of RS422_1, and the interlocking communication gateway CPU2 processes the data of RS422_2. Both CPUs are synchronized through SPI and are controlled by the interlocking communication gateway CPU1.

[0022] When the interlocking side communication gateway RS422-1 receives the data from the interlocking machine, it passes the received data to the interlocking side communication gateway CPU2 through SPI, and the interlocking side communication gateway CPU2 verifies the signature CRC of the received data, prepares the response data and calculates the signature CRC of the response data. The interlocking side communication gateway CPU1 requests the signature CRC calculation result and the signature CRC of the response data from the interlocking side communication gateway CPU2;

[0023] When the interlocking side communication gateway RS422-2 receives the data from the interlocking machine, it passes the data to the interlocking side communication gateway CPU1 through SPI, and the interlocking side communication gateway CPU1 verifies the transmission CRC of the received data, prepares the response data and calculates the transmission CRC of the response data. The interlocking side communication gateway CPU2 requests the interlocking side communication gateway CPU1 to transmit the CRC calculation result and the transmission CRC of the response data;

[0024] When receiving RS422 data with the virtual communication machine address of 1, the timer of T1 time is started. After T1 time, it is considered that the data reception is completed, and the interlocking machine ends the current cycle search;

[0025] After RS422 data reception is completed, the signature CRC sent by Ethernet is obtained first, and the broadcast packet is sent, and finally the non-safe data is sent;

[0026] After receiving the RS422 data, the interlocking communication gateway RS422-1 starts the T2 timer. When the T2 time is exceeded, Ethernet parsing is performed to prepare to fill in the broadcast data sent to the IO communication gateway. The interlocking communication gateway CPU1 requests the signature CRC of the NET1 broadcast data from CPU2, and then sends it out through NET1 after the broadcast data is filled.

[0027] After receiving the RS422 data, the interlocking side communication gateway RS422-2 starts the T2 timer. When the T2 time is exceeded, Ethernet parsing is performed to start preparing to fill in the broadcast data of NET2 sent to the IO side communication gateway. The interlocking side communication gateway CPU2 requests the transmission CRC of the NET2 broadcast data from the interlocking side communication gateway CPU1, and then sends it out through NET2 after the broadcast data is filled.

[0028] Furthermore, the data transmission process of the IO side communication gateway is:

[0029] When any NET network port of the IO side communication gateway receives data, the IO side communication gateway CPU1 processes the data of NET1, and the IO side communication gateway CPU2 processes the data of NET2. Both CPUs are synchronized through SPI and are controlled by CPU1. The IO side communication gateway CPU1 transmits the data received by the NET1 network port to the IO side communication gateway CPU2, which verifies the signature CRC, prepares the response data, and calculates the signature CRC of the response data. The IO side communication gateway CPU1 requests the IO side communication gateway CPU2 for the signature CRC calculation result and the signature CRC of the response data.

[0030] The IO side communication gateway CPU2 transmits the data received by the NET2 network port to the IO side communication gateway CPU1, which verifies the transmission CRC, prepares the response data and calculates the transmission CRC of the response data. The IO side communication gateway CPU2 requests the IO side communication gateway CPU1 to transmit the CRC calculation result and the transmission CRC of the response data.

[0031] The IO side communication gateway CPU1 sends a CAN search flag to the IO side communication gateway CPU2 via SPI, so that the IO side communication gateway CPU2 starts the CAN search;

[0032] If the IO side communication gateway receives data forwarded by the main system interlocking machine, it will immediately search for the main system. If it receives data forwarded by the standby system interlocking machine and Ethernet registration is completed, it will wait for T4 time. If there is no main system search within T4 time, it will search for the standby system. If there is a main system search, it will execute the main system search.

[0033] When CAN registration is successful, the device information reported by the IO execution module is compressed and packaged by the IO side communication gateway and uploaded to the interlocking side communication gateway. Before CAN registration is completed, the device information sent to the Ethernet data is empty.

[0034] Furthermore, the maintenance computer data reporting process is as follows:

[0035] The maintenance computer exchanges data with the IO side communication gateway via Ethernet, and the maintenance computer target IP corresponding to each NET is different;

[0036] When the maintenance computer sends the relevant command data for querying the IO execution module, NET1 or NET2 receives the data and sends it to another CPU through synchronization. The IO side communication gateway sends it to the IO execution module through CAN. After the IO execution module responds to the IO side communication gateway, the IO side communication gateway parses and packages it into Ethernet data and then uploads it to the maintenance computer.

[0037] When the maintenance computer sends out query command data related to the IO side communication gateway itself, the IO side communication gateway receives the data, parses it and packages it into Ethernet data for response. At the same time, if the IO side communication gateway fails, the fault code is synchronously packaged and uploaded;

[0038] In addition to querying data, the maintenance computer is also used to control DIDO input and output. After NET1 or NET2 receives the DO control command, it will synchronize the DO control command to another CPU, and the IO side communication gateway CPU1 controls the DO output; the DI input status is detected by the IO side communication gateway CPU2, and the detected status is also synchronized to the IO side communication gateway CPU1 via SPI; when the maintenance computer queries the DIDO status through NET1 or NET2, the IO side communication gateway will report the data.

[0039] The advantages of the computer interlocking system with a distributed communication network topology structure provided by the present invention are as follows: the computer interlocking system with a distributed communication network topology structure provided in the structure of the present invention separates the outdoor actuator from the control room system, the network main node is installed indoors or centrally in the interlocking cabinet, and the remaining sub-nodes are all distributed in various areas of the outdoor station field. The system is divided into indoor and outdoor areas, which makes the station field wiring more convenient. Ethernet as an intermediate data communication method can improve the data transmission capacity and transmission rate, and improve the efficient execution and good maintainability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is the hardware communication connection diagram of the computer interlocking system;

[0041] Figure 2 It is the working flow chart of the interlocking side communication gateway;

[0042] Figure 3 This is the workflow diagram of the IO side communication gateway;

[0043] Figure 4 This is the data transmission and reception timing diagram of the interlocking side communication gateway;

[0044] Figure 5 This is the timing diagram of data transmission and reception of the IO side communication gateway;

[0045] Figure 6 It is the timing logic diagram of the power-on delay circuit of the communication gateway. DETAILED DESCRIPTION

[0046] Below, the technical solution of the present invention is described in detail through specific embodiments. Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific implementation disclosed below.

[0047] The biggest difference between this embodiment and the traditional centralized control system in terms of hardware is that communication gateway equipment and switches are used to replace traditional communication machines and optical fiber splitters.

[0048] like Figures 1 to 6 As shown, the present invention proposes a computer interlocking system with a distributed communication network topology structure, including an indoor interlocking system and an outdoor interlocking control system, wherein the indoor interlocking system includes an interlocking machine, a control and display machine, and an interlocking side communication gateway; the outdoor interlocking control system includes multiple target controllers, each target controller includes an IO side communication gateway and an IO execution module; the interlocking machine and the control and display machine are connected through Ethernet, the interlocking machine and the interlocking side communication gateway are connected through a serial port, the interlocking side communication gateway and the IO side communication gateway are connected through Ethernet, and the IO side communication gateway and the IO execution module are connected through a CAN bus.

[0049] This embodiment separates the outdoor actuator from the control room system. The main network node is installed indoors or centrally in an interlocking cabinet, and the remaining sub-nodes are all distributed in various areas of the outdoor station. Dividing the system into indoor and outdoor makes station wiring more convenient. Ethernet as an intermediate data communication method can increase data transmission capacity and transmission rate, improve the efficient execution of the system and improve maintainability.

[0050] In this embodiment, two interlocking machines, two interlocking side communication gateways, one master-slave switcher, two control and display computers and one maintenance computer are installed in one cabinet. Outdoors, up to 20 target controllers (i.e., centralized control areas) are supported, each of which is equipped with two IO side communication gateways, a maximum of five IO cages, and each IO cage can be inserted with a maximum of six IO execution modules, as well as several turnout transfer machines, signal machines, track circuits, etc. corresponding to the IO execution modules. Both the interlocking side communication gateway and the IO side communication gateway use a power-on delay circuit to distinguish whether a hot reset or a power-on reset occurs; after the communication gateway module is powered on and the timer is initialized, the delay circuit detection pin is detected every 1ms before the first watchdog feeding. The continuous monitoring results are all low levels, indicating that the power-on delay circuit is effective and operating normally.

[0051] Among them, the interlocking machine is the core module of the computer interlocking system. The interlocking machine reads the basic data of the station field from the interlocking system configuration data, and the basic data of the station field is generated by the dedicated basic data configuration software. The interlocking machine receives the operation command from the control and display machine, and after the logical operation of these commands, sends them to the interlocking side communication gateway according to the virtual address. The interlocking side communication gateway converts these commands through the address mapping table, and sends them to the IO side communication gateway through the Ethernet port according to the real address. The IO side communication gateway then sends them to the final IO execution module to control the equipment on site.

[0052] The IO side communication gateway reads the signal status of the field equipment from the IO execution module, including the track circuit status, signal status and switch position information. The interlocking side communication gateway reports the collected IO execution module data to the interlocking machine, and forwards the control command of the interlocking machine to the IO side communication gateway. The IO side communication gateway communicates with the IO execution module as the host, collects the data detected by the IO execution module, and controls the output of the IO execution module. The CAN interface between the IO side communication gateway and the IO execution module realizes the collection of operation-related data inside the IO execution module. The IO side communication gateway sends safety data to the interlocking side communication gateway through the Ethernet interface, and sends non-safety data to the maintenance computer. The interlocking side communication gateway and the maintenance computer realize the reporting of fault information of the interlocking side communication gateway through the Ethernet interface. The above-mentioned system is mainly different from the traditional centralized system in the following aspects: the use of address mapping tables, specific data transmission processes, and the reporting of non-safety data by the maintenance computer.

[0053] 1. Acquisition and processing of address mapping table: The distributed interlocking system supports up to 20 centralized control areas outdoors, corresponding to the 20 target controllers in the figure. When the number of target controllers in the distributed interlocking configuration is less than or equal to 12, the virtual communication machine address and the analog module address are the same, and there is no mapping transformation relationship. When the number of target controllers in the distributed interlocking configuration is greater than 12, the converted virtual communication machine address and virtual module address are written into the interlocking system configuration data. The interlocking machine reads the interlocking system configuration data, and sends the address mapping table table1 and the index table index_table1 of table1 to the interlocking side communication gateway through the RS422 serial port after compression during the registration process.

[0054] The distributed actual module addresses and the centralized virtual addresses are organized into an address mapping table table1 and an index table index_table1 of table1. The interlocking side communication gateway obtains the virtual address through the actual module address according to table1 and index_table1, or obtains the actual module address through the virtual address according to table1 and index_table1.

[0055] The interlocking side communication gateway maps the virtual device address in the data sent by the interlocking machine to the real device address through the address mapping table, and forwards the control command sent by the interlocking machine to the IO side communication gateway; when the IO side communication gateway uploads the target controller and IO execution module device information via Ethernet, it is compressed through the address mapping table and reported to the interlocking machine.

[0056] 2. Data transmission process:

[0057] RS422-1 and RS422-2 of the interlocking side communication gateway are connected to two interlocking machines respectively. RS422-1 forwards data with Ethernet NET1, and RS422-2 forwards data with Ethernet NET2. The NET1 and NET2 Ethernet communication interfaces of the interlocking side communication gateway are connected with Ethernet NET1 and NET2 of the IO side communication gateway using Ethernet communication protocol. The interlocking side communication gateway packages the message sent by the interlocking machine and broadcasts it to 20 IO side nodes; after receiving the response data from the 20 IO side nodes, it forms up to 12 virtual communication machine messages and forwards them to the interlocking machine.

[0058] The interlocking side communication gateway data transmission is as follows Figure 4 As shown, any RS422 serial port of the interlocking communication gateway receives the data of RS422-1, the interlocking communication gateway CPU1 processes the data of RS422-1, and the interlocking communication gateway CPU2 processes the data of RS422-2. Both CPUs are synchronized through SPI and are controlled by CPU1.

[0059] When the interlocking side communication gateway CPU1 receives data from the RS422-1 serial port, it will pass the received data to the interlocking side communication gateway CPU2 through SPI, and the interlocking side communication gateway CPU2 will verify the signature CRC of the received data, prepare the response data and calculate the signature CRC of the response data; and request the signature CRC calculation result and the signature CRC of the response data from the interlocking side communication gateway CPU2. Similarly, after the interlocking side communication gateway CPU2 receives data from the RS422-2 serial port, the interlocking side communication gateway CPU2 will pass the data to the interlocking side communication gateway CPU1 through SPI, and the interlocking side communication gateway CPU1 will verify the transmission CRC of the received data, prepare the response data and calculate the transmission CRC of the response data; the interlocking side communication gateway CPU2 will request the transmission CRC calculation result and the transmission CRC of the response data from the interlocking side communication gateway CPU1.

[0060] The data transmission and reception sequence of the interlocking communication gateway is as follows: Figure 6 As shown, when receiving RS422 data with the virtual communication machine address of 1, the timer of T1 time is started. When T1 time is exceeded, it is considered that the data reception is completed, and the interlocking machine search in this cycle is considered to be over. After the RS422 data is received, the signature CRC sent by Ethernet is first obtained, and the broadcast packet is sent, and finally the non-safe data is sent. After receiving the RS422 data, the interlocking side communication gateway CPU1 starts the timer of T2 time. When T2 time is exceeded, Ethernet parsing is performed, and preparations are made to fill in the broadcast data of NET1 sent to the IO side (the broadcast data is received from RS422-1 in this cycle, and the device control command is converted by the address mapping table). The interlocking side communication gateway CPU1 requests the signature CRC of the NET1 broadcast data from the interlocking side communication gateway CPU2, and then after the broadcast data is filled, the interlocking side communication gateway CPU1 sends it out through NET1. Similarly, after receiving the RS422 data, the interlocking side communication gateway CPU1 starts the T2 timer. After T2 time, it is considered that the data reception is completed, and it starts to prepare to fill in the broadcast data of NET2 sent to the IO side communication gateway (the broadcast data is the device control command received from RS422-2 in this cycle and converted by the address mapping table). The interlocking side communication gateway CPU2 requests the transmission CRC of the NET2 broadcast data from the interlocking side communication gateway CPU1, and then after the broadcast data is filled, the interlocking side communication gateway CPU2 sends it out through NET2.

[0061] The data transmission of the IO side communication gateway is shown in Figure 5. When any NET network port of the IO side communication gateway receives data, the IO side communication gateway CPU1 processes the data of NET1, and the IO side communication gateway CPU2 processes the data of NET2. Both CPUs are synchronized through SPI and are controlled by the IO side communication gateway CPU1. The IO side communication gateway CPU1 transmits the data received by the NET1 network port to the IO side communication gateway CPU2, and the IO side communication gateway CPU2 verifies the signature CRC, prepares the response data, and calculates the signature CRC of the response data. The IO side communication gateway CPU1 requests the IO side communication gateway CPU2 for the signature CRC calculation result and the signature CRC of the response data. Similarly, the IO side communication gateway CPU2 transmits the data received by the NET2 network port to the IO side communication gateway CPU1, and the IO side communication gateway CPU1 verifies the transmission CRC, prepares the response data, and calculates the transmission CRC of the response data. The IO side communication gateway CPU2 requests the IO side communication gateway CPU1 for the transmission CRC calculation result and the transmission CRC of the response data. The IO side communication gateway CPU1 also sends a flag that allows CAN search to the IO side communication gateway CPU2 through SPI so that the IO side communication gateway CPU2 can start the CAN search.

[0062] The data transmission and reception timing of the IO side communication gateway is as follows Figure 5 As shown, if the IO side communication gateway receives data forwarded by the main system interlocking machine, it will immediately perform a main system search. If it receives data forwarded by the standby system interlocking machine and the Ethernet registration is completed, it will wait for T4 time. If there is no main system search within T4 time, the standby system search will be performed. If there is a main system search, the main system search will be executed. The CAN search cycle is T5 time. When CAN registration is successful, the IO execution module reports the device information, which is compressed and packaged by the IO side communication gateway and uploaded to the interlocking side communication gateway. Before CAN registration is completed, the device information sent to the Ethernet data is empty.

[0063] The interlocking side communication gateways A and B are in a redundant relationship. The IO side communication gateways A and B of each target controller (i.e., IO cabinet) are also in a redundant relationship. Each IO side communication gateway corresponds to one CAN. Each communication gateway device sets the hardware address ID in the form of a dip switch, ranging from 0 to 255. When the device is powered on, the read hardware pin ID number is bound to the Ethernet local IP. The IDs of the communication gateways that are redundant to each other (interlocking side communication gateways A and B are redundant to each other, and IO side communication gateways A and B are redundant to each other) must be consistent, and the IDs of the remaining communication gateways must be different and unique in the system. In this system, the IDs of the two interlocking side communication gateways in the interlocking cabinet are preset to 21, and the local IP is 192.168.88.21; similarly, the IO side communication gateway is also the same. Usually, the local IP address of the IO side communication gateway is set to 192.168.88.1 to 192.168.88.20.

[0064] It should be noted that the system default is to connect RS422-1 to the main system interlocking machine, and RS422-2 to the standby system interlocking machine. In actual applications, RS422-1 can also be connected to the standby system interlocking machine, and RS422-2 to the main system interlocking machine. The "device control command" is obtained from the data of the interlocking machine main system. If a double-master fault occurs, that is, RS422-1 and RS422-2 are both connected to the interlocking main system or the two interlocking machine states are both main system interlocking machines (the data sent by the two interlocking machines contain device control commands), at this time, when the two RS422 serial ports of the interlocking side communication gateway register with the interlocking machine, which serial port first registers with the interlocking machine to obtain the "main system The interlocking side communication gateway will use the data of which serial port to forward the control command, and the two CPUs (interlocking side communication gateway CPU1 and CPU2) will retain the interlocking master system flag for a cycle time and then clear it, and the standby system flag will not be processed. After the continuous cumulative T6 time, both CPUs (interlocking side communication gateway CPU1 and CPU2) are receiving the master system flag, the dual-master mode flag is set, and the interlocking side communication gateway determines that it has entered the dual-master mode. After that, the data control command forwarded by the serial port with the "master system search flag" is set to empty, and the LED light is alarmed; if the fault needs to be resolved, the interlocking side communication gateway can only be restarted to restore to normal, and the two interlocking machines will restore to the normal state of one master and one standby.

[0065] 3. Maintenance computer data reporting process:

[0066] There are two communication gateways in the interlock cabinet and each target controller (i.e., IO cabinet) corresponding to 4 NET ports, connected to 4 switches, and connected to the maintenance computer. The maintenance computer exchanges data with the IO-side communication gateway through Ethernet, and the maintenance computer target IP corresponding to each NET is different. When the maintenance computer sends the relevant command data for querying the IO execution module, no matter which NET receives the data, it will be synchronized to another CPU and sent to the IO execution module through CAN. After the IO execution module responds to the IO-side communication gateway, the IO-side communication gateway parses and packages it into Ethernet data and then uploads it to the maintenance computer; if the relevant command data of the query communication gateway itself is sent, the IO-side communication gateway will parse and package it into Ethernet data for response after receiving the data. At the same time, if the IO-side communication gateway fails, the fault code will also be synchronously packaged and uploaded. In addition to querying data, the maintenance computer can also control DIDO input and output. No matter which NET of the IO side communication gateway receives the DO control command, it will synchronize the DO control command to another CPU, and the IO side communication gateway CPU1 controls the DO output; the DI input status is detected by the IO side communication gateway CPU2, and the detected status is also synchronized to the IO side communication gateway CPU1 via SPI; when the maintenance computer queries the DIDO status no matter which NET, the IO side communication gateway will report the status.

[0067] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A computer interlocking system with a distributed communication network topology, characterized in that: It includes an indoor interlocking system and an outdoor interlocking control system, wherein the indoor interlocking system includes an interlocking machine, a control and display machine, and an interlocking side communication gateway; the outdoor interlocking control system includes multiple target controllers, each of which includes an IO side communication gateway and an IO execution module; The interlocking machine and the control and display machine are connected via Ethernet, and the interlocking machine and the interlocking side communication gateway are connected via a serial port; The interlocking side communication gateway Ethernet can be expanded to a maximum of 20 IO side nodes through external network switch equipment and passive optical fiber splitter equipment, and establish communication connections with 20 IO side communication gateways respectively; The IO side communication gateway is connected to the IO execution module through the CAN bus. The CAN bus of each IO side communication gateway supports up to 30 IO execution modules.

2. The computer interlocking system of the distributed communication network topology structure according to claim 1 is characterized in that: The indoor interlocking system also includes a maintenance computer, which is connected to the interlocking side communication gateway and the IO side communication gateway through Ethernet to share the Ethernet bus.

3. The computer interlocking system of the distributed communication network topology structure according to claim 1 is characterized in that: The interlocking machine comprises an interlocking main system and an interlocking backup system, and the interlocking main system and the interlocking backup system are redundantly arranged.

4. The computer interlocking system of the distributed communication network topology structure according to claim 1 is characterized in that: The communication gateway includes an interlocking side communication gateway and an IO side communication gateway. The communication gateway MCU has no hot reset status register, and a power-on delay circuit is added to the hardware circuit. When the MCU determines the reset flag during initialization, the output status of the power-on delay circuit is combined to determine whether the IO execution module is normally powered on and reset initialized or hot reset initialized. The power-on delay circuit shares a power supply with the MCU, starts timing and outputs a low level at the power-on moment, and the output state of the power-on delay circuit is changed to a fixed high level after a time greater than T6. The state does not change when the communication gateway module is powered on.

5. The computer interlocking system of the distributed communication network topology structure according to claim 1 is characterized in that: The interlocking machine receives the operation command from the control and display machine, and sends it to the interlocking side communication gateway according to the virtual address. The interlocking side communication gateway converts the operation command through the address mapping table, and sends it to the IO side communication gateway through the Ethernet port according to the actual module address. The IO side communication gateway then sends it to the IO execution module to control the equipment on site; The IO side communication gateway reads the data signal status of the field equipment from the IO execution module, and sends the safety data to the interlocking side communication gateway via Ethernet. The interlocking side communication gateway reports the collected data signal status to the interlocking machine, and parses the control command of the interlocking machine according to the address mapping label, recompresses it and broadcasts it to the IO side communication gateway to control the IO execution module. At the same time, the IO side communication gateway sends the non-safety data to the maintenance computer via Ethernet. The interlocking side communication gateway and the maintenance computer use the Ethernet interface to realize the fault information reporting of the interlocking side communication gateway.

6. The computer interlocking system of the distributed communication network topology structure according to claim 5 is characterized in that: The acquisition process of the address mapping table is as follows: When the number of target controllers is less than or equal to 12, the virtual communication machine address and the simulation module address are the same, and there is no mapping transformation relationship. The interlocking side communication gateway directly sends the operation command to the IO side communication gateway; when the number of target controllers is greater than 12, the distributed actual module addresses and the centralized virtual addresses are organized into an address mapping table table1 and an index table index_table1 of table1. The address mapping table table1 stores the virtual communication address, virtual module address, target controller address and actual module address of the device; The converted virtual communication machine address and virtual module address are written into the interlocking system configuration data. The interlocking machine reads the interlocking system configuration data, and sends the address mapping table table1 and the index table index_table1 of table1 to the interlocking side communication gateway through the serial port after compression during the registration process; The interlocking side communication gateway obtains the virtual address through the actual module address according to the address mapping table table1 and the index table index_table1, or obtains the actual module address through the virtual address according to the address mapping table table1 and the index table index_table1.

7. The computer interlocking system of the distributed communication network topology structure according to claim 6 is characterized in that: RS422-1 and RS422-2 of the interlocking side communication gateway are connected to the interlocking machine main system and interlocking machine standby system respectively. RS422-1 data is forwarded through Ethernet NET1, and RS422-2 data is forwarded through Ethernet NET2. The Ethernet NET1 and NET2 of the interlocking side communication gateway and the Ethernet NET1 and NET2 of the IO side communication gateway are connected using the Ethernet communication protocol; The communication gateway on the interlocking side packages the message sent by the interlocking machine and broadcasts it to 20 target controllers; after receiving the response data from the 20 nodes of the target controller, it composes up to 12 virtual communication machine messages and forwards them to the interlocking machine.

8. The computer interlocking system of the distributed communication network topology structure according to claim 7 is characterized in that: The data transmission process of the interlocking side communication gateway is as follows: When any RS422 serial port of the interlocking communication gateway receives data, the interlocking communication gateway CPU1 processes the data of RS422_1, and the interlocking communication gateway CPU2 processes the data of RS422_2. Both CPUs are synchronized through SPI and are controlled by the interlocking communication gateway CPU1. When the interlocking side communication gateway RS422-1 receives the data from the interlocking machine, it passes the received data to the interlocking side communication gateway CPU2 through SPI, and the interlocking side communication gateway CPU2 verifies the signature CRC of the received data, prepares the response data and calculates the signature CRC of the response data. The interlocking side communication gateway CPU1 requests the signature CRC calculation result and the signature CRC of the response data from the interlocking side communication gateway CPU2; When the interlocking side communication gateway RS422-2 receives the data from the interlocking machine, it passes the data to the interlocking side communication gateway CPU1 through SPI, and the interlocking side communication gateway CPU1 verifies the transmission CRC of the received data, prepares the response data and calculates the transmission CRC of the response data. The interlocking side communication gateway CPU2 requests the interlocking side communication gateway CPU1 to transmit the CRC calculation result and the transmission CRC of the response data; When receiving RS422 data with the virtual communication machine address of 1, the timer of T1 time is started. After T1 time, it is considered that the data reception is completed, and the interlocking machine ends the search in this cycle; After RS422 data reception is completed, the signature CRC sent by Ethernet is obtained first, and the broadcast packet is sent, and finally the non-safe data is sent; After receiving the RS422 data, the interlocking communication gateway RS422-1 starts the T2 timer. When the T2 time is exceeded, Ethernet parsing is performed to prepare to fill in the broadcast data sent to the IO communication gateway. The interlocking communication gateway CPU1 requests the signature CRC of the NET1 broadcast data from the interlocking communication gateway CPU2, and then sends it out through NET1 after the broadcast data is filled. After receiving the RS422 data, the interlocking side communication gateway RS422-2 starts the T2 timer. When the T2 time is exceeded, Ethernet parsing is performed to start preparing to fill in the broadcast data of NET2 sent to the IO side communication gateway. The interlocking side communication gateway CPU2 requests the transmission CRC of the NET2 broadcast data from the interlocking side communication gateway CPU1, and then sends it out through NET2 after the broadcast data is filled.

9. The computer interlocking system of the distributed communication network topology structure according to claim 7 is characterized in that: The data transmission process of the IO side communication gateway is as follows: When any NET network port of the IO side communication gateway receives data, the IO side communication gateway CPU1 processes the data of NET1, and the IO side communication gateway CPU2 processes the data of NET2. Both CPUs are synchronized through SPI and are controlled by CPU1. The IO side communication gateway CPU1 transmits the data received by the NET1 network port to the IO side communication gateway CPU2, which verifies the signature CRC, prepares the response data, and calculates the signature CRC of the response data. The IO side communication gateway CPU1 requests the IO side communication gateway CPU2 for the signature CRC calculation result and the signature CRC of the response data. The IO side communication gateway CPU2 transmits the data received by the NET2 network port to the IO side communication gateway CPU1, which verifies the transmission CRC, prepares the response data and calculates the transmission CRC of the response data. The IO side communication gateway CPU2 requests the IO side communication gateway CPU1 to transmit the CRC calculation result and the transmission CRC of the response data. The IO side communication gateway CPU1 sends a CAN search flag to the IO side communication gateway CPU2 via SPI, so that the IO side communication gateway CPU2 starts the CAN search; If the IO side communication gateway receives data forwarded by the main system interlocking machine, it will immediately search for the main system. If it receives data forwarded by the standby system interlocking machine and Ethernet registration is completed, it will wait for T4 time. If there is no main system search within T4 time, it will search for the standby system. If there is a main system search, it will execute the main system search. When CAN registration is successful, the device information reported by the IO execution module is compressed and packaged by the IO side communication gateway and uploaded to the interlocking side communication gateway. Before CAN registration is completed, the device information sent to the Ethernet data is empty.

10. The computer interlocking system of the distributed communication network topology structure according to claim 7, characterized in that: The process of reporting maintenance computer data is as follows: The maintenance computer exchanges data with the IO side communication gateway via Ethernet, and the maintenance computer target IP corresponding to each NET is different; When the maintenance computer sends the relevant command data for querying the IO execution module, NET1 or NET2 receives the data and sends it to another CPU through synchronization. The IO side communication gateway sends it to the IO execution module through CAN. After the IO execution module responds to the IO side communication gateway, the IO side communication gateway parses and packages it into Ethernet data and then uploads it to the maintenance computer. When the maintenance computer sends out query command data related to the IO side communication gateway itself, the IO side communication gateway receives the data, parses it and packages it into Ethernet data for response. At the same time, if the IO side communication gateway fails, the fault code is synchronously packaged and uploaded; In addition to querying data, the maintenance computer is also used to control DIDO input and output. After NET1 or NET2 receives the DO control command, it will synchronize the DO control command to another CPU, and the IO side communication gateway CPU1 controls the DO output; the DI input status is detected by the IO side communication gateway CPU2, and the detected status is also synchronized to the IO side communication gateway CPU1 via SPI; when the maintenance computer queries the DIDO status through NET1 or NET2, the IO side communication gateway will report the data.

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