Silicon carbide MOSFET layout structure for improving high-frequency performance and manufacturing method

Abstract

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) cellular structure for improving high-frequency performance, the silicon carbide MOSFET cellular structure comprises four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are arranged in order to form a square, and channels with equal distance are arranged between every two square silicon carbide MOSFET cells; the center of the square is provided with a cross-shaped JFET region; a cross-shaped JFET region is arranged on the four square silicon carbide MOSFET cells, a P + region is arranged on the cross-shaped JFET region, the P + region covers channel regions at the corners of the four square silicon carbide MOSFET cells, the P + region is of a split gate structure, and gates of other regions in the square are of a traditional gate structure. The periodic array of the silicon carbide MOSFET cellular structure forms a silicon carbide MOSFET layout structure capable of improving high-frequency performance. The invention further provides a manufacturing method of the MOSFET layout structure. According to the invention, the problem that the on resistance and the Cgd capacitance of the existing device are too large is solved.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor technology, and in particular to a silicon carbide MOSFET layout structure and a manufacturing method for improving high-frequency performance. Background Art

[0002] Power metal oxide field effect transistors (MOSFETs) can carry large currents in the on state and withstand large breakdown voltages in the off state. The current between the source and drain regions in the semiconductor substrate is controlled by a voltage applied to the gate, which is isolated from the semiconductor surface by an insulator (usually silicon dioxide). For example, in an n-type enhancement MOSFET, a positive bias on the gate causes a surface inversion layer or channel to form in the p-type region under the gate oxide, forming a conductive path between the source and drain. Current is generated between the positive drain and source. Over the years, lateral and vertical power MOSFET structures in silicon have been explored, with the former having the drain, gate, and source on the same surface of the silicon wafer and the latter having the source and drain on opposite surfaces of the silicon wafer. Several different types of vertical power MOSFETs have been proposed, including DMOSFET and UMOSFET.

[0003] The structures of DMOSFET and UMOSFET are still valid for SiC MOSFET. The D in DMOSFET refers to double-implanted MOSFET in SiC MOSFET. The P base region and N+ source region are produced by ion implantation rather than thermal diffusion. Because the diffusion coefficient of impurities in SiC is very low, it is not practical to apply diffusion process in SiC. SiC is the third generation of wide bandgap semiconductor material. Compared with Si-based MOSFET, SiC-based MOSFET has higher breakdown voltage, lower on-resistance and lower conduction loss. In the field of power devices, the market share of SiC power devices is increasing year by year.

[0004] Despite this, the potential advantages of silicon carbide as a power MOSFET have not yet been fully realized. There are still problems with excessive on-resistance and capacitance, which lead to reduced switching speed and increased conduction loss of the device. The traditional linear layout structure has low channel density and high on-resistance, while the square, hexagonal, and octagonal cell layout structures have high channel density and low on-resistance. However, the size of the square, hexagonal, and octagonal cells cannot be very small due to structural limitations. For device reliability, each individual cell must have a P+ region to ground the P-well region of the cell. This results in the resistance performance of square, hexagonal, and octagonal cells having no obvious advantages over compact linear cells, and the capacitance Cgd will be even larger. Therefore, it is necessary to propose a MOSFET layout with low on-resistance and low capacitance Cgd to optimize the performance of silicon carbide MOSFETs. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a silicon carbide MOSFET layout structure and a manufacturing method for improving high-frequency performance, which is used to solve the problem of excessive device on-resistance and device capacitance Cgd in the prior art while ensuring a high breakdown voltage. The silicon carbide power MOSFET has a higher channel density and can achieve a smaller cell size under the same process technology. Part of the gate adopts a split gate design, which reduces the capacitance of the device and improves the switching speed of the device. Compared with traditional MOSFET, the present invention does not require additional process steps.

[0006] To solve the above technical problems, the first implementation scheme provided by the present invention is to provide a silicon carbide MOSFET cell structure for improving high-frequency performance, including: four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are neatly arranged into a square cell structure, and there are channels with equal distances between every two square silicon carbide MOSFET cells; a cross-shaped JFET region is provided at the center of the square cell structure; a P+ region is provided on the cross-shaped JFET region, the P+ region covers the channel region at the corners of the four square silicon carbide MOSFET cells, the P+ region is a split gate structure, so that the exposed P+ region is used to make a source electrode, the gate of other areas in the square is a traditional gate structure, and the P+ region forms a reverse biased PN junction with the cross-shaped JFET region to shield the high gate oxide layer electric field at the corners of the split gate structure and the corners of the square cell structure.

[0007] Preferably, the square silicon carbide MOSFET cell includes a substrate, an epitaxial layer and a CSL layer from bottom to top, a first hard mask layer is provided on the CSL layer, a P-well region injection window is etched on the first hard mask layer, and ions in the P-well region are injected into the P-well region injection window to obtain the P-well region, and a gate oxide layer, a gate polysilicon and a dielectric layer are symmetrically provided on the P-well region and the CSL layer from bottom to top along the axis, an N+ region and an ohmic contact metal layer are provided in the P-well region from bottom to top, the N+ region is provided below the two gate oxide layers, the ohmic contact metal layer is provided between the two gate oxide layers, a source metal layer is provided on the ohmic contact metal layer and the dielectric layer, and the P+ region covers the upper layer of the P-well region.

[0008] Preferably, the split gate structure surrounds the P+ region, mainly to expose the P+ region for source contact.

[0009] The second implementation scheme provided by the present invention is to provide a silicon carbide MOSFET layout structure composed of a silicon carbide MOSFET cell structure for improving high-frequency performance. The silicon carbide MOSFET layout structure is composed of a plurality of silicon carbide MOSFET cell structures periodically arrayed along the X direction and the Y direction.

[0010] Preferably, a plurality of silicon carbide MOSFET cell structures for improving high frequency performance are arranged in a periodic matrix.

[0011] The third implementation scheme provided by the present invention is to provide a method for manufacturing a silicon carbide MOSFET layout structure for improving high-frequency performance, comprising the following steps: An epitaxial layer and a CSL layer are grown from bottom to top on a substrate, wherein the epitaxial layer is an n-type epitaxial layer, the CSL layer is an n-type CSL layer, and the substrate is an n-type silicon carbide substrate, or after growing a uniformly doped epitaxial layer on the substrate, ion implantation is performed to generate a CSL layer; A first hard mask layer is formed on the CSL layer, and the first hard mask layer is etched using a mask plate to expose a P-well region injection window on the first hard mask layer; P-well region ions are injected into the P-well region injection window to form a P-well region; Depositing a dielectric silicon nitride layer on the first hard mask layer, and performing carpet etching to the same thickness to form a dielectric silicon nitride spacer layer on the sidewall of the first hard mask layer, wherein the dielectric silicon nitride spacer layer is used to realize a self-aligned channel of a MOSFET cell and to form an N+ region; The dielectric silicon nitride spacer layer and the first hard mask layer are removed, and a second hard mask layer is formed, and a mask is used to etch a P+ region window; p-type ion implantation is performed to form a P+ region, and the second hard mask layer is removed after the implantation is completed; Next, a cap layer composed of carbon is deposited, and a high-temperature thermal annealing is performed in an inert gas atmosphere to activate the implanted ions; after the annealing is completed, the cap layer is removed; Next, the subsequent production is carried out through the standard MOSFET production process; first, the surface of the wafer obtained above is cleaned; then, a gate oxide layer is formed by thermally oxidizing silicon carbide and annealing; a layer of gate polysilicon is deposited on the gate oxide layer, and the gate area is etched out using a mask; then a dielectric layer is deposited on the gate area of ​​the gate polysilicon, and a window in the source area is etched out using a mask, and an ohmic contact metal layer is sputtered and high-temperature thermal annealing is performed to form an ohmic contact between the ohmic contact metal layer, the N+ area, and the P+ area; the source metal is evaporated and the source area is etched out using a mask; then, back-side scribing, cleaning, and substrate thinning processes are performed, and ohmic contact metal and drain metal (the drain metal is the drain electrode) are formed on the back side.

[0012] Preferably, the substrate is a 4H-SiC n-type heavily doped low-resistivity substrate, the resistivity of the substrate is 0.015Ω·cm~0.025Ω·cm; the doping concentration of the n-type epitaxial layer is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of the CSL layer is 1×10 16 cm -3 ~1×10 17 cm -3 The use of the n-type heavily doped low resistivity substrate and the CSL layer here is to reduce the on-resistance of the device.

[0013] Preferably, the high temperature annealing is performed in an inert gas atmosphere, wherein the inert gas is nitrogen or argon; the temperature of the high temperature thermal annealing is between 1500°C and 1900°C, and the time of the high temperature thermal annealing is between 8 minutes and 15 minutes. The appropriate annealing temperature can increase the activation rate of the injected ions, mainly the activation rate of the P-type doped ions in the P-well region. A high P-well concentration can increase the breakdown voltage of the device.

[0014] Preferably, the ions used to make the P-well region are aluminum ions, and the doping concentration of the P-well region is 1×10 18 cm -3 ~3×10 18 cm -3 In order to avoid the threshold voltage being too high, the P-well region adopts a reverse doping distribution, with low surface doping concentration and high doping concentration deep below; the doping concentration in the channel region is 7×10 16 cm -3~ p-type doping 5×10 16 cm -3 The peak doping concentration is greater than 1×10 18 cm -3 The reverse doping distribution can reduce the channel resistance of the device while ensuring the breakdown voltage of the device, thereby reducing the overall on-resistance of the device.

[0015] Preferably, the ions used to make the N+ region are nitrogen ions; the peak concentration of the N+ region should be 1×10 19 cm -3 The thickness of the dielectric silicon nitride spacer does not exceed 0.5 μm. The doping concentration of the N+ region should be as high as possible to reduce the on-resistance of the N+ region. The thickness of the dielectric silicon nitride will affect the length of the channel. If the channel length is too long, the channel resistance will increase, which will in turn increase the on-resistance of the device.

[0016] Compared with the prior art, the present invention has the following beneficial effects: In order to solve the problem of excessive on-resistance and capacitance Cgd of silicon carbide power MOSFET, the present invention proposes a compact square cell structure design, in which the P+ region is set to the cross-shaped JFET region of the square cell structure, so that a smaller MOSFET cell structure can be produced under the same process conditions.

[0017] The present invention reduces the on-resistance and capacitance Cgd of the silicon carbide power MOSFET without adding process steps. Part of the gate adopts a split gate design, which reduces the capacitance of the device and improves the switching speed of the device. In addition, the P+ region can also shield the high electric field on the gate oxide layer in the JFET region, ensuring the reliability of the silicon carbide power MOSFET device.

[0018] In the present invention, the square silicon carbide MOSFET cell structure improves the channel density and reduces the on-resistance of the silicon carbide MOSFET device. The P+ region is set at the cross-shaped JFET region, which can achieve a smaller cell size under the same process conditions, improve the current density of the MOSFET device, and then reduce the on-resistance of the MOSFET device. At the same time, the P+ region provided by the present invention shields the gate oxide layer in the JFET region and the high electric field at the corner of the square cell, avoiding the premature breakdown of the MOSFET device and improving the reliability of the MOSFET device. In addition, the present invention does not add additional process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of a semiconductor device cell layout formed by a method according to an embodiment of the present invention.

[0020] Figure 2 The chip structure formed according to the method of the embodiment is along Figure 1 Cross-sectional view of section AA'.

[0021] Figure 3 The chip structure formed according to the method of the embodiment is along Figure 1 Cross-section of BB'.

[0022] Figure 4 It is a schematic cross-sectional view of the substrate, epitaxial layer and CSL layer.

[0023] Figure 5 is a schematic cross-sectional view of a semiconductor device after a P-well region is formed according to a method of an embodiment.

[0024] Figure 6 is a schematic cross-sectional view of a semiconductor device after an N+ region is formed according to a method of an embodiment.

[0025] Figure 7 The semiconductor device after forming the P+ region according to the method of the embodiment Figure 1 Schematic diagram of the cross section of AA'.

[0026] Description of reference numerals: 1. Substrate; 2. Epitaxial layer; 3. CSL layer; 4. First hard mask layer; 5. P-well region injection window; 6. P-well region; 7. Dielectric silicon nitride spacer layer; 8. N+ region; 9. Second hard mask layer; 10. P+ region injection window; 11. P+ region; 12. Gate oxide layer; 13. Gate polysilicon; 14. Dielectric layer; 15. Ohmic contact metal layer; 16. Source metal layer. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0029] Figure 1 The layout structure of a silicon carbide power MOSFET manufactured according to the manufacturing method given by the present invention is shown. Figure 2 and Figure 3 The cross-sectional views of the silicon carbide MOSFET cell structures formed according to the manufacturing method of the present invention are respectively shown. Figures 4 to 7 The various steps of the manufacturing process of the MOSFET cell structure provided by the present invention are described.

[0030] The inventors found that in the layout structure design of silicon carbide MOSFET, the square cell has a higher channel density than the linear cell, and therefore has a lower channel resistance, which can achieve a lower on-resistance. However, due to the large electric field on the gate oxide layer at the corners of the square cell and in the center of the JFET area, the device will break down prematurely. Providing a P+ shielding area at the corner can shield the large electric field at the corner. The split gate design can reduce the overlapping area between the gate and the drain, greatly reduce the capacitance Cgd, and remove part of the oxide layer in the center of the JFET area to avoid a large electric field.

[0031] In view of this, the present invention provides a silicon carbide MOSFET layout structure and a manufacturing method for improving high-frequency performance, which is used to solve the problem of excessive on-resistance and Cgd capacitance of the device in the prior art under the premise of ensuring the reverse withstand voltage of the device. The silicon carbide power MOSFET has a higher channel density and can achieve a smaller cell size under the same process technology. Part of the gate adopts a split gate design, which reduces the capacitance of the device and improves the switching speed of the device. Compared with traditional MOSFET, the present invention does not require additional process steps.

[0032] Example 1 like Figure 1 A silicon carbide MOSFET cell structure for improving high-frequency performance is shown, which can improve high-frequency performance. The silicon carbide MOSFET cell structure for improving high-frequency performance includes: four square silicon carbide MOSFET cells, the four square silicon carbide MOSFET cells are neatly arranged into a square cell structure, and there are channels with equal distances between every two square silicon carbide MOSFET cells; a cross-shaped JFET region is provided at the center of the square cell structure; a P+ region is provided on the cross-shaped JFET region, and the P+ region covers the channel region at the corners of the four square silicon carbide MOSFET cells, the P+ region is a split gate structure, so that the exposed P+ region is used to make a source electrode, and the gates of other regions in the square cell are traditional gate structures, and the P+ region forms a reverse biased PN junction with the cross-shaped JFET region to shield the high gate oxide layer electric field at the corners of the split gate structure and the corners of the square cell structure.

[0033] The present invention aims at the problem that the on-resistance and capacitance Cgd of silicon carbide power MOSFET are too large, and proposes a compact square cell structure design. The P+ region is set to the cross-shaped JFET region of the square cell structure, and a smaller MOSFET cell structure can be produced under the same process conditions, thereby increasing the current density of the MOSFET device and reducing the on-resistance of the MOSFET device. The present invention reduces the on-resistance and capacitance Cgd of the silicon carbide power MOSFET without adding process steps. In addition, the P+ region can also simultaneously shield the high electric field on the gate oxide layer in the JFET region, thereby ensuring the reliability of the silicon carbide power MOSFET device.

[0034] In order to solve the problem of high electric field in the JFET area at the corner of the existing square cell structure, the present invention places the P+ area at the corner to shield the high electric field in the JFET area and ensure the breakdown voltage of the device. And after removing the P+ area from the square cell structure, the size of the square cell structure can be made smaller, and the current density of the device will become larger. The structure of the square silicon carbide MOSFET cell is as follows: Figure 2As shown, the square silicon carbide MOSFET cell structure includes a substrate 1, an epitaxial layer 2 and a CSL layer 3 from bottom to top, a first hard mask layer 4 is provided on the upper layer of the CSL layer 3, a P-well region injection window 5 is etched on the first hard mask layer 4, and the P-well region injection window 5 injects P-well region ions to obtain a P-well region 6, and a gate oxide layer 12, a gate polysilicon 13 and a dielectric layer 14 are symmetrically provided on the P-well region 6 and the CSL layer 3 along the axis from bottom to top, and an N+ region 8 and an ohmic contact metal layer 15 are provided in the P-well region 6 from bottom to top, the N+ region 8 is provided below the two gate oxide layers 12, the ohmic contact metal layer 15 is provided between the two gate oxide layers 12, a source metal layer 16 is provided on the ohmic contact metal layer 15 and the dielectric layer 14, and the P+ region covers the upper layer of the P-well region 6.

[0035] like Figure 3 As shown, the split gate surrounds the P+ region 11. This is mainly to expose the P+ region for source contact.

[0036] The SiC MOSFET layout structure for improving high-frequency performance is formed by a SiC MOSFET cell structure that improves high-frequency performance, and is composed of a plurality of SiC MOSFET cell structures that are periodically arrayed along the X direction and the Y direction.

[0037] Specifically, a plurality of silicon carbide MOSFET cell structures for improving high frequency performance are arranged in a periodic matrix.

[0038] Example 2 A method for manufacturing a silicon carbide MOSFET layout structure for improving high frequency performance comprises the following steps: like Figure 4 As shown, an epitaxial layer 2 and a CSL layer 3 are grown from bottom to top on a substrate 1, wherein the epitaxial layer 2 is an n-type epitaxial layer 2, the CSL layer 3 is an n-type CSL layer 3, and the substrate 1 is an n-type silicon carbide substrate, or after a uniformly doped epitaxial layer 2 is grown on the substrate 1, ion implantation is performed to generate the CSL layer 3.

[0039] like Figure 5 As shown, a first hard mask layer 4 is formed on the CSL layer 3, and the first hard mask layer 4 is etched using a mask to expose a P-well region injection window 5 on the first hard mask layer 4; P-well region ions (the P-well region ions are aluminum ions) are injected into the P-well region injection window 5 to form a P-well region 6, and the P-well region injection window 5 is etched to the ion injection blocking layer.

[0040] The composition of the first hard mask layer 4 from bottom to top includes the following options: An ion implantation barrier layer (e.g., a silicon dioxide layer), an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum).

[0041] The P-well region implantation window 5 only needs to be etched to the ion implantation blocking layer of the first hard mask layer 4 .

[0042] like Figure 6 As shown, a dielectric silicon nitride layer is deposited on the side wall of the first hard mask layer 4, and carpet etching of the same thickness is performed to form a dielectric silicon nitride spacer 7 on the side wall of the first hard mask layer 4. The dielectric silicon nitride spacer 7 is used to realize the self-aligned channel of the MOSFET cell and to produce the N+ region 8.

[0043] The dielectric silicon nitride spacer layer 7 and the first hard mask layer 4 are removed, and a second hard mask layer 9 is formed, and a mask is used to etch a P+ region injection window 10; p-type ion implantation is performed to form a P+ region 11, and the second hard mask layer 9 is removed after the implantation is completed; like Figure 7 As shown, a cap layer composed of carbon is then deposited, and high-temperature thermal annealing is performed in an inert gas atmosphere to activate the implanted ions; after the annealing is completed, the cap layer is removed.

[0044] The second hard mask layer 9 has the following composition from bottom to top: An ion implantation barrier layer (e.g., a silicon dioxide layer), an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), or an ion implantation barrier layer (e.g., a silicon dioxide layer), a polysilicon layer, an oxide layer (e.g., a silicon dioxide layer), a metal layer (e.g., nickel, titanium, gold, copper, chromium, aluminum).

[0045] like Figure 2 and Figure 3As shown, the subsequent manufacturing is carried out through the standard MOSFET manufacturing process; first, the surface of the wafer obtained above is cleaned; then, a gate oxide layer 12 is formed by thermally oxidizing silicon carbide and annealing; a layer of gate polysilicon 13 is deposited on the gate oxide layer 12, and a gate region is etched out using a mask; then, a layer of dielectric layer 14 is deposited on the gate region of the gate polysilicon 13, and a window of the source region is etched out using a mask, and an ohmic contact metal layer 15 is sputtered and a rapid high-temperature thermal annealing is performed to form an ohmic contact between the ohmic contact metal layer 15, the N+ region 8 and the P+ region 11; the source metal is evaporated and the source region is etched out using a mask; then, back-side scribing, cleaning and substrate thinning processes are performed, and ohmic contact metal and drain metal (the drain metal is a drain electrode) are formed on the back side.

[0046] The ohmic contact metal layer 15 may be made of nickel, titanium, tungsten, tantalum, molybdenum, aluminum or alloys thereof; the source metal layer 16 may be made of aluminum.

[0047] Specifically, the substrate 1 is a 4H-SiC n-type heavily doped low resistivity substrate, the resistivity of the substrate 1 is 0.015Ω·cm~0.025Ω·cm; the n-type epitaxial layer is lightly doped, and the doping concentration of the n-type epitaxial layer is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of CSL layer 3 is 1×10 16 cm -3 ~1×10 17 cm -3 .

[0048] Specifically, the high temperature annealing is performed in an inert gas atmosphere, wherein the inert gas is nitrogen or argon; the temperature of the high temperature thermal annealing is between 1500° C. and 1900° C., and the time of the high temperature thermal annealing is between 8 minutes and 15 minutes.

[0049] Specifically, the ions used to make the P-well region 6 are aluminum ions, and the doping concentration of the P-well region 6 is 1×10 18 cm -3 ~3×10 18 cm -3 ; The doping concentration at this order of magnitude is high enough so that the potential barrier at the source end of the channel will not be reduced by the voltage applied to the drain. In order to avoid the threshold voltage being too high, the P-well region 6 adopts a reverse doping distribution, with a low surface doping concentration and a high doping concentration deep below; because silicon carbide is a wide bandgap semiconductor material, it has a larger PN junction built-in electric field. Silicon carbide can be used to make normally-off accumulation channel MOSFETs. Therefore, the doping concentration in the channel region is 2×10 16 cm -3~ p-type doping 5×1016 cm -3 between.

[0050] The ions used to make the N+ region 8 are nitrogen ions; the peak concentration of the N+ region 8 should be 1×10 19 cm -3 The thickness of the dielectric silicon nitride spacer layer 7 does not exceed 0.5 μm to form a shorter channel of no more than 0.5 μm, thereby reducing the resistance of the channel region and thereby reducing the on-resistance of the device.

[0051] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A silicon carbide MOSFET cell structure for improving high frequency performance, characterized in that: include: Four square silicon carbide MOSFET cells are neatly arranged into a square cell structure, and channels with equal distances are provided between every two of the square silicon carbide MOSFET cells; a cross-shaped JFET region is provided at the center of the square cell structure; a P+ region (11) is provided on the cross-shaped JFET region, the P+ region (11) covers the channel regions at the corners of the four square silicon carbide MOSFET cells, the P+ region (11) is a split gate structure, so that the exposed P+ region (11) is used to make a source electrode, and the P+ region (11) forms a reverse biased PN junction with the cross-shaped JFET region to shield the high gate oxide layer electric field at the corners of the split gate structure and the square cell structure.

2. A silicon carbide MOSFET cell structure for improving high frequency performance according to claim 1, characterized in that: The square silicon carbide MOSFET cell comprises, from bottom to top, a substrate (1), an epitaxial layer (2) and a CSL layer (3); a first hard mask layer (4) is provided on the upper layer of the CSL layer (3); a P-well region injection window (5) is etched on the first hard mask layer (4); ions of the P-well region are injected into the P-well region injection window (5) to obtain a P-well region (6); and a gate oxide layer (12), a gate multilayer (13) and a gate oxide layer (14) are symmetrically provided on the P-well region (6) and the CSL layer (3) along an axis from bottom to top. Crystalline silicon (13) and a dielectric layer (14); an N+ region (8) and an ohmic contact metal layer (15) are arranged from bottom to top in the P-well region (6); the N+ region (8) is arranged below two gate oxide layers (12); the ohmic contact metal layer (15) is arranged between the two gate oxide layers (12); a source metal layer (16) is arranged above the ohmic contact metal layer (15) and the dielectric layer (14); and the P+ region (11) covers the upper layer of the P-well region (6).

3. The silicon carbide MOSFET cell structure for improving high frequency performance according to claim 1, characterized in that: The split gate structure surrounds the P+ region (11).

4. The silicon carbide MOSFET layout structure for improving high frequency performance formed by the silicon carbide MOSFET cell structure for improving high frequency performance as claimed in claim 3, characterized in that: The silicon carbide MOSFET layout structure is formed by a periodic array of multiple silicon carbide MOSFET cell structures along the X direction and the Y direction.

5. The silicon carbide MOSFET layout structure for improving high frequency performance according to claim 4, characterized in that: A plurality of the silicon carbide MOSFET cell structures are arranged in a periodic matrix.

6. The method for manufacturing a silicon carbide MOSFET layout structure for improving high frequency performance according to claim 5, characterized in that: The steps include: Growing an epitaxial layer (2) and a CSL layer (3) from bottom to top on a substrate (1), wherein the epitaxial layer (2) and the CSL layer (3) are both n-type, and the substrate (1) is an n-type silicon carbide substrate, or after growing a uniformly doped epitaxial layer (2) on the substrate (1), ion implantation is performed to generate the CSL layer (3); Performing multiple ion implantations on the CSL layer (3) to generate a P-well region (6), an N+ region (8), and a P+ region (11); performing high temperature thermal annealing in an inert gas atmosphere to activate the implanted ions; An isolation gate region is prepared on the CSL layer (3) by a standard MOSFET process, wherein the isolation gate region comprises a gate oxide layer (12) and a gate polysilicon (13) arranged from bottom to top, a dielectric layer (14) is deposited on the gate polysilicon (13), an ohmic contact metal layer (15) is sputtered between two adjacent dielectric layers (14) to form an ohmic contact metal layer (15) with the N+ region (8) and the P+ region (11), and a source metal layer (16) is formed between the dielectric layer (14) and the ohmic contact metal layer (15) by evaporating a source metal for connection; A drain metal is deposited beneath the n-type silicon carbide substrate.

7. The method according to claim 6, characterized in that: The substrate (1) is a 4H-SiC n-type heavily doped low-resistivity substrate, and the resistivity of the substrate (1) is 0.015Ω·cm~0.025Ω·cm; the doping concentration of the n-type epitaxial layer is 1×10 15 cm -3 ~3×10 16 cm -3 ; The doping concentration of the CSL layer (3) is 1×10 16 cm -3 ~1×10 17 cm -3 .

8. The method according to claim 6, characterized in that: The inert gas is nitrogen or argon; the temperature of the high temperature thermal annealing is 1500° C. to 1900° C., and the time of the high temperature thermal annealing is 8 minutes to 15 minutes.

9. The method according to claim 6, characterized in that: The ions used to make the P-well region (6) are aluminum ions, and the doping concentration of the P-well region (6) is 1×10 18 cm -3 ~3×10 18 cm -3 To avoid excessively high threshold voltage, the P-well region (6) adopts reverse doping distribution, with low surface doping concentration and high doping concentration deep below. The doping concentration of the channel region is 2×10 16 cm -3~ p-type doping 5×10 16 cm -3 between.

10. The method according to claim 6, characterized in that: The ions used to make the N+ region (8) are nitrogen ions; the peak concentration of the N+ region (8) should be 1×10 19 cm -3 above.

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