A latch and flip-flop resistant to single event upsets in digital circuits

Abstract

The application discloses a latch and a flip-flop resisting single event upset in a digital circuit, and relates to the technical field of digital integrated circuit design, to solve the problem that the prior art cannot resist single event upset of multiple nodes in the latch structure of a digital circuit. The latch comprises at least a basic latch, a transmission gate and a detection circuit which are connected with each other. The latch uses a detection signal of the detection circuit to judge the level upset state of the basic latch, and generates a control signal for controlling the output of the latch based on the level upset state of the basic latch. Further, a plurality of the above latch structures can be used to form a flip-flop. Thus, the latch and the flip-flop can be restored to the correct level after being subjected to multi-node single event upset, and the resistance of the latch and the flip-flop to single event radiation effects is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital integrated circuit design, and in particular to a latch and flip-flop resisting single event upset in a digital circuit. BACKGROUND

[0002] When a high-energy particle is incident into a semiconductor device, it will deposit energy through direct ionization and indirect ionization, and finally cause the ionization of atoms in the material to generate electron-hole pairs. Part of the charge is collected by the sensitive nodes of the device under the action of the electric field, such as the off MOS tube drain, thereby causing the logic state of the device to change, causing single event upset. In order to alleviate the impact of single event upset on digital circuit chips, the digital circuit needs to be hardened against radiation.

[0003] With the miniaturization of semiconductor device process feature size, node capacitance and power voltage are decreasing, making single event upset more likely to occur. Due to the reduction of node spacing caused by size miniaturization, on the one hand, the charge sharing effect is intensified, and on the other hand, the probability of adjacent nodes being hit by a single particle at the same time increases, making it more likely to occur multiple node single event upset, thus posing a great challenge to the hardening of advanced processes. In the prior art, the traditional latch hardening scheme is to harden the master-slave latch of the flip-flop, which has good resistance to single node upset. However, with the advancement of semiconductor processes, the shortening of node spacing makes the charge sharing effect more pronounced, and it is very easy to cause multiple nodes in the latch structure of the latch circuit to flip at the same time. The traditional latch hardening scheme cannot resist multiple node upset at the same time; and the interlocking structure increases the circuit delay and reduces the circuit speed.

[0004] Therefore, there is an urgent need to design a technical solution that can resist multiple nodes in the latch structure from flipping at the same time in the circuit, in order to solve the problem that the prior art cannot resist single event upset of multiple nodes in the latch structure of the digital circuit. SUMMARY

[0005] The present application aims to provide a latch and flip-flop resisting single event upset in a digital circuit, which designs a detection circuit independent of the latch structure. The latch uses the detection circuit to determine whether single event upset occurs in the basic latch circuit, and generates a control signal for controlling the output of the latch circuit based on the detection signal of the detection circuit, thereby realizing that the memory structure of the latch can recover to the correct level after being hit by multiple node single particles; solving the problem that the prior art cannot resist single event upset of multiple nodes in the latch structure of the digital circuit.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a latch for resisting single event upset in a digital circuit, the latch comprising at least a basic latch, a transmission gate and a detection circuit.

[0008] An input terminal of the basic latch is connected to an input terminal of the latch, an output terminal of the basic latch is connected to an input terminal of the transmission gate, an output terminal of the transmission gate is connected to an output terminal of the latch, an input terminal of the detection circuit is connected to the basic latch, and an output terminal of the detection circuit is connected to the transmission gate.

[0009] The latch uses a detection signal of the detection circuit to determine a level upset state of the basic latch, and generates a control signal for controlling an output of the latch based on the level upset state of the basic latch.

[0010] Preferably, the detection circuit comprises a first detection circuit, and the first detection circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor.

[0011] A drain of the seventh PMOS transistor is connected to a third signal terminal, a gate of the seventh PMOS transistor is connected to a clock inverse signal terminal, and a source of the seventh PMOS transistor is connected to a drain of the eighth PMOS transistor; a gate of the eighth PMOS transistor is connected to a first signal terminal, a source of the eighth PMOS transistor is connected to a drain of the ninth PMOS transistor; a gate of the ninth PMOS transistor is connected to the clock inverse signal terminal, a source of the ninth PMOS transistor is connected to a power supply terminal, and a drain of the ninth PMOS transistor is connected to a seventh signal terminal; a gate of the tenth PMOS transistor is connected to a clock signal terminal, a source of the tenth PMOS transistor is connected to the power supply terminal, and a drain of the tenth PMOS transistor is connected to a drain of the eleventh PMOS transistor and a fourth signal terminal; a gate of the eleventh PMOS transistor is connected to the first signal terminal; a drain of the twelfth PMOS transistor is connected to the fourth signal terminal, and a gate of the twelfth PMOS transistor is connected to the seventh signal terminal; a gate of the thirteenth PMOS transistor is connected to the fourth signal terminal, a source of the thirteenth PMOS transistor is connected to the power supply terminal, and a drain of the thirteenth PMOS transistor is connected to a fifth signal terminal.

[0012] The drain of the seventh NMOS tube is connected with the third signal end, the gate of the seventh NMOS tube is connected with the clock signal end, and the source of the seventh NMOS tube is connected with the source of the seventh PMOS tube; the drain of the eighth NMOS tube is connected with the drain of the eighth PMOS tube, the gate of the eighth NMOS tube is connected with the first signal end, and the source of the eighth NMOS tube is connected with the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is connected with the clock signal end, the gate of the ninth NMOS tube is grounded, and the drain of the ninth NMOS tube is connected with the sixth signal end; the gate of the tenth NMOS tube is connected with the clock signal end, the source of the tenth NMOS tube is grounded, and the drain of the tenth NMOS tube is connected with the source of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected with the sixth signal end, and the drain of the eleventh NMOS tube is connected with the source of the eleventh PMOS tube; the source of the twelfth NMOS tube is connected with the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is connected with the first signal end, and the drain of the tenth NMOS tube is connected with the source of the twelfth PMOS tube; the gate of the thirteenth NMOS tube is connected with the fourth signal end, the source of the thirteenth NMOS tube is grounded, and the drain of the thirteenth NMOS tube is connected with the fifth signal end.

[0013] Preferably, when the latch is in the transparent state, it can include:

[0014] In the first detection circuit, the tenth PMOS tube is turned on, the tenth NMOS tube is turned off, the level output to the fourth signal end node is high, and the level output to the fifth signal end node is low.

[0015] In the basic latch, the third PMOS tube and the third NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned off, the ninth PMOS tube and the ninth NMOS tube are turned on, the fourteenth PMOS and the fourteenth NMOS are turned on, the sixth signal end node is low, and the seventh signal end node is high.

[0016] Preferably, when the latch is in the latch state, it can include:

[0017] In the first detection circuit, the ninth PMOS tube and the ninth NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned on, the tenth PMOS tube is turned off, and the tenth NMOS tube is turned on.

[0018] When the first signal end is 1 and the second signal end is 0 in the basic latch; if a single event upset does not occur, the latch output is the third signal end; if a single event upset occurs in the first signal end and / or the second signal end node, the latch output is the second signal end.

[0019] When the first signal end is 1 and the second signal end is 0 in the basic latch, if no single event upset occurs, the latch output is the third signal end; if single event upset occurs in the first signal end and / or the second signal end node, the latch output is the second signal end.

[0020] Preferably, the detection circuit can comprise a second detection circuit, the second detection circuit comprising a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, and a thirty-seventh NMOS tube.

[0021] The source of the twenty-ninth PMOS tube is connected with the power supply end, the gate of the twenty-ninth PMOS tube is connected with the clock signal end, and the drain of the twenty-ninth PMOS tube is connected with the source of the thirtieth PMOS tube; the gate of the thirtieth PMOS tube is connected with the first signal end, the drain of the thirtieth PMOS tube is connected with the drain of the thirty-first NMOS tube, the source of the thirtieth PMOS tube is connected with the thirteenth signal end; the gate of the thirty-first NMOS tube is connected with the clock signal end, and the source of the thirty-first NMOS tube is grounded; the gate of the thirty-second PMOS tube is connected with the thirteenth signal end, the source of the thirty-second PMOS tube is connected with the power supply end, and the drain of the thirty-second PMOS tube is connected with the fourteenth signal end; the drain of the thirty-second NMOS tube is connected with the fourteenth signal end, the source of the thirty-second NMOS tube is grounded, and the gate of the thirty-second NMOS tube is connected with the thirteenth signal end; the source of the thirty-first PMOS tube is connected with the power supply end, the gate of the thirty-first PMOS tube is connected with the clock inverse signal end, and the drain of the thirty-first PMOS tube is connected with the drain of the thirtieth NMOS tube; the source of the thirtieth NMOS tube is connected with the fifteenth signal end, the gate of the thirtieth NMOS tube is connected with the first signal end, and the source of the thirtieth NMOS tube is connected with the drain of the twenty-ninth NMOS tube; the gate of the twenty-ninth NMOS tube is connected with the clock inverse signal end, and the source of the twenty-ninth NMOS tube is grounded; the source of the thirty-third PMOS tube is connected with the power supply end, the gate of the thirty-third PMOS tube is connected with the fifteenth signal end, and the drain of the thirty-third PMOS tube is connected with the sixteenth signal end; the source of the thirty-third NMOS tube is grounded, the gate of the thirty-third NMOS tube is connected with the fifteenth signal end, and the gate drain of the thirty-third NMOS tube is connected with the sixteenth signal end;

[0022] The gate of the thirty-fourth PMOS tube is connected with a clock signal end, the source of the thirty-fourth PMOS tube is connected with a power supply end, and the drain of the thirty-fourth PMOS tube is connected with a fourth signal end; the source of the thirty-fifth PMOS tube is connected with the power supply end, the gate of the thirty-fifth PMOS tube is connected with a thirteenth signal end, and the drain of the thirty-fifth PMOS tube is connected with the source of the thirty-seventh PMOS tube; the gate of the thirty-seventh PMOS tube is connected with a fifteenth signal end, and the drain of the thirty-seventh PMOS tube is connected with the fourth signal end; the source of the thirty-sixth PMOS tube is connected with the power supply end, the gate of the thirty-sixth PMOS tube is connected with a fourteenth signal end, and the drain of the thirty-sixth PMOS tube is connected with the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected with a sixteenth signal end, and the drain of the thirty-eighth PMOS tube is connected with the fourth signal end; the source of the thirty-ninth PMOS tube is connected with the power supply end, the gate of the thirty-ninth PMOS tube is connected with the fourth signal end, and the drain of the thirty-ninth PMOS tube is connected with a fifth signal end; the drain of the thirty-fourth NMOS tube is connected with the source of the thirty-fifth NMOS tube, the gate of the thirty-fourth NMOS tube is connected with the clock signal end, and the source of the thirty-fourth NMOS tube is grounded; the drain of the thirty-fifth NMOS tube is connected with the source of the thirty-sixth NMOS tube, the gate of the thirty-fifth NMOS tube is connected with the fourteenth signal end; the gate of the thirty-sixth NMOS tube is connected with the fifteenth signal end, and the drain of the thirty-sixth NMOS tube is connected with the fourth signal end; the drain of the thirty-seventh NMOS tube is connected with the fifth signal end, the source of the thirty-seventh NMOS tube is grounded, and the gate of the thirty-seventh NMOS tube is connected with the fourth signal end.

[0023] Preferably, when the latch is in a latching state, it can include:

[0024] The twenty-ninth PMOS tube and the twenty-ninth NMOS tube in the second detection circuit are turned off, and the thirty-first PMOS tube and the thirty-first NMOS tube are turned on;

[0025] When the first signal end is 1 and the second signal end is 0 in the basic latch, if a single event upset does not occur, the latch outputs the third signal end; if a single event upset occurs at the first signal end and / or the second signal end node, the latch outputs the electrical signal corresponding to the second signal end;

[0026] When the first signal end is 0 and the second signal end is 1 in the basic latch, if a single event upset does not occur, the latch outputs the third signal end; if a single event upset occurs at the first signal end and / or the second signal end node, the latch outputs the electrical signal corresponding to the second signal end.

[0027] Preferably, the basic latch can comprise a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a sixth NMOS transistor and a fourteenth NMOS transistor; and the transmission gate comprises a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor.

[0028] The source of the first PMOS transistor is connected with the source of the third PMOS transistor, the drain of the first PMOS transistor is connected with the second signal terminal, and the gate of the first PMOS transistor is connected with the first signal terminal; the source of the second PMOS transistor is connected with the drain of the third PMOS transistor, the drain of the second PMOS transistor is connected with the first signal terminal, and the gate of the second PMOS transistor is connected with the second signal terminal; the gate of the third PMOS transistor is connected with the clock inverse signal terminal; the gate of the sixth PMOS transistor is connected with the second signal terminal, the source of the sixth PMOS transistor is connected with the power terminal, and the drain of the sixth PMOS transistor is connected with the third signal terminal; the gate of the fourteenth PMOS transistor is connected with the clock signal terminal, the drain of the fourteenth PMOS transistor is connected with the input terminal of the latch, and the source of the fourteenth PMOS transistor is connected with the first signal terminal.

[0029] The drain of the first NMOS transistor is connected with the second signal terminal, the source of the first NMOS transistor is connected with the source of the third NMOS transistor, and the gate of the first NMOS transistor is connected with the first signal terminal; the source of the second NMOS transistor is connected with the drain of the third NMOS transistor, the drain of the second NMOS transistor is connected with the first signal terminal, and the gate of the second NMOS transistor is connected with the second signal terminal; the gate of the third NMOS transistor is connected with the clock signal terminal; the gate of the sixth NMOS transistor is connected with the second signal terminal, the source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected with the third signal terminal; the gate of the fourteenth NMOS transistor is connected with the clock inverse signal terminal, the drain of the fourteenth NMOS transistor is connected with the input terminal of the latch, and the source of the fourteenth NMOS transistor is connected with the first signal terminal.

[0030] The gate of the fourth PMOS tube is connected with the fifth signal terminal, the drain of the fourth PMOS tube is connected with the third signal terminal, and the source of the fourth PMOS tube is connected with the input terminal of the slave stage latch; the gate of the fifth PMOS tube is connected with the fourth signal terminal, the drain of the fifth PMOS tube is connected with the second signal terminal, and the source of the fifth PMOS tube is connected with the input terminal of the slave stage latch; the gate of the fourth NMOS tube is connected with the fourth signal terminal, the drain of the fourth NMOS tube is connected with the third signal terminal, and the source of the fourth NMOS tube is connected with the input terminal of the slave stage latch; the gate of the fifth NMOS tube is connected with the fifth signal terminal, the drain of the fifth NMOS tube is connected with the second signal terminal, and the source of the fifth NMOS tube is connected with the input terminal of the slave stage latch.

[0031] In a second aspect, the present application provides a flip-flop for resisting single event upset in a digital circuit, which can include at least a latch and a slave stage latch;

[0032] The input terminal of the latch is connected with the input terminal of the flip-flop, the output terminal of the latch is connected with the input terminal of the slave stage latch, and the output terminal of the slave stage latch is connected with the output terminal of the flip-flop;

[0033] The latch can include at least a detection circuit and a basic latch; the flip-flop uses the detection signal of the detection circuit to judge the level flip state of the basic latch, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch;

[0034] The slave stage latch can include at least a slave stage detection circuit and a slave stage basic latch; the flip-flop uses the detection signal of the slave stage detection circuit to judge the level flip state of the slave stage basic latch, and generates a control signal for controlling the output of the slave stage latch based on the level flip state of the slave stage basic latch.

[0035] Preferably, the latch can further include a transmission gate, and the slave stage latch can further include a slave stage transmission gate;

[0036] The input terminal of the basic latch is connected with the input terminal of the flip-flop, the output terminal of the basic latch is connected with the input terminal of the slave stage transmission gate, and the output terminal of the slave stage transmission gate is connected with the output terminal of the flip-flop;

[0037] The basic latch is used for latching the storage level state of the latch, and the slave stage basic latch is used for latching the storage level state of the slave stage latch.

[0038] Preferably, the slave stage basic latch can comprise a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a twentieth PMOS transistor, a twenty-eighth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a twentieth NMOS transistor and a twenty-eighth NMOS transistor; and the slave stage transmission gate comprises an eighteenth PMOS transistor, a nineteenth PMOS transistor, an eighteenth NMOS transistor and a nineteenth NMOS transistor.

[0039] The source of the fifteenth PMOS transistor is connected with the source of the seventeenth PMOS transistor, the drain of the fifteenth PMOS transistor is connected with a ninth signal terminal, and the gate of the fifteenth PMOS transistor is connected with an eighth signal terminal; the source of the sixteenth PMOS transistor is connected with the drain of the seventeenth PMOS transistor, the drain of the sixteenth PMOS transistor is connected with the eighth signal terminal, and the gate of the sixteenth PMOS transistor is connected with the ninth signal terminal; the gate of the seventeenth PMOS transistor is connected with a clock signal terminal; the gate of the twentieth PMOS transistor is connected with the ninth signal terminal, the source of the twentieth PMOS transistor is connected with a power terminal, and the drain of the twentieth PMOS transistor is connected with a tenth signal terminal; the gate of the twenty-eighth PMOS transistor is connected with a clock inverse signal terminal, the drain of the twenty-eighth PMOS transistor is connected with an input terminal of the slave stage basic latch, and the source of the twenty-eighth PMOS transistor is connected with the eighth signal terminal.

[0040] The drain of the fifteenth NMOS transistor is connected with the ninth signal terminal, the source of the fifteenth NMOS transistor is connected with the source of the seventeenth NMOS transistor, and the gate of the fifteenth NMOS transistor is connected with the eighth signal terminal; the source of the sixteenth NMOS transistor is connected with the drain of the seventeenth NMOS transistor, the drain of the sixteenth NMOS transistor is connected with the eighth signal terminal, and the gate of the sixteenth NMOS transistor is connected with the ninth signal terminal; the gate of the seventeenth NMOS transistor is connected with the clock inverse signal terminal; the gate of the twentieth NMOS transistor is connected with the ninth signal terminal, the source of the twentieth NMOS transistor is grounded, and the drain of the twentieth NMOS transistor is connected with the tenth signal terminal; the gate of the twenty-eighth NMOS transistor is connected with the clock signal terminal, the drain of the twenty-eighth NMOS transistor is connected with the input terminal of the slave stage basic latch, and the source of the twenty-eighth NMOS transistor is connected with the eighth signal terminal.

[0041] The gate of the eighteenth PMOS tube is connected with the twelfth signal terminal, the drain of the eighteenth PMOS tube is connected with the tenth signal terminal, and the source of the eighteenth PMOS tube is connected with the output terminal of the flip-flop; the gate of the nineteenth PMOS tube is connected with the eleventh signal terminal, the drain of the nineteenth PMOS tube is connected with the ninth signal terminal, and the source of the nineteenth PMOS tube is connected with the output terminal of the flip-flop; the gate of the eighteenth NMOS tube is connected with the eleventh signal terminal, the drain of the eighteenth NMOS tube is connected with the tenth signal terminal, and the source of the eighteenth NMOS tube is connected with the output terminal of the flip-flop; the gate of the nineteenth NMOS tube is connected with the twelfth signal terminal, the drain of the nineteenth NMOS tube is connected with the ninth signal terminal, and the source of the nineteenth NMOS tube is connected with the output terminal of the flip-flop.

[0042] Compared with the prior art, the application provides a latch resisting single event upset in a digital circuit, which can at least include a basic latch, a transmission gate and a detection circuit; the input terminal of the basic latch is connected with the input terminal of the latch, the output terminal of the basic latch is connected with the input terminal of the transmission gate, the output terminal of the transmission gate is connected with the output terminal of the latch, the input terminal of the detection circuit is connected with the basic latch, and the output terminal of the detection circuit is connected with the transmission gate; the latch uses the detection signal of the detection circuit to judge the level upset state of the basic latch, and generates a control signal controlling the output of the latch based on the level upset state of the basic latch; therefore, if any node in the latch circuit does not undergo single event upset, the latch normally outputs data; if single event upset occurs, the inverted level is outputted, which ensures that the latch can output correct logic level after multiple node single event upset, and improves the resistance of the latch structure to single event radiation effect. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings:

[0044] Figure 1 It is a first detection circuit structure schematic diagram in the prior art;

[0045] Figure 2 It is a second detection circuit structure schematic diagram in the prior art;

[0046] Figure 3 It is a main circuit structure schematic diagram of a latch resisting single event upset in a digital circuit and a flip-flop provided by the application;

[0047] Figure 4A first detection circuit structure schematic diagram of a latch and a flip-flop resisting single event upset in a digital circuit is provided in the present application.

[0048] Figure 5 A second detection circuit structure schematic diagram of a latch and a flip-flop resisting single event upset in a digital circuit is provided in the present application.

[0049] Figures: 100-flip-flop, 110-latch, 120-slave stage latch, 112-detection circuit, 111-basic latch, 113-transmission gate, 122-slave stage detection circuit, 121-slave stage basic latch, 123-slave stage transmission gate, 1121-first detection circuit, 1122-second detection circuit, clkb-clock inverse signal end, clkbb-clock signal end, b0-first signal end, b1-second signal end, b1N-third signal end, E1-fourth signal end, E1N-fifth signal end, A1-sixth signal end, C1-seventh signal end, b2-eighth signal end, b3-ninth signal end, b3N-tenth signal end, E2-eleventh signal end, E2N-twelfth signal end, A2-thirteenth signal end, A2N-fourteenth signal end, C2-fifteenth signal end, C2N-sixteenth signal end, IN-input end, OUT-output end. DETAILED DESCRIPTION

[0050] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc. For example, the first threshold value and the second threshold value are only used to distinguish different threshold values, and the first and the second are not limited in time sequence. Those skilled in the art can understand that "first", "second", etc. do not limit the quantity and execution sequence, and "first", "second", etc. do not necessarily mean different.

[0051] It should be noted that in the present application, "exemplary" or "for example" is used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0052] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents that the associated objects are in an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0053] At present, the traditional flip-flop reinforcement scheme is to reinforce the master-slave stage latch of the flip-flop; please refer to Figures 1 to 2 ; Figure 1 The first kind of detection circuit structure in the prior art is shown in the schematic diagram. Figure 2 The second kind of detection circuit structure in the prior art is shown in the schematic diagram.

[0054] Figure 1 The reinforcement design shown in the above formula is a single particle flip-flop reinforcement structure of a dual inter-locked storage cell (DICE), which has four data storage nodes. When a node occurs a single particle flip-flop due to an external high-energy particle, since the data stored in each node is controlled by another two nodes, the temporary flip-flop of a single node will not propagate the error level to other nodes, and will not cause the logic state change of other nodes. Finally, the other nodes unaffected by the feedback structure of the structure can restore the storage node with a single particle flip-flop to the original level.

[0055] The DICE reinforcement structure has good resistance to single node flip-flop, but as the semiconductor process improves, the shortening of the node spacing makes the charge sharing effect become more and more significant, and it is very easy to trigger the latch structure in the flip-flop circuit to occur multiple node flip-flops at the same time, and the DICE structure cannot resist multiple node flip-flops at the same time. The interlocking structure will increase the circuit delay and reduce the data transmission rate.

[0056] Figure 2The reinforcement design shown in the middle is a latch structure named Quatro, which has four data storage nodes, and the logic state of each node is controlled by another two nodes. When a node is flipped by an external high-energy particle, the temporary flip of a single node will not propagate the error level to other nodes and cause the logic state of other nodes to change, and finally the other nodes unaffected by the feedback structure of the structure can restore the storage node flipped by a single particle to the original level.

[0057] The structure cannot completely resist the case of single node flip, and there are two nodes in the four nodes, and when the two nodes are flipped, the logic state of the entire structure may be flipped. In addition, similar to the DICE structure, it also cannot resist the simultaneous flip of multiple nodes, and the interlocking structure increases the circuit delay and reduces the data transmission rate.

[0058] Therefore, the present application provides a latch and flip-flop that resists single event upset in digital circuits. By reinforcing the design of the ordinary trigger circuit, the memory structure in the flip-flop can recover to the correct level after being bombarded by multiple nodes of single particle, so that it has the ability to resist single particle radiation effects and can work normally in a space radiation environment. Moreover, the reinforcement structure of the reinforced latch circuit provided by the present application is not on the critical path of the circuit, has low circuit delay, and thus can improve the data transmission rate of the circuit, and is suitable for high-speed and high-performance circuit design.

[0059] Next, the technical solutions of the present application will be described in detail in combination with the drawings:

[0060] Please refer to Figure 3 , Figure 3 The main circuit structure diagram of a latch and flip-flop that resists single event upset in digital circuits provided by the present application. It should be noted that the present application Figure 3The overall circuit structure shown is a flip-flop circuit structure, which is essentially a single-event upset (SEE) resistant flip-flop composed of a left-hand latch circuit structure and a right-hand slave latch circuit structure. The left-hand latch circuit is a SEE resistant latch provided by this invention. In the SEE resistant flip-flop provided by this invention, the latch uses the same circuit structure as the SEE resistant latch provided by this invention; the slave latch circuit structure is the same as the latch circuit structure, the difference being that the operating states of the latch and the slave latch are reversed. Therefore, for the sake of concise explanation of the technical solution of this invention, in specific embodiments, [the following is used as an example]. Figure 3 The flip-flop circuit structure shown is introduced as a whole, and the solution is described using the latch circuit structure as an example; in practical applications, Figure 3 The latch in the circuit can also be called the master-level latch. Similarly, the sub-circuit structure in the latch, the basic latch can also be called the master-level basic latch, the transmission gate can also be called the master-level transmission gate, and the probe circuit can also be called the master-level probe circuit.

[0061] exist Figure 3 In this circuit, latch 110 includes at least a basic latch 111, a transmission gate 113, and a detection circuit 112; the input terminal of the basic latch 111 is connected to the input terminal of the latch 110, the output terminal of the basic latch 111 is connected to the input terminal of the transmission gate 113, the output terminal of the transmission gate 113 is connected to the output terminal of the latch 110, the input terminal of the detection circuit 112 is connected to the basic latch 110, and the output terminal of the detection circuit 112 is connected to the transmission gate 113.

[0062] The latch 110 uses the detection signal from the detection circuit 112 to determine the level switching state of the basic latch 111, and generates a control signal to control the latch 110 based on the level switching state of the basic latch 111; the output signal of the latch 110 serves as the input signal of the slave latch 120. The detection circuit 112 is a hardened circuit structure for the latch 110; the operating states of the latch 110 and the slave latch 120 are opposite; that is, when the latch 110 is in a transparent state, the slave latch 120 is in a latched state; when the latch 110 is in a latched state, the slave latch 120 is in a transparent state; wherein, the transparent state of the latch is for pre-charging during the transmission phase, and the latched state is for the calculation and evaluation phase.

[0063] Based on this, the application provides a latch resisting single event upset in a digital circuit, which comprises a basic latch, a transmission gate and a detection circuit; the input end of the basic latch is connected with the input end of the latch, the output end of the basic latch is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the output end of the latch, the input end of the detection circuit is connected with the basic latch, and the output end of the detection circuit is connected with the transmission gate; the latch uses the detection signal of the detection circuit to judge the level upset state of the basic latch, and generates a control signal for controlling the output of the latch based on the level upset state of the basic latch; the output signal of the latch is used as the input signal of a slave latch; thus, the latch structure can be restored to the correct level after being subjected to multi-node single particle bombardment, the resistance to single particle radiation effect is improved, the latch has the resistance to single particle radiation effect, and can work normally in a space irradiation environment; the problem that the latch structure in the prior art cannot resist single event upset of multiple nodes is solved. Moreover, the detection circuit in the latch circuit is not on the critical path of the circuit, so that the circuit delay is low, the data transmission rate of the circuit is improved, and the latch is suitable for high-speed and high-performance circuit design.

[0064] Preferably, the basic latch 111 can comprise a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixth PMOS tube, a fourteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a sixth NMOS tube and a fourteenth NMOS tube; and the transmission gate comprises a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube.

[0065] Specifically, the MOS tubes can be connected in the following manner: the source of the first PMOS tube is connected with the source of the third PMOS tube, the drain is connected with the second signal end b1, and the gate is connected with the first signal end b0; the source of the second PMOS tube is connected with the drain of the third PMOS tube, the drain is connected with the first signal end b0, and the gate is connected with the second signal end b1; the gate of the third PMOS tube is connected with the clock inverse signal end; the gate of the sixth PMOS tube is connected with the second signal end b1, the source is connected with the power supply end, and the drain is connected with the third signal end b1N; the gate of the fourteenth PMOS tube is connected with the clock signal end, the drain is connected with the input end of the latch, and the source is connected with the first signal end b0.

[0066] The drain of the first NMOS tube is connected with the second signal terminal b1, the source is connected with the source of the third NMOS tube, and the gate is connected with the first signal terminal b0; the source of the second NMOS tube is connected with the drain of the third NMOS tube, the drain is connected with the first signal terminal b0, and the gate is connected with the second signal terminal b1; the gate of the third NMOS tube is connected with the clock signal terminal; the gate of the sixth NMOS tube is connected with the second signal terminal b1, the source is grounded, and the drain is connected with the third signal terminal b1N; the gate of the fourteenth NMOS tube is connected with the clock inverse signal terminal, the drain is connected with the input terminal of the latch, and the source is connected with the first signal terminal b0.

[0067] The gate of the fourth PMOS tube is connected with the fifth signal terminal E1N, the drain is connected with the third signal terminal b1N, and the source is connected with the input terminal of the slave latch; the gate of the fifth PMOS tube is connected with the fourth signal terminal E1, the drain is connected with the second signal terminal b1, and the source is connected with the input terminal of the slave latch; the gate of the fourth NMOS tube is connected with the fourth signal terminal E1, the drain is connected with the third signal terminal b1N, and the source is connected with the input terminal of the slave latch; the gate of the fifth NMOS tube is connected with the fifth signal terminal E1N, the drain is connected with the second signal terminal b1, and the source is connected with the input terminal of the slave latch.

[0068] The following will be described by taking the circuit structure of the detection circuit in the hardened circuit of the latch as an example. As an example, the latch for resisting single event upset in a digital circuit of the present application adopts two kinds of detection circuit structures to form two kinds of high-speed anti-radiation hardened latches, which are realized by different detection circuits and transmission modules. The following will be described by taking the latch as an example. It should be noted that the detection circuits (the first detection circuit and the second detection circuit) shown in the following two kinds of ways are applied to the slave latch, and the input clock signal is inverted and then input correspondingly, and the connection modes of other ports in the slave latch are the same as those of the detection circuit in the latch.

[0069] Please refer to Figures 4 to 5 , Figure 4 The first detection circuit structure of the latch for resisting single event upset in a digital circuit and the flip-flop of the present application is shown in the figure; Figure 5This invention provides a schematic diagram of a second detection circuit structure for a latch and flip-flop resisting single-event upsets in digital circuits. When these two detection circuit structures are applied to the latch and flip-flop resisting single-event upsets in digital circuits provided by this invention, both can enable the latch structure (memory structure) in the flip-flop to recover to the correct level after being bombarded by multiple single-event events, thus giving it resistance to single-event radiation effects and allowing it to operate normally in space radiation environments. Furthermore, since it is not on the critical path of the circuit, it has lower circuit delay, thereby improving the data transmission rate of the circuit and making it suitable for high-speed, high-performance circuit designs.

[0070] Method 1, in Figure 4 In the first detection circuit 1121, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor may be included.

[0071] Specifically, the MOS transistors can be connected as follows: connect the drain of the seventh PMOS transistor to the third signal terminal b1N, the gate to the clock inverted signal terminal, and the source to the drain of the eighth PMOS transistor; connect the gate of the eighth PMOS transistor to the first signal terminal b0, and the source to the drain of the ninth PMOS transistor; connect the gate of the ninth PMOS transistor to the clock inverted signal terminal, the source to the power supply terminal, and the drain to the seventh signal terminal C1; connect the gate of the tenth PMOS transistor to the clock signal terminal, the source to the power supply terminal, and the drain to the drain of the eleventh PMOS transistor and the fourth signal terminal E1; connect the gate of the eleventh PMOS transistor to the first signal terminal b0; connect the drain of the twelfth PMOS transistor to the fourth signal terminal E1, and the gate to the seventh signal terminal C1; connect the gate of the thirteenth PMOS transistor to the fourth signal terminal E1, the source to the power supply terminal, and the drain to the fifth signal terminal E1N.

[0072] The drain of the seventh NMOS tube is connected with the third signal terminal b1N, the gate is connected with the clock signal terminal, and the source is connected with the source of the seventh PMOS tube; the drain of the eighth NMOS tube is connected with the drain of the eighth PMOS tube, the gate is connected with the first signal terminal b0, and the source is connected with the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is connected with the clock signal terminal, the source is grounded, and the drain is connected with the sixth signal terminal A1; the gate of the tenth NMOS tube is connected with the clock signal terminal, the source is grounded, and the drain is connected with the source of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected with the sixth signal terminal A1, and the drain is connected with the source of the eleventh PMOS tube; the source of the twelfth NMOS tube is connected with the drain of the tenth NMOS tube, the gate is connected with the first signal terminal b0, and the drain is connected with the source of the twelfth PMOS tube; the gate of the thirteenth NMOS tube is connected with the fourth signal terminal E1, the source is grounded, and the drain is connected with the fifth signal terminal E1N.

[0073] The working principle of the latch of the detection circuit in mode one is as follows:

[0074] When the latch is in the transparent state, the tenth PMOS tube in the first detection circuit 1121 is turned on, the tenth NMOS tube is turned off, the level of the node of the fourth signal terminal E1 output to the fourth signal terminal E1 is high, and the level of the node of the fifth signal terminal E1N output to the fifth signal terminal E1N is low; the third PMOS tube and the third NMOS tube in the basic latch are turned off, the seventh PMOS tube and the seventh NMOS tube are turned off, the ninth PMOS tube and the ninth NMOS tube are turned on, the sixth signal terminal A1 node is low, and the seventh signal terminal C1 node is high.

[0075] In Figure 4 , the output signal terminal of the first detection circuit 1121 is connected with the fourth signal terminal E1 and the fifth signal terminal E1N; the input signal terminal is the second signal terminal b1, the third signal terminal b1N, the clock inverse signal terminal clkb and the clock signal terminal clkbb. It should be noted that E1 and E1N are inverse signal ports, that is, when E1 is 0, E1N is 1; when E1 is 1, E1N is 0. Similarly, b1 and b1N are inverse signal ports, clkb and clkbb are inverse signal ports; and in other paragraphs or drawings of the specification, b3 and b3N are inverse signal ports, E2 and E2N are inverse signal ports, A2 and A2N are inverse signal ports, and C2 and C2N are inverse signal ports.

[0076] Preferably, when the latch is in the latch state, the ninth PMOS tube and the ninth NMOS tube in the first detection circuit 1121 are turned off, the seventh PMOS tube and the seventh NMOS tube are turned on, the tenth PMOS tube is turned off, and the tenth NMOS tube is turned on.

[0077] When the first signal end b0 in the basic latch is 1 and the second signal end b1 is 0; if a single event upset does not occur, the latch output is the third signal end b1N; if a single event upset occurs at the first signal end b0 and / or the second signal end b1 node, the latch output is the corresponding electrical signal of the second signal end b1.

[0078] When the first signal end b0 in the basic latch is 1 and the second signal end b1 is 0; if a single event upset does not occur, the latch output is the third signal end b1N; if a single event upset occurs at the first signal end b0 and / or the second signal end b1 node, the latch output is the corresponding electrical signal of the second signal end b1.

[0079] Specifically, the working principle of the first mode is as follows:

[0080] (1) Transparent state (the clock clk is low)

[0081] When the latch is in the transparent state, the clkbb is low at this time, the MP10 is turned on, the MN10 is turned off, the E1 node is pulled up to high level, the EN1 output is low, therefore the MP4 and the MN4 are turned on, the MP5 and the MN5 are turned off, the detection circuit has no any influence on the output of the latch, and the working state is equivalent to an ordinary latch; in the latch, since the clkbb is low, the reverse clock signal clkb is high, the MP3 and the MN3 are turned off, the input signal IN is transmitted to the b0, then reaches the b1 node through an inverter, and then is transmitted as the main level output OUT through an inverter, and the MP7 and the MN7 are turned off when the clkbb is low, so the value of the b1N node will not be transmitted to the A1 and C1 nodes, the MP9 and the MN9 are turned on, the MP14 and the MN14 are turned on, therefore the A1 node is pulled down to low level, and the C1 node is pulled up to high level.

[0082] (2) Latch state (the clock clk is high)

[0083] When the latch is in the latch state, the clkbb is high at this time. The MP9 and the MN9 are turned off, the MP7 and the MN7 are turned on, the MP10 is turned off, and the MN10 is turned on. The circuit can be in two working states:

[0084] ① When b0 = 1, b1 = 0:

[0085] a) When no single event upset occurs, at this time, since b0=1, MP8 is off, MN8 is on, b1N=1 is transmitted to the A1 node, thus A1=1, while C1 remains its original high level unchanged, and its high level can be maintained by the drain current of MP8. Since b0=1, b1=0, A1=1, C1=1, MP11 and MP12 in the two pull-down paths of the E1 node are both off, E1 remains 1 unchanged, E1N=0, thus MP4 and MN4 are on, MP5 and MN5 are off, at this time the detection circuit has no effect on the output, the circuit output OUT is connected to the b1N node, so under the condition of no single event upset, the latch works in the same way as a normal latch.

[0086] b) When a single event upset occurs on any node b0 and / or b1 in the basic latch, it will cause an error latch. Irradiation particles will produce a low-level pulse in NMOS and a high-level pulse in PMOS. The b0 and b1 nodes are connected to both NMOS and PMOS, so the b0 and b1 nodes may undergo a flip from 0 to 1 or from 1 to 0. When b0=1, b1=0, the latch circuit state flips, i.e. b0=0, b1=1. b1N=0, MP8 is on, b1N=0 is transmitted to C1, b0=0, C1=0, A1=1, MP11 and MN11 are on, there is a pull-down path for the E node, the level of the E1 node is pulled low to 0, at this time MP4 and MN4 are off, MP5 and MN5 are on, the output is b1 instead of b1N, so the circuit output is still 1.

[0087] c) For the nodes in the first detection circuit 1121, since the E1 node and the C1 node are surrounded by PMOS, they will only undergo a flip from 0 to 1 under the action of single particles, while the A1 node is surrounded by NMOS and thus will only undergo a flip from 1 to 0. Therefore, when b0=1, b1=0, A1=1, C1=1, only the A1 node may flip to 0, and the A1 node flipping to 0 will only turn off MN11, the E1 node still has no pull-down path and E1 still equals 1, so the output is still the output of the latch b1N node. If only b1N undergoes a 1 to 0 jump, this case is similar to the above-mentioned flip of the A1 node from 1 to 0.

[0088] ② When b0=0, b1=1:

[0089] a) When no single event upset occurs in the latch structure, at this time, since b0=0, MP8 is on, C1 is pulled down to low level, since b0=0, b1=1, C1=0, A1=0, therefore MN11 and MN12 in the two pull-down paths of E1 node are both off, E1 remains 1 unchanged, E1N=0, MP11 is on, and then E1 node is maintained at high level, therefore MP4 and MN4 are on, MP5 and MN5 are off, at this time, the detection circuit has no effect on the output, the latch circuit output is connected to b1N node, therefore, in the case of no single event upset, the working state is equivalent to that of a normal latch.

[0090] b) When single event upset occurs in any node b0 and / or b1 in the latch, it will cause false latching, the irradiation particles will produce low level pulse in NMOS and high level pulse in PMOS, b0 and b1 nodes are connected to both NMOS and PMOS, therefore, b0 and b1 nodes can occur from 0 to 1 flip or from 1 to 0 flip, when b0=1, b1=0, the latch circuit state flips, i.e. b0=1, b1=0, b1N=1, therefore MN8 is on, A1 is pulled up to 1, at this time, b0=1, b1=0, A1=1, C1=0, MP12 and MN12 in the pull-down path of E1 node are on, therefore E1=0, E1N=1, MP4 and MN4 are off, MP5 and MN5 are on, the output is b1 instead of b1N, therefore the latch circuit output is still 0.

[0091] c) For the nodes in the first detection circuit 1121, since E1 node and C1 node are surrounded by PMOS, therefore, only 0 to 1 flip will occur in single event upset, and A1 node is surrounded by NMOS, therefore, only 1 to 0 flip will occur, so when b0=0, b1=1, A1=0, C1=0, and C1 node flips to 1, only MP12 will be off, E1 node still has no pull-down path, E1 still equals to 1, therefore the output is still the output of the latch b1N node. If only b1N occurs 1 to 0 jump, this case is similar to the above-mentioned 1 to 0 flip of A1 node.

[0092] For the corresponding hardened circuit of the second stage latch, it is high level transparent and low level latching, therefore all clock control signals are inverted with the main stage.

[0093] Method two, in Figure 5In the embodiment, the second detection circuit 1122 can include a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube, and a thirty-seventh NMOS tube.

[0094] Specifically, the source of the twenty-ninth PMOS tube can be connected with the power supply end, the gate can be connected with the clock signal end, and the drain can be connected with the source of the thirtieth PMOS tube; the gate of the thirtieth PMOS tube can be connected with the first signal end b0, the drain can be connected with the drain of the thirty-first NMOS tube, and the source can be connected with the thirteenth signal end A2; the gate of the thirty-first NMOS tube can be connected with the clock signal end, and the source can be grounded; the gate of the thirty-second PMOS tube can be connected with the thirteenth signal end A2, the source can be connected with the power supply end, and the drain can be connected with the fourteenth signal end A2N; the drain of the thirty-second NMOS tube can be connected with the fourteenth signal end A2N, the source can be grounded, and the gate can be connected with the thirteenth signal end A2; the source of the thirty-first PMOS tube can be connected with the power supply end, the gate can be connected with the clock inverse signal end, and the drain can be connected with the drain of the thirtieth NMOS tube; the source of the thirtieth NMOS tube can be connected with the fifteenth signal end C2, the gate can be connected with the first signal end b0, and the source can be connected with the drain of the twenty-ninth NMOS tube; the gate of the twenty-ninth NMOS tube can be connected with the clock inverse signal end, and the source can be grounded; the source of the thirty-third PMOS tube can be connected with the power supply end, the gate can be connected with the fifteenth signal end C2, and the drain can be connected with the sixteenth signal end C2N; the source of the thirty-third NMOS tube can be grounded, the gate can be connected with the fifteenth signal end C2, and the drain can be connected with the sixteenth signal end C2N.

[0095] The gate of the thirty-fourth PMOS tube is connected with the clock signal end, the source is connected with the power supply end, and the drain is connected with the fourth signal end E1; the source of the thirty-fifth PMOS tube is connected with the power supply end, the gate is connected with the thirteenth signal end A2, and the drain is connected with the source of the thirty-seventh PMOS tube; the gate of the thirty-seventh PMOS tube is connected with the fifteenth signal end C2, and the drain is connected with the fourth signal end E1; the source of the thirty-sixth PMOS tube is connected with the power supply end, the gate is connected with the fourteenth signal end A2N, and the drain is connected with the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected with the sixteenth signal end C2N, and the drain is connected with the fourth signal end E1; the source of the thirty-ninth PMOS tube is connected with the power supply end, the gate is connected with the fourth signal end E1, and the drain is connected with the fifth signal end E1N; the drain of the thirty-fourth NMOS tube is connected with the source of the thirty-fifth NMOS tube, the gate is connected with the clock signal end, and the source is grounded; the drain of the thirty-fifth NMOS tube is connected with the source of the thirty-sixth NMOS tube, and the gate is connected with the fourteenth signal end A2N; the gate of the thirty-sixth NMOS tube is connected with the fifteenth signal end C2, and the drain is connected with the fourth signal end E1; the drain of the thirty-seventh NMOS tube is connected with the fifth signal end E1N, the source is grounded, and the gate is connected with the fourth signal end E1.

[0096] Preferably, when the latch is in the latching state, the second detection circuit 1122 can include that the twenty-ninth PMOS tube and the twenty-ninth NMOS tube are turned off, and the thirty-first PMOS tube and the thirty-first NMOS tube are turned on.

[0097] When the first signal end b0 in the basic latch is 1 and the second signal end b1 is 0; if no single event upset occurs, the latch output is the third signal end b1N; if the first signal end b0 and / or the second signal end b1 node has a single event upset, the latch output is the corresponding electrical signal of the second signal end b1.

[0098] When the first signal end b0 in the basic latch is 0 and the second signal end b1 is 1; if no single event upset occurs, the latch output is the third signal end b1N; if the first signal end b0 and / or the second signal end b1 node has a single event upset, the latch output is the corresponding electrical signal of the second signal end b1.

[0099] Specifically, the latch of the detection circuit in the second mode, the output signal of the second detection circuit 1122 is E1 and E1N; the input signal end is the second signal end b1, the third signal end b1N, the clock inverse signal end clkb and the clock signal end clkbb; and the working principle is:

[0100] (1) Transparent state (the clock clk is low)

[0101] When the basic latch is in transparent state, MP34 is on and MN34 is off, E1 node is pulled up to high level, E1N output is low level, so MP4 and MN4 are on, MP5 and MN5 are off, the second detecting circuit has no effect on the output of the latch at this time, the working state of the latch is equivalent to a common latch; since clkbb is low level, the reverse clock signal clkb is high level, MP3 and MN3 are off, the input signal is transmitted to bO and then reaches b1 node through an inverter and then through an inverter and a transmission gate as the output of the main stage.

[0102] Since MP29 and MN29 are on and MP31 and MN31 are off, A1 node is pulled up to high level 1 and C1 node is pulled down to low level 0.

[0103] (2) Latch state (clock clk is high level)

[0104] When the latch is in latch state, clkbb is high level, MP29 and MN29 are off and MP31 and MN31 are on.

[0105] When b0=1 and b1=0:

[0106] a) When the latch does not occur single event upset, since b0=1, MN30 is on, C1 is pulled up to high level, C1=1, C1N=0, A1=1, A1N=0, so MN35 in the pull-down path of E node is off and MP36 and MP38 in the pull-up path are on, so E1=1, E1N=0, MP4 and MN4 are on, MP5 and MN5 are off, the second detecting circuit has no effect on the output of the latch, so the working state of the latch is equivalent to a common latch without single event upset, the output level is b1N=1.

[0107] b) When single event upset occurs in any node b0 and / or b1 of the latch, it will cause error latch, the irradiation particle will produce low level pulse in NMOS and high level pulse in PMOS, b0 and b1 nodes are connected to NMOS and PMOS, so b0 and b1 nodes can occur flip from 0 to 1 or from 1 to 0, when b0=1 and b1=0, the state of the latch circuit is flipped, i.e. b0=0 and b1=1, so MP30 is on, A1 is pulled down to 0, A1=0, A1N=1, C1=1, C1N=0, MP36 and MP37 in the pull-up path of E node are off, MN36 and MN35 in the pull-down path are on, E1=0, E1N=1, MP4 and MN4 are off, MP5 and MN5 are on, the output is b1 instead of b1N, so the latch circuit still outputs b1=1.

[0108] c) For the nodes in the second detection circuit 1122, the A1 node is surrounded by PMOS so it will only have a 0 to 1 pulse, the C1 node is surrounded by NMOS so it will only have a 1 to 0 pulse, so when b0 = 1, b1 = 0, A1 = 1, C1 = 1, only the C1 node can flip to 0, but since MN30 is on, C1 will be pulled back to high soon, the final output of the latch circuit returns to normal.

[0109] When b0 = 0, b1 = 1:

[0110] a) When no single event upset occurs, at this time, since b0 = 0, MP30 is on, MN30 is off, A1 is pulled down to low, C1 = 0, C1N = 1, A1 = 0, A1N = 1, MN36 in the pull-down path of E node is off, and MP35 and MP37 in the pull-up path are both on, so E1 = 1, EN = 0, at this time MP4 and MN4 are on, MP5 and MN5 are off, at this time the second detection circuit has no effect on the output, so in the case of no single event upset, the working state of the latch is equivalent to that of a normal latch.

[0111] b) When a single event upset occurs on any node b0 and / or b1 in the latch, it will cause an error latch, the irradiation particle will produce a low level pulse in NMOS and a high level pulse in PMOS, b0 and b1 nodes are connected to both NMOS and PMOS, so b0 and b1 nodes can have a 0 to 1 flip or a 1 to 0 flip, when b0 = 0, b1 = 1, the circuit state flips, i.e. b0 = 1, b1 = 0, MN30 is on, C1 is pulled up to 1, A1 = 0, A1N = 1, C1 = 1, C1N = 0, MP36 and MP37 in the pull-up path of E node are off, MN35 and MN36 in the pull-down path are on, E1 = 0, E1N = 1, MP4 and MN4 are off, MP5 and MN5 are on, the output is b1 instead of b1N, so the latch circuit still outputs b1 = 0.

[0112] c) For the nodes in the second detection circuit 1122, the A1 node is surrounded by PMOS so it will only have a 0 to 1 pulse, the C1 node is surrounded by NMOS so it will only have a 1 to 0 pulse, so when b0 = 0, b1 = 1, A1 = 0, C1 = 0, only the A1 node can flip to 1, but since MP30 is on, A1 will be pulled back to low soon, the final output of the latch circuit returns to normal.

[0113] For the corresponding hardened circuit of the slave stage latch, it is high level transparent and low level latching, so all clock control signals are inverted with the main stage.

[0114] Based on this, the application provides a latch for resisting single event upset in a digital circuit, which can use the signal of the detection circuit to determine whether the latch has level state upset. If single event upset does not occur, the latch normally outputs data; if single event upset occurs, the inverted level is output. The structure can output correct logic level after single event upset, thus having good resistance to single event upset. The sensitive node of the structure is few, thus having good resistance to multi-node upset. Meanwhile, since the detection circuit as the latch reinforcement structure is located outside the data transmission critical path, the structure has high transmission rate characteristics, is suitable for anti-radiation reinforcement circuit design of advanced process, and is also suitable for single event reinforcement design of latch circuit.

[0115] In the second aspect, the application provides a flip-flop for resisting single event upset in a digital circuit, which will be described below Figure 3 . Figure 3 The whole circuit structure shown in the left half part is a flip-flop for resisting single event upset in a digital circuit. In actual application, Figure 3 The latch shown in the left half part can also be called a master latch. The flip-flop is a rising edge master-slave latch structure, which is composed of a latch circuit cascaded by a transmission gate and a slave latch circuit. The two-stage structure is consistent. The output signal of the detection circuit (single event upset detection circuit) is used to determine whether the latch circuit has single event upset, and the output signal of the detection circuit is used to determine the output signal of the master-slave latch. The output signal of the slave detection circuit is used to determine whether single event upset occurs in the corresponding circuit of the slave latch, and the output signal of the slave detection circuit is used to determine the output signal of the master-slave latch.

[0116] The detection circuit in the latch and the flip-flop for resisting single event upset in a digital circuit has the same structure as the slave detection circuit, and the difference lies in the opposite input clock signals of the detection circuit and the slave detection circuit. For example, when the first clock signal input end of the detection circuit inputs the clock signal, the first clock signal input end of the slave detection circuit inputs the clock inverse signal; when the second clock signal input end of the detection circuit inputs the clock inverse signal, the second clock signal input end of the slave detection circuit inputs the clock signal.

[0117] It should be noted that the detection circuit corresponding to the flip-flop is precharged in the transparent transmission stage of the latch, and the latch state is evaluated. The single event upset detection circuit can identify whether single event upset occurs in the latch, and send an alarm signal to provide conditions for architecture-level reinforcement. The output level of the detection circuit determines the output value of the latch. When single event upset is not detected, the latch normally outputs; when single event upset is detected, the inverted level of the latch is output.

[0118] In Figure 3 the application provides a flip-flop for resisting single event upset in digital circuit, which comprises at least a latch 110 and a slave latch 120.

[0119] The input end of the latch 110 is connected with the input end IN of the flip-flop 100, the output end of the latch 110 is connected with the input end of the slave latch 120, and the output end of the slave latch 120 is connected with the output end OUT of the flip-flop 100.

[0120] The latch 110 comprises at least a detection circuit 112 and a basic latch 111; the flip-flop 100 judges the level upset state of the basic latch 111 by using the detection signal of the detection circuit 112, and generates a control signal for controlling the output of the latch 110 based on the level upset state of the basic latch 111.

[0121] The slave latch 120 comprises at least a slave detection circuit 122 and a slave basic latch 121; the flip-flop 100 judges the level upset state of the slave basic latch 121 by using the detection signal of the slave detection circuit 122, and generates a control signal for controlling the output of the slave latch 120 based on the level upset state of the slave basic latch 121.

[0122] Preferably, the latch 110 of the flip-flop for resisting single event upset in digital circuit provided by the application can comprise a transmission gate 113, and the slave latch 120 can further comprise a slave transmission gate 123.

[0123] Specifically, the input end of the basic latch 111 is connected with the input end IN of the flip-flop 100, and the output end is connected with the input end of the transmission gate 113; the output end of the transmission gate 113 is connected with the input end of the slave latch 121, the output end of the slave latch 121 is connected with the input end of the slave transmission gate 123, and the output end of the slave transmission gate 123 is connected with the output end OUT of the flip-flop 100. The basic latch 111 is used for locking the storage level state of the main stage hardened circuit corresponding to the latch 110, and the slave basic latch 121 is used for locking the storage level state of the slave stage hardened circuit corresponding to the slave latch 120.

[0124] Preferably, the slave basic latch 121 can comprise a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a twentieth PMOS tube, a twenty-eighth PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a twentieth NMOS tube and a twenty-eighth NMOS tube; and the slave transmission gate can comprise an eighteenth PMOS tube, a nineteenth PMOS tube, an eighteenth NMOS tube and a nineteenth NMOS tube.

[0125] Specifically, the fifteenth PMOS transistor and the seventeenth PMOS transistor can be connected as follows: the source of the fifteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor, the drain is connected to the ninth signal terminal b3, and the gate is connected to the eighth signal terminal b2; the source of the sixteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor, the drain is connected to the eighth signal terminal b2, and the gate is connected to the ninth signal terminal b3; the gate of the seventeenth PMOS transistor is connected to the clock signal terminal; the gate of the twentieth PMOS transistor is connected to the ninth signal terminal b3, the source is connected to the power supply terminal, and the drain is connected to the tenth signal terminal b3N; the gate of the twenty-eighth PMOS transistor is connected to the clock inverse signal terminal, the drain is connected to the input terminal of the slave basic latch, and the source is connected to the eighth signal terminal b2; the drain of the twenty-eighth PMOS transistor is the input terminal of the slave level hardening circuit corresponding to the slave latch.

[0126] The fifteenth NMOS transistor and the seventeenth NMOS transistor can be connected as follows: the drain of the fifteenth NMOS transistor is connected to the ninth signal terminal b3, the source is connected to the source of the seventeenth NMOS transistor, and the gate is connected to the eighth signal terminal b2; the source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, the drain is connected to the eighth signal terminal b2, and the gate is connected to the ninth signal terminal b3; the gate of the seventeenth NMOS transistor is connected to the clock inverse signal terminal; the gate of the twentieth NMOS transistor is connected to the ninth signal terminal b3, the source is grounded, and the drain is connected to the tenth signal terminal b3N; the gate of the twenty-eighth NMOS transistor is connected to the clock signal terminal, the drain is connected to the input terminal of the slave basic latch, and the source is connected to the input terminal of the slave latch.

[0127] The eighteenth PMOS transistor and the nineteenth PMOS transistor can be connected as follows: the gate of the eighteenth PMOS transistor is connected to the twelfth signal terminal E2N, the drain is connected to the tenth signal terminal b3N, and the source is connected to the OUT terminal; the gate of the nineteenth PMOS transistor is connected to the eleventh signal terminal E2, the drain is connected to the ninth signal terminal b3, and the source is connected to the OUT terminal; the gate of the eighteenth NMOS transistor is connected to the eleventh signal terminal E2, the drain is connected to the tenth signal terminal b3N, and the source is connected to the OUT terminal; the gate of the nineteenth NMOS transistor is connected to the twelfth signal terminal E2N, the drain is connected to the ninth signal terminal b3, and the source is connected to the OUT terminal.

[0128] It should be noted that the circuit structure and working principle of the latch in the flip-flop are the same as those of the latch in the first aspect, and will not be described here. The working principle of the slave latch in the flip-flop is opposite to that of the latch in the first aspect, that is, by inputting a clock signal opposite to that in the latch in the slave latch, the correct level signal output of the slave latch circuit is realized when particle collision occurs in the slave latch.

[0129] Based on this, the application provides a flip-flop resisting single event upset in a digital circuit, which can also be implemented in a latch and / or a master-slave latch and can restore to a correct level after being subjected to multi-node single particle bombardment, thereby improving the resistance of the flip-flop circuit to single particle radiation effects.

[0130] Although the application has been described in connection with various embodiments thereof, it will be understood that other modifications and variations will be apparent to those skilled in the art in view of the foregoing disclosure, the drawings, and the accompanying claims. It is therefore contemplated that the application will be practiced otherwise than as specifically set forth herein. For example, claims can be presented that are different from the "normal" claims that follow the specification, but are intended to be covered thereby. Assuredly, other changes can be made to the application in light of the above teachings. The scope of the application is to be measured only in terms of the following claims, and not in terms of the brief description of the drawings and the preferred embodiments that are intended as illustrative only, and should not be used in a limiting sense. In the claims, the term "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The term "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. One processor or other unit can fulfil the requirements of several items recited in a claim. Multiple dependent claims do not require multiplication of similar features in each claim - various dependent claims can refer to each other for the purpose of their specific combination.

[0131] Although the application has been described in connection with specific embodiments thereof, it will be understood that various modifications and variations can be made without departing from the spirit and scope of the application. Accordingly, it is intended that there be included within this application all such modifications and alterations as are within the scope of the application. It is intended that the application be understood as including all such modifications and alterations. Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A latch that resists single-event flips in digital circuits, characterized in that, A latch includes at least a basic latch, a transmission gate, and a detection circuit. The input terminal of the basic latch is connected to the input terminal of the latch, the output terminal of the basic latch is connected to the input terminal of the transmission gate, the output terminal of the transmission gate is connected to the output terminal of the latch, the input terminal of the detection circuit is connected to the basic latch, and the output terminal of the detection circuit is connected to the transmission gate. The latch uses the detection signal of the detection circuit to determine the level switching state of the basic latch, and generates a control signal to control the output of the latch based on the level switching state of the basic latch; The detection circuit includes a first detection circuit or a second detection circuit; The first detection circuit includes the seventh PMOS transistor to the thirteenth PMOS transistor, and the seventh NMOS transistor to the thirteenth NMOS transistor; The drain of the seventh PMOS transistor is connected to the third signal terminal, the gate is connected to the clock inverted signal terminal, and the source is connected to the drain of the eighth PMOS transistor; the gate of the eighth PMOS transistor is connected to the first signal terminal, and the source is connected to the drain of the ninth PMOS transistor; the gate of the ninth PMOS transistor is connected to the clock inverted signal terminal, the source is connected to the power supply terminal, and the drain is connected to the seventh signal terminal; the gate of the tenth PMOS transistor is connected to the clock signal terminal, the source is connected to the power supply terminal, and the drain is connected to the drain of the eleventh PMOS transistor and the fourth signal terminal; the gate of the eleventh PMOS transistor is connected to the first signal terminal; the drain of the twelfth PMOS transistor is connected to the fourth signal terminal, and the gate is connected to the seventh signal terminal; the gate of the thirteenth PMOS transistor is connected to the fourth signal terminal, the source is connected to the power supply terminal, and the drain is connected to the fifth signal terminal. The drain of the seventh NMOS transistor is connected to the third signal terminal, the gate is connected to the clock signal terminal, and the source is connected to the source of the seventh PMOS transistor; the drain of the eighth NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate is connected to the first signal terminal, and the source is connected to the drain of the ninth NMOS transistor; the gate of the ninth NMOS transistor is connected to the clock signal terminal, the gate and source are grounded, and the drain is connected to the sixth signal terminal; the gate of the tenth NMOS transistor is connected to the clock signal terminal, the source is grounded, and the drain is connected to the source of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor is connected to the sixth signal terminal, and the drain is connected to the source of the eleventh PMOS transistor; the source of the twelfth NMOS transistor is connected to the drain of the tenth NMOS transistor, the gate is connected to the first signal terminal, and the drain is connected to the source of the twelfth PMOS transistor; the gate of the thirteenth NMOS transistor is connected to the fourth signal terminal, the source is grounded, and the drain is connected to the fifth signal terminal. When the latch is in a transparent state, the following conditions are met: the tenth PMOS transistor is turned on, the tenth NMOS transistor is turned off, the level output to the fourth signal terminal node is high, and the level output to the fifth signal terminal node is low; when the latch is in a latched state, the following conditions are met: the ninth PMOS transistor and the ninth NMOS transistor are turned off, the seventh PMOS transistor and the seventh NMOS transistor are turned on, the tenth PMOS transistor is turned off, and the tenth NMOS transistor is turned on.

2. The latch as described in claim 1, characterized in that, When the latch is in a transparent state, it includes: In the basic latch, the third PMOS and the third NMOS are turned off, the seventh PMOS and the seventh NMOS are turned off, the ninth PMOS and the ninth NMOS are turned on, the fourteenth PMOS and the fourteenth NMOS are turned on, the sixth signal terminal node is at a low level, and the seventh signal terminal node is at a high level.

3. The latch as described in claim 1, characterized in that, When the latch is in the latched state, it includes: When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-event upset occurs, the latch output is the third signal terminal; if a single-event upset occurs at the nodes of the first and / or second signal terminals, the latch output is the electrical signal corresponding to the second signal terminal. When the first signal terminal in the basic latch is 1 and the second signal terminal is 0, if no single-event upset occurs, the latch output is the third signal terminal; if a single-event upset occurs at the nodes of the first and / or second signal terminals, the latch output is the electrical signal corresponding to the second signal terminal.

4. The latch as described in claim 1, characterized in that, The second detection circuit includes the twenty-ninth PMOS transistor to the thirty-ninth PMOS transistor, and the twenty-ninth NMOS transistor to the thirty-seventh NMOS transistor; The source of the 29th PMOS transistor is connected to the power supply terminal, the gate is connected to the clock signal terminal, and the drain is connected to the source of the 30th PMOS transistor; the gate of the 30th PMOS transistor is connected to the first signal terminal, the drain is connected to the drain of the 31st NMOS transistor, and the source is connected to the 13th signal terminal; the gate of the 31st NMOS transistor is connected to the clock signal terminal, and the source is grounded; the gate of the 32nd PMOS transistor is connected to the 13th signal terminal, the source is connected to the power supply terminal, and the drain is connected to the 14th signal terminal; the drain of the 32nd NMOS transistor is connected to the 14th signal terminal, the source is grounded, and the gate is connected to the 13th signal terminal. The source of the thirty-first PMOS transistor is connected to the power supply terminal, the gate is connected to the clock inverted signal terminal, and the drain is connected to the drain of the thirtieth NMOS transistor; the source of the thirtieth NMOS transistor is connected to the fifteenth signal terminal, the gate is connected to the first signal terminal, and the source is connected to the drain of the twenty-ninth NMOS transistor; the gate of the twenty-ninth NMOS transistor is connected to the clock inverted signal terminal, and the source is grounded; the source of the thirty-third PMOS transistor is connected to the power supply terminal, the gate is connected to the fifteenth signal terminal, and the drain is connected to the sixteenth signal terminal; the source of the thirty-third NMOS transistor is grounded, the gate is connected to the fifteenth signal terminal, and the drain is connected to the sixteenth signal terminal. The gate of the thirty-fourth PMOS transistor is connected to the clock signal terminal, the source to the power supply terminal, and the drain to the fourth signal terminal; the source of the thirty-fifth PMOS transistor is connected to the power supply terminal, the gate to the thirteenth signal terminal, and the drain to the source of the thirty-seventh PMOS transistor; the gate of the thirty-seventh PMOS transistor is connected to the fifteenth signal terminal, and the drain to the fourth signal terminal; the source of the thirty-sixth PMOS transistor is connected to the power supply terminal, the gate to the fourteenth signal terminal, and the drain to the source of the thirty-eighth PMOS transistor; the gate of the thirty-eighth PMOS transistor is connected to the sixteenth signal terminal, and the drain to the fourth signal terminal. The source of the thirty-ninth PMOS transistor is connected to the power supply terminal, the gate is connected to the fourth signal terminal, and the drain is connected to the fifth signal terminal; the drain of the thirty-fourth NMOS transistor is connected to the source of the thirty-fifth NMOS transistor, the gate is connected to the clock signal terminal, and the source is grounded; the drain of the thirty-fifth NMOS transistor is connected to the source of the thirty-sixth NMOS transistor, and the gate is connected to the fourteenth signal terminal; the gate of the thirty-sixth NMOS transistor is connected to the fifteenth signal terminal, and the drain is connected to the fourth signal terminal; the drain of the thirty-seventh NMOS transistor is connected to the fifth signal terminal, the source is grounded, and the gate is connected to the fourth signal terminal. When the latch is in a transparent state, the following conditions are met: the thirty-fourth PMOS transistor is turned on, the thirty-fourth NMOS transistor is turned off, the output to the fourth signal terminal node is high, and the output to the fifth signal terminal node is low; when the latch is in a latched state, the following conditions are met: the twenty-ninth PMOS transistor and the twenty-ninth NMOS transistor are turned off, and the thirty-first PMOS transistor and the thirty-first NMOS transistor are turned on.

5. The latch as described in claim 4, characterized in that, When the latch is in a transparent state, it also includes: In the basic latch, the third PMOS and the third NMOS are turned off, the twenty-ninth PMOS and the twenty-ninth NMOS are turned on, the thirty-first PMOS and the thirty-first NMOS are turned off, the sixth signal terminal node is at a high level, and the seventh signal terminal node is at a low level.

6. The latch as described in claim 4, characterized in that, When the latch is in the latched state, it further includes: When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-event upset occurs, the latch output is the third signal terminal; if a single-event upset occurs at the nodes of the first and / or second signal terminals, the latch output is the electrical signal corresponding to the second signal terminal. When the first signal terminal in the basic latch is 0 and the second signal terminal is 1, if no single-event upset occurs, the latch output is the third signal terminal; if a single-event upset occurs at the nodes of the first and / or second signal terminals, the latch output is the electrical signal corresponding to the second signal terminal.

7. The latch as claimed in claim 1, characterized in that, The basic latch includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a sixth NMOS transistor, and a fourteenth NMOS transistor; the transmission gate includes: a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the first PMOS transistor is connected to the source of the third PMOS transistor, the drain of the first PMOS transistor is connected to the second signal terminal, and the gate of the first PMOS transistor is connected to the first signal terminal; the source of the second PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the second PMOS transistor is connected to the first signal terminal, and the gate of the second PMOS transistor is connected to the second signal terminal; the gate of the third PMOS transistor is connected to the clock inverting signal terminal; the gate of the sixth PMOS transistor is connected to the second signal terminal, the source of the sixth PMOS transistor is connected to the power supply terminal, and the drain of the sixth PMOS transistor is connected to the third signal terminal; the gate of the fourteenth PMOS transistor is connected to the clock signal terminal, the drain of the fourteenth PMOS transistor is connected to the input terminal of the latch, and the source of the fourteenth PMOS transistor is connected to the first signal terminal; The drain of the first NMOS transistor is connected to the second signal terminal, the source of the first NMOS transistor is connected to the source of the third NMOS transistor, and the gate of the first NMOS transistor is connected to the first signal terminal; the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the second NMOS transistor is connected to the first signal terminal, and the gate of the second NMOS transistor is connected to the second signal terminal; the gate of the third NMOS transistor is connected to the clock signal terminal; the gate of the sixth NMOS transistor is connected to the second signal terminal, the source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the third signal terminal; the gate of the fourteenth NMOS transistor is connected to the clock inverting signal terminal, the drain of the fourteenth NMOS transistor is connected to the input terminal of the latch, and the source of the fourteenth NMOS transistor is connected to the first signal terminal. The gate of the fourth PMOS transistor is connected to the fifth signal terminal, the drain of the fourth PMOS transistor is connected to the third signal terminal, and the source of the fourth PMOS transistor is connected to the input terminal of the slave latch; the gate of the fifth PMOS transistor is connected to the fourth signal terminal, the drain of the fifth PMOS transistor is connected to the second signal terminal, and the source of the fifth PMOS transistor is connected to the input terminal of the slave latch; the gate of the fourth NMOS transistor is connected to the fourth signal terminal, the drain of the fourth NMOS transistor is connected to the third signal terminal, and the source of the fourth NMOS transistor is connected to the input terminal of the slave latch; the gate of the fifth NMOS transistor is connected to the fifth signal terminal, the drain of the fifth NMOS transistor is connected to the second signal terminal, and the source of the fifth NMOS transistor is connected to the input terminal of the slave latch.

8. A trigger that resists single-event flip-flops in digital circuits, characterized in that, The trigger includes at least a latch and a slave latch, wherein the latch is a latch resistant to single-event flips in digital circuits as described in any one of claims 1 to 7; The input terminal of the latch is connected to the input terminal of the flip-flop, the output terminal of the latch is connected to the input terminal of the slave latch, and the output terminal of the slave latch is connected to the output terminal of the flip-flop. The latch includes at least a detection circuit and a basic latch; the trigger uses the detection signal of the detection circuit to determine the level switching state of the basic latch, and generates a control signal to control the output of the latch based on the level switching state of the basic latch; The slave latch includes at least a slave detection circuit and a slave basic latch; The trigger uses the detection signal of the slave detection circuit to determine the level switching state of the slave basic latch, and generates a control signal to control the output of the slave latch based on the level switching state of the slave basic latch.

9. The trigger as described in claim 8, characterized in that, The latch further includes a transmission gate, and the slave latch further includes a slave transmission gate; The input terminal of the basic latch is connected to the input terminal of the flip-flop, and the output terminal of the basic latch is connected to the input terminal of the transmission gate; the output terminal of the transmission gate is connected to the input terminal of the slave basic latch, the output terminal of the slave basic latch is connected to the input terminal of the slave transmission gate, and the output terminal of the slave transmission gate is connected to the output terminal of the flip-flop. The basic latch is used to latch the stored level state of the latch; The slave-level basic latch is used to latch the stored level state of the slave-level latch.

10. The trigger as claimed in claim 9, characterized in that, The slave-level basic latch includes: the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the twentieth PMOS transistor, the twenty-eighth PMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the twentieth NMOS transistor, and the twenty-eighth NMOS transistor; the slave-level transmission gate includes: the eighteenth PMOS transistor, the nineteenth PMOS transistor, the eighteenth NMOS transistor, and the nineteenth NMOS transistor; The source of the fifteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor, the drain of the fifteenth PMOS transistor is connected to the ninth signal terminal, and the gate of the fifteenth PMOS transistor is connected to the eighth signal terminal; the source of the sixteenth PMOS transistor is connected to the drain of the seventeenth PMOS transistor, the drain of the sixteenth PMOS transistor is connected to the eighth signal terminal, and the gate of the sixteenth PMOS transistor is connected to the ninth signal terminal; the gate of the seventeenth PMOS transistor is connected to the clock signal terminal; the gate of the twentieth PMOS transistor is connected to the ninth signal terminal, the source of the twentieth PMOS transistor is connected to the power supply terminal, and the drain of the twentieth PMOS transistor is connected to the tenth signal terminal; the gate of the twenty-eighth PMOS transistor is connected to the clock inverting signal terminal, the drain of the twenty-eighth PMOS transistor is connected to the input terminal of the slave basic latch, and the source of the twenty-eighth PMOS transistor is connected to the eighth signal terminal; The drain of the fifteenth NMOS transistor is connected to the ninth signal terminal, the source of the fifteenth NMOS transistor is connected to the source of the seventeenth NMOS transistor, and the gate of the fifteenth NMOS transistor is connected to the eighth signal terminal; the source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, the drain of the sixteenth NMOS transistor is connected to the eighth signal terminal, and the gate of the sixteenth NMOS transistor is connected to the ninth signal terminal; the gate of the seventeenth NMOS transistor is connected to the clock inverting signal terminal; the gate of the twentieth NMOS transistor is connected to the ninth signal terminal, the source of the twentieth NMOS transistor is grounded, and the drain of the twentieth NMOS transistor is connected to the tenth signal terminal; the gate of the twenty-eighth NMOS transistor is connected to the clock signal terminal, the drain of the twenty-eighth NMOS transistor is connected to the input terminal of the slave-level basic latch, and the source of the twenty-eighth NMOS transistor is connected to the eighth signal terminal. The gate of the eighteenth PMOS transistor is connected to the twelfth signal terminal, the drain of the eighteenth PMOS transistor is connected to the tenth signal terminal, and the source of the eighteenth PMOS transistor is connected to the output terminal of the flip-flop; the gate of the nineteenth PMOS transistor is connected to the eleventh signal terminal, the drain of the nineteenth PMOS transistor is connected to the ninth signal terminal, and the source of the nineteenth PMOS transistor is connected to the output terminal of the flip-flop; the gate of the eighteenth NMOS transistor is connected to the eleventh signal terminal, the drain of the eighteenth NMOS transistor is connected to the tenth signal terminal, and the source of the eighteenth NMOS transistor is connected to the output terminal of the flip-flop; the gate of the nineteenth NMOS transistor is connected to the twelfth signal terminal, the drain of the nineteenth NMOS transistor is connected to the ninth signal terminal, and the source of the nineteenth NMOS transistor is connected to the output terminal of the flip-flop.

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