Circuit board and manufacturing method thereof

Abstract

The invention discloses a circuit board and a manufacturing method thereof, and relates to the technical field of electronic circuit additive manufacturing. The manufacturing method comprises the following steps: providing a metal laminated board which comprises a base material and a metal layer attached to the base material; printing conductive paste on the metal layer to form a patterned outer side plating seed layer, and etching the metal layer which is not covered by the outer side plating seed layer to form an inner side plating seed layer; and forming a metal plating layer covering the inner plating seed layer and the outer plating seed layer. According to the application, the patterned outer side plating seed layer is directly printed on the metal layer, then the metal layer which is not covered by the seed layer is etched, the inner side plating seed layer which is consistent with the pattern below the outer side plating seed layer is obtained, and during plating, the metal plating layer is simultaneously and integrally formed on the side wall of the inner side plating seed layer and the outer side plating seed layer in a growing manner; as the inner side plating seed layer is made of metal, stable anchoring points can be formed at the joint of the metal plating layer and the inner side plating seed layer, so that the overall combination stability of the metal plating layer is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit additive manufacturing, and in particular relates to a circuit board and a manufacturing method thereof. Background Art

[0002] At present, electronic additive manufacturing has begun to be gradually applied, mainly by directly forming conductive patterns on the substrate through printing technology. Although compared with traditional etching, it has the advantages of simple process, high efficiency and environmental protection, it still has shortcomings in conductivity, solderability and antioxidant properties. Therefore, many manufacturers have also begun to improve their processes.

[0003] Among them, the improved solution of first using a printing process to directly form a patterned seed layer, and then using a plating process to directly form a patterned metal coating on the basis of the seed layer can effectively solve the shortcomings of the conductive paste in terms of conductivity, solderability, and antioxidant properties. However, the bonding stability of the metal coating on the printed seed layer needs to be improved. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a method for manufacturing a circuit board to solve the problem that the bonding stability of the metal plating layer on the printed seed layer is poor, which affects the reliability of the circuit board.

[0005] In some illustrative embodiments, the method for manufacturing the circuit board includes: providing a metal laminate, which includes: a substrate, and a metal layer attached to the substrate; printing a conductive paste on the metal layer to form a patterned outer plating seed layer, and etching the metal layer not covered by the outer plating seed layer to form an inner plating seed layer; wherein the inner plating seed layer and the outer plating seed layer are overlapped and have the same pattern; plating on the exposed surfaces of the inner plating seed layer and the outer plating seed layer to form a metal plating layer covering the inner plating seed layer and the outer plating seed layer.

[0006] In some optional embodiments, the metal layer includes: a first metal layer attached to one side of the substrate, and a second metal layer attached to the other side of the substrate; the manufacturing method includes: printing a first conductive paste and a second conductive paste on the first metal layer and the second metal layer, respectively, to form a patterned first outer plating seed layer and a second outer plating seed layer, and etching the first metal layer and the second metal layer not covered by the first outer plating seed layer and the second outer plating seed layer to form a first inner plating seed layer and a second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are overlapped and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are overlapped and have the same pattern; a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer is plated on the exposed surfaces of the first inner plating seed layer and the first outer plating seed layer, and a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer is plated on the exposed surfaces of the second inner plating seed layer and the second outer plating seed layer.

[0007] In some optional embodiments, the manufacturing method further includes: forming a blind hole on the metal laminate that penetrates the substrate and the first metal layer and reaches the second metal layer; printing a third conductive paste in the blind hole to form a conductive column that realizes conductive interconnection between the first metal layer and the second metal layer, and then printing the first conductive paste on the first metal layer to form the first outer plating seed layer covering the conductive column; or, printing the first conductive paste on the first metal layer to simultaneously form the conductive column and the first outer plating seed layer.

[0008] In some optional embodiments, before forming the blind hole, a second conductive paste is first printed on the second metal layer to form the second outer plating seed layer; wherein the second outer plating seed layer covers the position of the blind hole relative to the second metal layer; wherein the blind hole does not damage the second metal layer; or, the blind hole damages but does not penetrate the second metal layer; or, the blind hole damages and penetrates the second metal layer.

[0009] In some optional embodiments, after forming the first outer plating seed layer and the second outer plating seed layer, it also includes: forming a through hole on the metal laminate that penetrates the substrate, the first metal layer, the second metal layer, the first outer plating seed layer and the second outer plating seed layer, and forming a conductive structure that realizes conductive interconnection between the first metal layer and the second metal layer at least on the hole wall of the through hole; in the process of integrally forming the first metal plating layer covering the exposed surfaces of the first inner plating seed layer and the first outer plating seed layer, and integrally forming the second metal plating layer covering the exposed surfaces of the second inner plating seed layer and the second outer plating seed layer, it also includes: plating a third metal plating layer on the conductive structure on the hole wall of the through hole; wherein the first metal plating layer, the second metal plating layer and the third metal plating layer are an integral structure.

[0010] In some optional embodiments, the conductive structure is one or more of metal, conductive carbon black, and conductive graphene.

[0011] In some optional embodiments, the metal layer is one or more of gold, silver, copper, iron, nickel, zinc, and aluminum; and / or the metal layer is an ultra-thin metal foil layer with a thickness of 1-10 μm; and / or the conductive paste is a low-temperature conductive paste containing resin and conductive particles; and / or the etching is performed by flash etching.

[0012] Another object of the present invention is to provide a circuit board to solve the problems existing in the prior art.

[0013] In some illustrative embodiments, the circuit board includes: a substrate, an inner plating seed layer attached to the substrate, and an outer plating seed layer attached to the inner plating seed layer; the inner plating seed layer and the outer plating seed layer are stacked and have consistent patterns; and a metal plating layer covering the inner plating seed layer and the outer plating seed layer.

[0014] In some optional embodiments, the inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; the outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are overlapped and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are overlapped and have the same pattern; a conductive column passes through the substrate to connect the first inner plating seed layer and the second inner plating seed layer; the metal plating includes: a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer, and a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer.

[0015] In some optional embodiments, the inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; the outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; a through hole penetrating the substrate, the first inner plating seed layer, the second inner plating seed layer, the first outer plating seed layer and the second outer plating seed layer is formed, at least on the hole wall of the through hole, a conductive structure is formed to realize conductive interconnection between the first inner plating seed layer and the second inner plating seed layer;

[0016] The metal plating layer includes: a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer, a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer, and a third metal plating layer formed on the conductive structure on the wall of the through hole; wherein the first metal plating layer, the second metal plating layer and the third metal plating layer are an integrated structure.

[0017] Compared with the prior art, this application has the following advantages:

[0018] The present application directly prints a patterned outer plating seed layer on the metal layer, and then etches the metal layer not covered by the seed layer, so as to obtain an inner plating seed layer on the metal layer that is stacked with the outer plating seed layer and has the same pattern. At this time, the side wall of the inner plating seed layer is exposed to the outside, so the metal plating layer formed during plating will grow integrally on the side wall of the inner plating seed layer and the outer plating seed layer at the same time. Since the inner plating seed layer is metal, the metal plating layer will form a stable anchor point at the junction with the inner plating seed layer, thereby improving the overall bonding stability of the metal plating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is an example of a process of a method for manufacturing a circuit board in an embodiment of the present invention;

[0020] Figure 2 This is a process example 1 of the method for manufacturing a circuit board in an embodiment of the present invention;

[0021] Figure 3 This is a second process example of the method for manufacturing a circuit board in an embodiment of the present invention;

[0022] Figure 4 This is process example 3 of the method for manufacturing a circuit board in an embodiment of the present invention;

[0023] Figure 5 This is a fourth process example of the method for manufacturing a circuit board in an embodiment of the present invention;

[0024] Figure 6 This is process example 5 of the method for manufacturing a circuit board in an embodiment of the present invention;

[0025] Figure 7 This is a sixth process example of the method for manufacturing a circuit board in an embodiment of the present invention;

[0026] Figure 8 This is a structural example 1 of the method for manufacturing a circuit board in an embodiment of the present invention;

[0027] Fig. 9 This is a second structural example of the method for manufacturing a circuit board in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be noted that the various technical features in the embodiments of the present invention can be combined with each other without conflict.

[0030] The present invention discloses a method for manufacturing a circuit board. Specifically, Figure 1-2 As shown, Figure 1 This is an example of a process of a method for manufacturing a circuit board in an embodiment of the present invention; Figure 2 This is a process example 1 of a method for manufacturing a circuit board in an embodiment of the present invention; the manufacturing method comprises:

[0031] Step S11, providing a metal laminate 100; the metal laminate 100 comprises: a substrate 10, and a metal layer 20 attached to the substrate 10;

[0032] Step S12, printing a conductive paste on the metal layer 20 to form a patterned outer plating seed layer 30, and etching the metal layer 20 not covered by the outer plating seed layer 30 to form an inner plating seed layer 40;

[0033] The inner plating seed layer 40 and the outer plating seed layer 30 are stacked and have the same pattern;

[0034] Step S13 : plating on the exposed surfaces of the inner plating seed layer 40 and the outer plating seed layer 30 to form a metal plating layer 50 covering the inner plating seed layer 40 and the outer plating seed layer 30 .

[0035] Among them, the exposed surface of the outer plating seed layer 30 refers to the surface of the outer plating seed layer 30 other than the bonding surface with the inner plating seed layer 40 (i.e., the outer side surface and side wall), and the exposed surface of the inner plating seed layer 40 refers to the side wall of the inner plating seed layer 40.

[0036] The present application directly prints a patterned outer plating seed layer on the metal layer, and then etches the metal layer not covered by the seed layer, so as to obtain an inner plating seed layer on the metal layer that is stacked with the outer plating seed layer and has the same pattern. At this time, the side wall of the inner plating seed layer is exposed to the outside, so the metal plating layer formed during plating will grow integrally on the side wall of the inner plating seed layer and the outer plating seed layer at the same time. Since the inner plating seed layer is metal, the metal plating layer will form a stable anchor point at the junction with the inner plating seed layer, thereby improving the overall bonding stability of the metal plating layer.

[0037] The substrate in the embodiment of the present invention is used to carry a metal layer on its surface, which is an insulating material. The metal layer can be used to make conductive structures, such as antennas, traces, pads, electrodes, etc.; among them, in the embodiment of the present invention, the metal layer is mainly used to make an inner plating seed layer and as part of the main conductive structure.

[0038] The metal layer in the metal laminate in the embodiment of the present invention can be formed on the substrate by conventional methods such as deposition or lamination; wherein the metal layer can be one or more of gold, silver, copper, iron, nickel, zinc, and aluminum; wherein the substrate can be a hard board or a soft board, and the hard board includes but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (Acrylic), etc.; the soft board includes but is not limited to PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.; exemplarily, the metal laminate uses a copper-clad laminate, the metal layer is copper foil, and the substrate is PI or PET. Wherein, the copper foil is not limited to being formed on PI or PET by gluing lamination or chemical / physical deposition.

[0039] The thickness of the metal layer in the embodiment of the present invention ranges from 0.1 to 100μm, which can be selected according to product performance requirements or process requirements, including but not limited to 0.1μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 15μm, 20μm, 30μm, 40μm, 60μm, 80μm, and 100μm.

[0040] In the embodiments of the present invention, there is no clear restriction on the thickness range of the substrate, and its thickness range can meet the product performance requirements, usually between 0.1 and 500 μm, including but not limited to 0.1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 200 μm, 250 μm, 300 μm, 400 μm, and 500 μm.

[0041] The conductive paste in the embodiment of the present invention can be a low-temperature conductive paste with resin as a bonding phase, or a high-temperature conductive paste with glass frit as a bonding phase. For example, the low-temperature conductive paste in the embodiment of the present invention has the advantages of simple process, low curing temperature and wide range of substrate selection compared to the high-temperature conductive paste.

[0042] The low-temperature conductive paste in the embodiment of the present invention mainly includes resin and conductive filler; wherein, the conductive filler is not limited to one or more of gold, silver, copper, iron, nickel, zinc, aluminum, palladium, conductive carbon black, and graphene; since the final conductive structure in the embodiment of the present invention is a structure in which the inner plating seed layer cooperates with the metal plating layer to wrap the outer plating seed layer, there is no special requirement for the resin in the embodiment of the present invention, as long as it satisfies the requirement that the outer plating seed layer can be stably attached to the metal layer during the etching and plating process, and also because of the above structure, the adhesion of the resin can be sacrificed to a certain extent, thereby increasing the solid content of the conductive filler in the low-temperature conductive paste, thereby improving the plating quality and efficiency, as well as the conductive performance of the final conductive structure.

[0043] The conductive filler in the low-temperature conductive paste in the embodiment of the present invention may also include a low-melting-point metal / alloy that can form an alloy phase with the metal layer and / or the metal plating layer, thereby enhancing the bonding strength between it and the metal layer and / or the metal plating layer; wherein the low-melting-point metal / alloy includes but is not limited to SnBi, Sn, and Bi.

[0044] The first conductive paste, the second conductive paste, and the third conductive paste in the embodiment of the present invention may be made of the same conductive paste, or may be made of conductive pastes with different components, which is not limited in the present application.

[0045] In the embodiment of the present invention, step S12 prints a conductive paste on the metal layer to form a patterned outer plating seed layer (and a printed conductive layer). The method is not limited to printing methods such as silk brushes and inkjet. It can directly form a printed pattern on the metal layer, and after curing, a patterned outer plating seed layer can be obtained. Among them, the thickness of the outer plating seed layer in the embodiment of the present invention can be 0.1 to 100 μm; in a preferred embodiment, the upper limit of the thickness of the outer plating seed layer does not exceed 35 μm, so as to improve the subsequent plating efficiency. Furthermore, the thickness of the outer plating seed layer can be 1 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 22 μm, 25 μm, 30 μm, and 35 μm.

[0046] In the embodiment of the present invention, step S12 is a process of etching the metal layer not covered by the outer plating seed layer to form the inner plating seed layer, which may specifically include:

[0047] Step S121, forming an etching protection layer on the outer plating seed layer, which is consistent with the pattern of the outer plating seed layer and covers the outer plating seed layer;

[0048] Step S122, etching the metal layer to remove the metal layer not covered by the outer plating seed layer, and forming an inner plating seed layer that is stacked with the outer plating seed layer and has the same pattern;

[0049] Step S123 , stripping the etching protection layer to expose the outer plating seed layer.

[0050] The applicant has found that the thickness of the outer plating seed layer formed by the low-temperature conductive paste can reach 2μm to withstand a low degree of etching treatment, namely flash etching (also known as differential etching or rapid etching process); it will basically not be affected in the flash etching process, so in other embodiments, the metal layer can use an ultra-thin metal foil layer (including but not limited to ultra-thin copper-clad laminate) with a thickness range of 0.1-10μm, in conjunction with the flash etching process. During the flash etching process, the outer plating seed layer can be directly used as an etching protection layer to protect the metal layer under its pattern from being removed by flash etching, so there is no need to configure an additional etching protection layer on the outer plating seed layer, which simplifies the process and reduces material consumption; therefore, the thickness of the outer plating seed layer in this embodiment is not less than 2μm.

[0051] The applicant also found that if the thickness of the metal layer is less than 1 μm, the bonding strength between the inner plating seed layer and the metal plating layer will be reduced; and if it is greater than 3 μm, the material cost will increase significantly; therefore, the thickness of the metal layer in the preferred embodiment can be 1-3 μm.

[0052] Although the industry has corresponding definitions for conventional chemical etching and flash etching, in order to facilitate those skilled in the art to quickly understand the present application, the present application briefly describes the two:

[0053] For conventional etching, commonly used acidic etching solutions are mostly cupric chloride (containing cupric chloride, hydrochloric acid, and oxidant) and ferric chloride (containing ferric chloride and hydrochloric acid), and commonly used alkaline etching solutions are mostly ammonia water. In order to ensure thorough etching, the etching solution concentration is relatively high and the etching speed is moderate, which is suitable for thicker copper foils. The continuous etching time is usually from a few minutes to tens of minutes.

[0054] The flash etching process mostly uses an acidic etching solution, such as sulfuric acid-hydrogen peroxide (containing sulfuric acid, hydrogen peroxide, and stabilizer). In order to achieve precise etching, the etching solution concentration is low and the etching speed is fast. It is suitable for ultra-thin copper foil, and the continuous etching time is usually from a few seconds to tens of seconds.

[0055] Those skilled in the art should understand that there are many formulation processes for implementing the above-mentioned conventional etching and flash etching processes. The above-mentioned example descriptions of etching solutions and etching parameters are only used to enable those skilled in the art to quickly understand the difference between the two, and should not have any impact on the scope of application of the technical solution of the present application.

[0056] Furthermore, in order to enable technical personnel in this field to quickly distinguish between the two, the continuous etching time of flash etching in this application is limited to no more than 60 seconds, for example 5 seconds, 10 seconds, 15 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, 60 seconds; the continuous etching time of conventional etching is limited to no less than 180 seconds.

[0057] The metal laminate in the embodiment of the present invention can be a single-sided metal laminate with a metal layer attached to one side of the substrate, or it can be a double-sided metal laminate with metal layers attached to both opposite sides of the substrate; wherein, for the double-sided metal laminate, the above process can be performed on only one of the metal layers, or on both metal layers, so as to obtain the above structure on both sides.

[0058] Among them, for the metal laminate with double-sided metal layers, the metal layers on both sides can use the same metal composition or different metal compositions, and the present application does not limit this.

[0059] The first metal coating layer, the second metal coating layer and the third metal coating layer in the embodiment of the present invention may be made of the same metal component or different metal components.

[0060] Specifically, if Figure 3 As shown, Figure 3 This is a second process example of a circuit board in an embodiment of the present invention; an implementation example for a double-sided metal laminate is disclosed in an embodiment of the present invention; wherein the metal layer 100 in the metal laminate includes: a first metal layer 21 attached to one side of a substrate 10, and a second metal layer 22 attached to the other side of the substrate 10; the manufacturing method includes:

[0061] Step S21, providing the above-mentioned double-sided metal laminate 100;

[0062] Step S22, printing a first conductive paste and a second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and a second outer plating seed layer 32, and etching the first metal layer 21 and the second metal layer 22 not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and a second inner plating seed layer 42;

[0063] The first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern;

[0064] Step S23, plating on the exposed surfaces of the first inner plating seed layer 41 and the first outer plating seed layer 31 to form a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, and plating on the exposed surfaces of the second inner plating seed layer 42 and the second outer plating seed layer 32 to form a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32.

[0065] like Figure 4 As shown, Figure 4This is a third process example of the circuit board in the embodiment of the present invention; in some embodiments, the manufacturing method in the embodiment of the present invention may further include:

[0066] Step S31, providing the above-mentioned double-sided metal laminate 100;

[0067] Step S32, forming a blind hole 60 on the metal laminate 100, which penetrates the substrate 10 and the first metal layer 21 and reaches the second metal layer 22; wherein the process for forming the blind hole 60 is not limited to laser ablation or mechanical drilling;

[0068] Step S33, printing a third conductive paste in the blind hole 60 to form a conductive column 70 for realizing conductive interconnection between the first metal layer 21 and the second metal layer 22;

[0069] Step S34, printing the first conductive paste and the second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and a second outer plating seed layer 32, and etching the first metal layer 21 and the second metal layer 22 not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and a second inner plating seed layer 42; wherein the first outer plating seed layer 31 formed by the first conductive paste covers the surface of the conductive pillar 70 on this side;

[0070] The first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern;

[0071] Step S35, plating on the exposed surfaces of the first inner plating seed layer 41 and the first outer plating seed layer 31 to form a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, and plating on the exposed surfaces of the second inner plating seed layer 42 and the second outer plating seed layer 32 to form a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32.

[0072] In this embodiment, step S33 can be omitted, and the conductive pillar 70 and the first outer plating seed layer 31 are formed while printing the first conductive paste on the first metal layer 21 in step S34. That is, the conductive pillar 70 and the first outer plating seed layer 31 can both be formed by the first conductive paste.

[0073] In this embodiment, conductive interconnection is achieved on both sides of the substrate by plugging the conductive paste. And because the plugging method is directly based on the blind holes on the metal laminate, the process is simple, and there are no problems such as ink leakage and pollution in the through-holes, and it can be applied to the production of flexible boards such as FPC.

[0074] like Figure 5 As shown, Figure 5 This is process example 4 of the manufacturing method in the embodiment of the present invention; in some embodiments, the manufacturing method in the embodiment of the present invention may further include:

[0075] Step S41, providing the above-mentioned double-sided metal laminate 100;

[0076] Step S42, printing a second conductive paste on the second metal layer 22 to form a second outer plating seed layer 32;

[0077] Step S43, forming a blind hole on the metal laminate 100, which penetrates the substrate 10 and the first metal layer 21 and reaches the second metal layer 22; wherein the second outer plating seed layer 32 covers the position of the blind hole 60 relative to the second metal layer 22;

[0078] The blind hole 60 may not damage the second metal layer 22; or, the blind hole 60 may damage but not penetrate the second metal layer 22; or, the blind hole 60 may damage and penetrate the second metal layer 22; wherein the process for forming the blind hole 60 is not limited to laser ablation or mechanical drilling;

[0079] Step S44, printing a third conductive paste in the blind hole 60 to form a conductive column 70 for realizing conductive interconnection between the first metal layer 21 and the second metal layer 22;

[0080] Step S45, printing a first conductive paste on the first metal layer 21 to form a patterned first outer plating seed layer 31, and etching the first metal layer 21 and the second metal layer 22 not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and a second inner plating seed layer 42; wherein the first outer plating seed layer 31 formed by the first conductive paste covers the surface of the conductive pillar 70 on this side;

[0081] The first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern;

[0082] Step S46, plating on the exposed surfaces of the first inner plating seed layer 41 and the first outer plating seed layer 31 to form a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, and plating on the exposed surfaces of the second inner plating seed layer 42 and the second outer plating seed layer 32 to form a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32.

[0083] In this embodiment, step S44 can be omitted, and the conductive pillar 70 and the first outer plating seed layer 31 can be formed while printing the first conductive paste on the first metal layer 21 in step S34. That is, the conductive pillar 70 and the first outer plating seed layer 31 can both be formed by the first conductive paste.

[0084] In this embodiment, before the blind hole is formed, a second outer plating seed layer is first printed on the second metal layer at the corresponding position of the blind hole, which can avoid the problem of laser ablation or mechanical drilling directly penetrating the second metal layer and causing failure of the blind hole structure. The second outer plating seed layer is used to add a layer of insurance on the second metal layer to avoid the difficulty of subsequent plugging, ink leakage, pollution and other problems. It is particularly suitable for embodiments where an ultra-thin metal foil layer is used for the second metal layer.

[0085] like Figure 6 As shown, Figure 6 It is process example five of the manufacturing method in the embodiment of the present invention; in other embodiments, after forming the first outer plating seed layer 31 and the second outer plating seed layer 32, it may also include: forming a through hole 60' on the metal laminate 100 that penetrates the substrate 10, the first metal layer 21, the second metal layer 22, the first outer plating seed layer 31 and the second outer plating seed layer 32, and forming a conductive structure 70' on at least the hole wall of the through hole 60' to achieve conductive interconnection between the first metal layer 21 and the second metal layer 22; forming a first metal plating layer 51 that covers the first inner plating seed layer 41 and the first outer plating seed layer 31 on the exposed surfaces of the two, and forming a second metal plating layer 52 that covers the second inner plating seed layer 42 and the second outer plating seed layer 32 on the exposed surfaces of the two, it also includes: plating a third metal plating layer 53 on the conductive structure 70' on the hole wall of the through hole 60'; wherein the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integrated structure.

[0086] Specifically, the method for manufacturing a circuit board in an embodiment of the present invention may include:

[0087] Step S51, providing the above-mentioned double-sided metal laminate 100;

[0088] Step S52, printing a first conductive paste and a second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and a second outer plating seed layer 32, and etching the first metal layer 21 and the second metal layer 22 not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and a second inner plating seed layer 42;

[0089] Wherein, the first outer plating seed layer 31 and the second outer plating seed layer 32 have an overlapping area in the horizontal direction of the metal laminate 100;

[0090] Step S53, forming a through hole 60' on the metal laminate 100, which penetrates the substrate 10, the first inner plating seed layer 41, the second inner plating seed layer 42, the first outer plating seed layer 31 and the second outer plating seed layer 32, and forming a conductive structure 70' on at least the hole wall of the through hole 60' to achieve conductive interconnection between the first inner plating seed layer 41 and the second inner plating seed layer 42;

[0091] Step S54, integrally forming a first metal plating layer 51 covering the exposed surfaces of the first inner plating seed layer 41 and the first outer plating seed layer 31, integrally forming a second metal plating layer 52 covering the exposed surfaces of the second inner plating seed layer 42 and the second outer plating seed layer 32, and plating a third metal plating layer 53 on the conductive structure 70' on the hole wall of the through hole 60'; wherein the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integral structure.

[0092] The conductive structure 70 ′ may also be formed on the first inner plating seed layer 41 , the second inner plating seed layer 42 , the first outer plating seed layer 31 and the second outer plating seed layer 32 at the same time.

[0093] The conductive structure in the embodiment may be one or more of metal, conductive carbon black, and conductive graphene, and may be formed by one or more conductive pastes containing metal particles (i.e., through-hole printing process), conductive carbon black (i.e., black hole process), and conductive graphene (i.e., black shadow process).

[0094] like Figure 7 As shown, Figure 7 This is a sixth process example of the manufacturing method in the embodiment of the present invention; in other embodiments, the manufacturing method of the circuit board in the embodiment of the present invention may include:

[0095] Step S61, providing the above-mentioned double-sided metal laminate 100;

[0096] Step S62, printing a first conductive paste and a second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and a second outer plating seed layer 32;

[0097] Wherein, the first outer plating seed layer 31 and the second outer plating seed layer 32 have an overlapping area in the horizontal direction of the metal laminate 100;

[0098] Step S63, forming a through hole 60' on the metal laminate 100, which penetrates the substrate 10, the first metal layer 21, the second metal layer 22, the first outer plating seed layer 31 and the second outer plating seed layer 32, and forming a conductive structure 70' (conductive carbon black or conductive graphene) of conductive interconnection on the hole wall of the through hole 60' and on the surface of the first metal layer 21, the second metal layer 22, the first outer plating seed layer 31 and the second outer plating seed layer 32;

[0099] Step S64, etching the first metal layer 21, the second metal layer 22 and the conductive carbon black or conductive graphene thereon which are not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 by a flash etching process to form a first inner plating seed layer 41 and a second inner plating seed layer 42;

[0100] At this time, a conductive structure 70' of conductive carbon black or conductive graphene is formed on the first outer plating seed layer 31, the second outer plating seed layer 32, the first inner plating seed layer 41, the second inner plating seed layer 42 and the wall of the through hole 60', except for the side walls of the first inner plating seed layer 41 and the second inner plating seed layer 42 away from the through hole 60'.

[0101] Step S65, integrally forming a first metal plating layer 51 covering the exposed surfaces of the first inner plating seed layer 41 and the first outer plating seed layer 31, integrally forming a second metal plating layer 52 covering the exposed surfaces of the second inner plating seed layer 42 and the second outer plating seed layer 32, and plating forming a third metal plating layer 53 on the conductive structure 70' on the hole wall of the through hole 60'; wherein the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integral structure.

[0102] In this embodiment, the blind hole process can be replaced by a through hole process, and then combined with the traditional black hole / black shadow process, the first metal layer and the second metal layer not covered by the first outer plating seed layer and the second outer plating seed layer can be etched by the flash etching process, without the need to set up other additional masks, and the first inner plating seed layer and the second inner plating seed layer formed still have a metal bonding interface with the metal plating layer as an anchor point for the metal plating layer. At the same time, the flash etching process is used in this embodiment, so the first metal layer and the second metal layer should use the above-mentioned ultra-thin metal foil layer range.

[0103] Among them, one or more of the conductive carbon black and conductive graphene in the conductive structure of the embodiment can be formed by one or more conductive pastes of conductive carbon black (ie, black hole process) and conductive graphene (ie, black shadow process).

[0104] Another object of the present invention is to provide a circuit board, which can be obtained by any of the above-mentioned manufacturing methods.

[0105] The embodiment of the present invention discloses a circuit board, specifically, Figure 8 As shown, Figure 8 This is a structural example 1 of a circuit board in an embodiment of the present invention; the circuit board comprises: a substrate 10, an inner plating seed layer 40 attached to the substrate 10, and an outer plating seed layer 30 attached to the inner plating seed layer 40; the inner plating seed layer 40 and the outer plating seed layer 30 are stacked and have the same pattern; and a metal plating layer 50 covering the inner plating seed layer 40 and the outer plating seed layer 30. There is a metal bonding interface between the metal plating layer 50 and the inner plating seed layer 40.

[0106] In some embodiments, the inner plating seed layer 40 may include: a first inner plating seed layer 41 attached to one side of the substrate 10, and a second inner plating seed layer 42 attached to the other side of the substrate 10; the outer plating seed layer 30 may include: a first outer plating seed layer 31 attached to the first inner plating seed layer 41, and a second outer plating seed layer 32 attached to the second inner plating seed layer 42; wherein the first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern; the metal plating layer includes: a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, and a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32.

[0107] In some embodiments, the circuit board may further include: a conductive column 70 penetrating through the substrate 10 and connecting the first inner plating seed layer 41 and the second inner plating seed layer 42 .

[0108] The present invention also discloses a circuit board, specifically, Fig. 9 As shown, Fig. 9This is a second structural example of a circuit board in an embodiment of the present invention; the circuit board comprises: a substrate 10, a first inner plating seed layer 41 attached to one side of the substrate 10, and a second inner plating seed layer 42 attached to the other side of the substrate 10; a first outer plating seed layer 31 attached to the first inner plating seed layer 41, and a second outer plating seed layer 32 attached to the second inner plating seed layer 42; wherein the first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern; the substrate 10, the first inner plating seed layer 41, the second inner plating seed layer 42, the first outer plating seed layer The through hole 60' of the through hole 60' is provided with a first inner plating seed layer 41 and a second outer plating seed layer 32, and at least a conductive structure 70' is formed on the hole wall of the through hole 60' to realize conductive interconnection between the first inner plating seed layer 41 and the second inner plating seed layer 42; the metal plating layer includes: a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32, and a third metal plating layer 53 formed on the conductive structure 70' on the hole wall of the through hole 60'; wherein the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integrated structure (i.e., a complete metal plating layer). There is a metal bonding interface between the metal plating layer and the inner plating seed layer.

[0109] In some embodiments, the conductive structure may further cover the surfaces of the first outer plating seed layer and the second outer plating seed layer.

[0110] The material selection and related dimensional parameters of the circuit board in the embodiment of the present invention can refer to the embodiment of the manufacturing method of the present invention, and will not be repeated here.

[0111] In the embodiments of the present invention, "the pattern of the inner plating seed layer and the outer plating seed layer are consistent" mainly refers to that the pattern contours between the inner plating seed layer and the outer plating seed layer are basically consistent, which may be limited by the process type and process accuracy (and side etching) to produce a certain impact: for example, when the outer plating seed layer is used as a mask for the metal layer in the flash etching process, excluding the influence of process accuracy (and side etching), it can be considered that the patterns of the inner plating seed layer and the outer plating seed layer are completely consistent; and when a traditional etching protection layer is formed on the outer plating seed layer as a mask for the metal layer in the traditional conventional etching process, excluding the influence of process accuracy (and side etching) and the etching protection layer completely covers the side wall of the outer plating seed layer, the inner plating seed layer is limited by the influence of the thickness of the etching protection layer, slightly larger than the pattern of the outer plating seed layer, and the thickness of the etching protection layer is usually very thin and its influence can be ignored. In some embodiments, for the above situation, it can be considered that the contour of the outer plating seed layer plus the range of the thickness of the etching protection layer is consistent with the pattern of the inner plating seed layer.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a circuit board, characterized in that: include: A metal laminate is provided, comprising: a substrate, and a metal layer attached to the substrate; Printing a conductive paste on the metal layer to form a patterned outer plating seed layer, and etching the metal layer not covered by the outer plating seed layer to form an inner plating seed layer; Wherein, the inner plating seed layer and the outer plating seed layer are stacked and have the same pattern; A metal plating layer covering the inner plating seed layer and the outer plating seed layer is formed by plating on the exposed surfaces of the inner plating seed layer and the outer plating seed layer.

2. The method according to claim 1, characterized in that: The metal layer includes: a first metal layer attached to one side of the substrate, and a second metal layer attached to the other side of the substrate; The production method comprises: Printing a first conductive paste and a second conductive paste on the first metal layer and the second metal layer, respectively, to form a patterned first outer plating seed layer and a second outer plating seed layer, and etching the first metal layer and the second metal layer not covered by the first outer plating seed layer and the second outer plating seed layer to form a first inner plating seed layer and a second inner plating seed layer; Wherein, the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; A first metal coating is formed by coating the exposed surfaces of the first inner coating seed layer and the first outer coating seed layer to cover the first inner coating seed layer and the first outer coating seed layer, and a second metal coating is formed by coating the exposed surfaces of the second inner coating seed layer and the second outer coating seed layer to cover the second inner coating seed layer and the second outer coating seed layer.

3. The method according to claim 2, characterized in that: Also includes: forming a blind hole on the metal laminate that penetrates through the substrate and the first metal layer and reaches the second metal layer; A third conductive paste is printed in the blind hole to form a conductive column for realizing conductive interconnection between the first metal layer and the second metal layer, and then the first conductive paste is printed on the first metal layer to form the first outer plating seed layer covering the conductive column; or, the first conductive paste is printed on the first metal layer to simultaneously form the conductive column and the first outer plating seed layer.

4. The method according to claim 3, characterized in that: Before forming the blind hole, firstly print a second conductive paste on the second metal layer to form the second outer plating seed layer; wherein the second outer plating seed layer covers the position of the blind hole relative to the second metal layer; The blind hole does not damage the second metal layer; or the blind hole damages but does not penetrate the second metal layer; or the blind hole damages and penetrates the second metal layer.

5. The method according to claim 2, characterized in that: After forming the first outer plating seed layer and the second outer plating seed layer, the method further comprises: Forming a through hole on the metal laminate that penetrates the substrate, the first metal layer, the second metal layer, the first outer plating seed layer, and the second outer plating seed layer, and forming a conductive structure that realizes conductive interconnection between the first metal layer and the second metal layer at least on the hole wall of the through hole; The process of integrally forming a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer on the exposed surfaces thereof, and integrally forming a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer on the exposed surfaces thereof, further includes: A third metal coating is formed by plating on the conductive structure on the hole wall of the through hole; wherein the first metal coating, the second metal coating and the third metal coating are an integrated structure.

6. The method according to claim 5, characterized in that: The conductive structure is one or more of metal, conductive carbon black, and conductive graphene.

7. The method according to any one of claims 1 to 6, characterized in that: The metal layer is one or more of gold, silver, copper, iron, nickel, zinc and aluminum; and / or, The metal layer is an ultra-thin metal foil layer with a thickness of 1-10 μm; and / or, The conductive paste is a low-temperature conductive paste comprising a resin and conductive particles; and / or, The etching is performed by flash etching.

8. A circuit board, characterized in that: include: A substrate, an inner plating seed layer attached to the substrate, and an outer plating seed layer attached to the inner plating seed layer; the inner plating seed layer and the outer plating seed layer are stacked and have consistent patterns; and a metal plating layer covering the inner plating seed layer and the outer plating seed layer.

9. The circuit board according to claim 8, characterized in that: The inner plating seed layer comprises: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; The outer plating seed layer comprises: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; Wherein, the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; A conductive column penetrating through the substrate and connecting the first inner plating seed layer and the second inner plating seed layer; The metal plating layer includes: a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer, and a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer.

10. The circuit board according to claim 8, characterized in that: The inner plating seed layer comprises: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; The outer plating seed layer comprises: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; Wherein, the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; A through hole penetrating the substrate, the first inner plating seed layer, the second inner plating seed layer, the first outer plating seed layer and the second outer plating seed layer, at least forming a conductive structure on the hole wall of the through hole to realize conductive interconnection between the first inner plating seed layer and the second inner plating seed layer; The metal plating layer includes: a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer, a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer, and a third metal plating layer formed on the conductive structure on the wall of the through hole; wherein the first metal plating layer, the second metal plating layer and the third metal plating layer are an integrated structure.

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