Layout of power device, power device and forming method thereof

Abstract

The invention provides a layout of a power device, the power device and a forming method of the power device, a plurality of redundant active regions are arranged in an insulation region outside an active region in a substrate of the layout of the power device, and a pattern of the layout of the power device is transferred to the substrate in the forming method of the power device; then executing an LOCOS process so as to form a field oxide layer in the redundant active region and an insulating region outside the active region; and performing a chemical mechanical polishing process to flatten the top surface of the field oxide layer. Because the area of the insulation region in the high-voltage power device is large, a plurality of redundant active regions are arranged in the insulation region, namely, the large-area insulation region is divided into a plurality of small-area insulation regions, and field oxide layers are not formed on the surfaces of the active regions and the redundant active regions in the LOCOS process, the field oxide layers are not formed on the surfaces of the active regions and the redundant active regions in the chemical mechanical grinding process, and the field oxide layers are not formed on the surfaces of the active regions and the redundant active regions. The difficulty of the chemical mechanical grinding process is reduced, and the thickness uniformity of the chemical mechanical grinding process of the field oxide layer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a layout of a power device, a power device and a method for forming the same. Background Art

[0002] In the technology nodes of 0.25um and below, shallow trench isolation technology is widely used. In the manufacturing process of shallow trench isolation structure, the planarization process is a key factor affecting the performance of shallow trench isolation structure. Usually, the technology used in the planarization process is the chemical mechanical polishing (CMP) process. However, according to the characteristics of the chemical mechanical polishing process, the polishing rate is related to the pattern of the bottom layer, that is, the larger the area of ​​the layer to be polished, the smaller the polishing rate; conversely, the smaller the area of ​​the layer to be polished, the greater the polishing rate. Due to the uneven polishing rate of the semiconductor wafer surface, some semiconductor wafers are over-polished, while some semiconductor wafer surfaces are under-polished, making speed control very difficult. Therefore, when using shallow trench isolation, there are certain requirements for the area of ​​the active area. This is because when depositing the shallow trench isolation structure, the oxide layer will also be deposited on the active area. When the area of ​​the active area is too large, a large area and thick oxide layer is usually formed on the active area, which affects the subsequent chemical mechanical polishing process.

[0003] Due to the characteristics of high current and high voltage, the isolation layer of power devices must be large in area and thick in thickness. This is especially true for IGBT (Insulate-Gate Bipolar Transistor) devices. Therefore, the IGBT process requires the use of both LOCOS (Local Oxidation of Silicon) and CMP (Chemical Mechanical Polishing) processes to improve the uniformity of the thickness of the isolation field oxide layer in the plane. Specifically, the LOCOS process is usually a normal Si loss-free process or a recess locos process. Due to the gap (about 16,000 angstroms) formed between the FOX (Field Oxide) area and the active area, the subsequent Gate poly (polycrystalline silicon gate) morphology after etching is affected. Therefore, a chemical mechanical polishing process is added to reduce the gap. However, if the area of ​​a large field oxide layer is too large, it will affect the thickness uniformity of the chemical mechanical polishing process. Summary of the invention

[0004] The object of the present invention is to provide a layout of a power device, a power device and a method for forming the same, so as to solve the problem of thickness uniformity of chemical mechanical polishing of a field oxide layer region in the power device.

[0005] In order to solve the above technical problems, the present invention provides a layout of a power device, including a substrate, an active area in the substrate and an insulating area outside the active area, wherein a plurality of redundant active areas are arranged in the insulating area.

[0006] Optionally, the redundant active area is in the shape of a rectangle or a square.

[0007] Optionally, a ratio of line width to spacing of the redundant active area is 1:10 to 10:1.

[0008] Optionally, the spacing between adjacent redundant active areas meets a preset critical dimension threshold.

[0009] Optionally, the substrate also includes a well region, the well region includes an active region and a redundant active region, a gate is formed on the active region of the well region, the spacing between the active region and the adjacent redundant active region meets the critical dimension preset threshold, the spacing between the gate and the adjacent redundant active region meets the critical dimension preset threshold, and the distance between the redundant active region and the boundary of the well region meets the critical dimension preset threshold.

[0010] Optionally, the substrate includes a cutting path, and a distance between the redundant active area and the cutting path meets a preset threshold of a critical dimension.

[0011] Optionally, the preset threshold of the critical dimension is 0.1um to 100um.

[0012] Based on the same inventive concept, the present invention also provides a method for forming a power device, which uses any of the above-mentioned patterns of the power device to transfer to a substrate, comprising:

[0013] Providing a substrate, wherein the substrate defines an active region and an insulating region outside the active region;

[0014] Disposing a plurality of redundant active regions in the insulating region;

[0015] Performing a LOCOS process to form a field oxide layer in the redundant active region and the insulating region outside the active region;

[0016] A chemical mechanical polishing process is performed to planarize a top surface of the field oxide layer.

[0017] Optionally, before performing the LOCOS process, the process includes:

[0018] forming a pad oxide layer and a hard mask layer in sequence, wherein the pad oxide layer covers the active area, the redundant active area and the insulating area in the substrate;

[0019] forming a photoresist layer, wherein the photoresist layer covers the hard mask layer;

[0020] Performing a photolithography process and a development process to form a patterned photoresist layer, wherein the patterned photoresist layer covers the hard mask layer of the active area and the redundant active area and exposes the hard mask layer outside the active area and the redundant active area;

[0021] An etching process is performed, using the patterned photoresist layer as a mask, and etching the hard mask layer and the pad oxide layer in sequence until the surface of the substrate outside the active area and the redundant active area is exposed.

[0022] Based on the same inventive concept, the present invention further provides a power device, characterized in that it is manufactured using any of the above-mentioned methods for forming a power device.

[0023] In the layout of the power device, the power device and the method for forming the same provided by the present invention, a plurality of redundant active regions are arranged in the insulating region outside the active region in the substrate of the layout of the power device, and in the method for forming the power device, the pattern of the layout of the power device is transferred to the substrate; then a LOCOS process is performed to form a field oxide layer in the redundant active region and the insulating region outside the active region; and a chemical mechanical polishing process is performed to flatten the top surface of the field oxide layer. Since the area of ​​the insulating region in the power device is relatively large, a plurality of redundant active regions are arranged in the insulating region, that is, the large-area insulating region is divided into a plurality of small-area insulating regions, and in the LOCOS process, the surface of the active region and the redundant active region will not form a field oxide layer, therefore, in the chemical mechanical polishing process, the difficulty of the chemical mechanical polishing process is reduced, and the thickness uniformity of the chemical mechanical polishing process of the field oxide layer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 It is a schematic diagram of the layout of a power device according to an embodiment of the present invention.

[0026] Figure 2 It is a flow chart of a method for forming a power device according to an embodiment of the present invention.

[0027] Figures 3 to 8 It is a structural schematic diagram of corresponding steps of the method for forming a power device according to an embodiment of the present invention.

[0028] In the attached figure:

[0029] 10-substrate; 11-well region; 12-active region; 13-insulating region; 14-redundant active region; 15-gate; 16-redundant well region; 17-cutting road;

[0030] 101 - pad oxide layer; 102 - hard mask layer; 103 - photoresist layer; 103a - patterned photoresist layer; 104 - field oxide layer. DETAILED DESCRIPTION

[0031] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0032] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Figure 1 Schematic diagram of the layout of the power device of the embodiment of the present invention. Figure 1As shown, this embodiment provides a layout of a power device, including a substrate 10, an active area 12 in the substrate 10, and an insulating area 13 located outside the active area 12, wherein a plurality of redundant active areas 14 are arranged in the insulating area 13. In some embodiments, the active area 12 is arranged separately. In some embodiments, the active area 12 is located in the well area 11. In other embodiments, a redundant well area 16 is also arranged in the substrate 10. A gate 15 is arranged on the active area 12. And the substrate 10 also includes a cutting path. The shape of the redundant active area 14 is a rectangle or a square. In this embodiment, the shape of the redundant active area 14 is, for example, a square, the side length (line width, Line) is W, and the spacing (space) between adjacent redundant active areas 14 is S. The ratio range of the line width W of the redundant active area 14 to the spacing S is, for example, 1:10 to 10:1. And the spacing S between adjacent redundant active areas 14 meets the preset threshold of the critical dimension (Critical Dimension, CD). The distance m between the redundant active area 14 and the boundary of the well area 11 meets the preset threshold of critical dimension. The spacing d2 between the gate 15 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The spacing d1 between the active area 12 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The spacing d3 between the well area 11 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The distance d4 between the redundant active area 14 and the cutting road 17 meets the preset threshold of critical dimension. The spacing d5 between the redundant well area 16 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The preset threshold of critical dimension is, for example, 0.1um to 100um. In this embodiment, by setting the redundant active area 14 in the insulating area, the problem of greater grinding difficulty and poor thickness uniformity of the chemical mechanical polishing process when the field oxide layer (Field Oxide, FOX) of the insulating area is flattened is solved.

[0034] Figure 2 FIG. 1 is a flow chart of a method for forming a power device according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for forming a power device, including:

[0035] Step S10, providing a substrate, wherein the substrate is defined with an active region and an insulating region outside the active region;

[0036] Step S20, setting a plurality of redundant active areas in the insulating area;

[0037] Step S30, performing a LOCOS process to form a field oxide layer in the redundant active area and the insulating area outside the active area;

[0038] Step S40 , performing a chemical mechanical polishing process to planarize the top surface of the field oxide layer.

[0039] Figures 3 to 8 1 is a schematic diagram of the structure of the corresponding steps of the method for forming a power device according to an embodiment of the present invention. Figures 3 to 8 The specific embodiments of the present invention are described in detail.

[0040] like Figure 3 As shown, a substrate 10 is provided. The substrate 10 can provide an operating platform for subsequent processes. The substrate 10 can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip or a wafer processed by an epitaxial growth process. In detail, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate.

[0041] Please continue to refer to Figure 3, an active area 12 and an insulating area 13 outside the active area 12 are defined on the substrate 10. In some embodiments, the active area 12 is located in the well area 11, and the well area 11 includes the active area 12 and the redundant active area 14. The substrate 10 in this embodiment is used to form a power device, and the power device is, for example, an IGBT device. Since the withstand voltage in the power device is required to be high, the area of ​​the insulating area in the power device is large. The large-area insulating area is more difficult for the chemical mechanical polishing process. Therefore, in this embodiment, a plurality of redundant active areas 14 are arranged in the insulating area 13, and the shape of the redundant active area 14 is a rectangle or a square. In this embodiment, the shape of the redundant active area 14 is, for example, a square, the side length (line width, Line) is W, and the spacing (space) between adjacent redundant active areas 14 is S. The ratio range of the line width W of the redundant active area 14 to the spacing S is, for example, 1:10 to 10:1. And the spacing S between adjacent redundant active areas 14 meets the preset threshold of critical dimension (Critical Dimension, CD). The distance m between the redundant active area 14 and the boundary of the well area 11 meets the preset threshold of critical dimension. A gate 15 is formed on the active area 12, and the spacing d2 between the gate 15 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The spacing d1 between the active area 12 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The spacing d3 between the well area 11 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The substrate 10 includes a cutting road 17, and the distance d4 between the redundant active area 14 and the cutting road 17 meets the preset threshold of critical dimension. And a redundant well area 16 is also provided in the substrate 10, and the spacing d5 between the redundant well area 16 and the adjacent redundant active area 14 meets the preset threshold of critical dimension. The preset threshold of critical dimension is 0.1um to 100um. In this embodiment, a redundant active region 14 is provided in the insulating region to solve the problem of greater polishing difficulty and poor thickness uniformity in the chemical mechanical polishing process when planarizing the field oxide (FOX) layer in the insulating region.

[0042] Please continue to refer to Figure 3 , a pad oxide layer 101 and a hard mask layer 102 are formed in sequence, wherein the pad oxide layer 101 covers the active area 12, the insulating area 13 and the redundant active area 14 in the insulating area 13 in the substrate 10. The material of the pad oxide layer 101 is an oxide layer, which is used to relieve the stress between the hard mask layer 102 and the substrate 10. The material of the hard mask layer 102 is silicon nitride, which is used to protect the active area 12 and the redundant active area 14 from being etched during the etching process. The pad oxide layer 101 and the hard mask layer 102 can be formed by a chemical vapor deposition process. Then, a photoresist layer 103 is formed, and the photoresist layer 103 covers the hard mask layer 102.

[0043] like Figure 4 As shown, a photolithography process and a development process are performed to transfer the pattern of the layout of the power device to the photoresist layer 103 to form a patterned photoresist layer 103a. The patterned photoresist layer 103a covers the hard mask layer 103 of the active area 12 and the redundant active area 14 and exposes the hard mask layer 103 outside the active area 12 and the redundant active area 14.

[0044] Figure 4 is a cross-sectional view of a certain part of the substrate 10, combined with Figure 1 It can be seen from the layout of the power device that the substrate 10 also includes a redundant well region 16. Therefore, the patterned photoresist layer 103a covers the hard mask layer 103 of the active area 12, the redundant active area 14 and the redundant well region 16 and exposes the hard mask layer 103 outside the active area 12, the redundant active area 14 and the redundant well region 16.

[0045] like Figure 5 As shown, an etching process is performed, using the patterned photoresist layer 103a as a mask, and sequentially etching the hard mask layer 102 and the pad oxide layer 101 until the surface of the substrate 10 outside the active area 12 and the redundant active area 14 is exposed. The etching process is, for example, a dry etching process.

[0046] like Figure 6 As shown, after the etching process is performed, if the patterned photoresist layer 103a has not been completely consumed, a photoresist removal process is required, and an ashing process or a stripping method is usually used to remove the remaining patterned photoresist layer 103a.

[0047] like Figure 7 As shown, a LOCOS process is performed to form a field oxide layer 104 in the insulating area outside the redundant active area 14 and the active area 12; the LOCOS (Local Oxidation of Silicon) process uses silicon nitride as a hard mask layer to achieve selective oxidation of silicon, and a thick field oxide is embedded between the active area 12 and the redundant active area 14 of the power device, thereby forming isolation between the active devices. The top surface of the formed field oxide layer 104 is higher than the top surface of the hard mask layer 102.

[0048] like Figure 8As shown, a chemical mechanical polishing process is performed to flatten the top surface of the field oxide layer 104. Since the withstand voltage in the power device is required to be high, the area of ​​the insulating region 13 in the power device is relatively large. The large-area insulating region is more difficult to process with chemical mechanical polishing. In this embodiment, a large-area insulating region is divided into a plurality of small-area insulating regions by setting a plurality of redundant active regions 14 in the insulating region, and the spacing between adjacent redundant active regions 14 meets the preset threshold of the critical size, which does not affect the isolation effect of the field oxide layer in the insulating region 13, reduces the difficulty of the chemical mechanical polishing process of the field oxide layer in the insulating region, and improves the thickness uniformity of the chemical mechanical polishing process of the field oxide layer in the insulating region, that is, solves the problem of greater grinding difficulty and poor thickness uniformity of the chemical mechanical polishing process when the field oxide layer (Field Oxide, FOX) in the insulating region is flattened.

[0049] like Figure 8 As shown, the present invention also provides a power device, which is made by any of the above-mentioned power device forming methods. It includes a substrate 10, an active area 12 and an insulating area 13 in the substrate 10. A plurality of redundant active areas 14 are arranged in the insulating area 13. A field oxide layer 104 is formed on the substrate 10 in the insulating area 13 between adjacent active areas 12 and redundant active areas 14.

[0050] In summary, in the layout of the power device, the power device and the method for forming the same provided by the embodiment of the present invention, a plurality of redundant active regions are set in the insulating region outside the active region in the substrate of the layout of the power device, and in the method for forming the power device, the pattern of the layout of the power device is transferred to the substrate; then the LOCOS process is performed to form a field oxide layer in the redundant active region and the insulating region outside the active region; and a chemical mechanical polishing process is performed to flatten the top surface of the field oxide layer. Since the area of ​​the insulating region in the power device is relatively large, a plurality of redundant active regions are set in the insulating region, that is, the large-area insulating region is divided into a plurality of small-area insulating regions, and in the LOCOS process, the surface of the active region and the redundant active region will not form a field oxide layer, therefore, in the chemical mechanical polishing process, the difficulty of the chemical mechanical polishing process is reduced, and the thickness uniformity of the field oxide layer in the chemical mechanical polishing process is improved.

[0051] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A layout of a power device, characterized in that: The invention comprises a substrate, an active area in the substrate and an insulating area outside the active area, wherein a plurality of redundant active areas are arranged in the insulating area.

2. The layout of the power device according to claim 1, characterized in that: The redundant active area is in a rectangular or square shape.

3. The layout of the power device according to claim 1, characterized in that: The ratio of the line width to the spacing of the redundant active area is 1:10 to 10:

1.

4. The layout of the power device according to claim 1, characterized in that: The spacing between adjacent redundant active regions meets a preset critical dimension threshold.

5. The layout of the power device according to claim 1, characterized in that: The substrate also includes a well region, the well region includes an active region and a redundant active region, a gate is formed on the active region of the well region, a spacing between the active region and an adjacent redundant active region satisfies a critical dimension preset threshold, a spacing between the gate and an adjacent redundant active region satisfies a critical dimension preset threshold, and a distance between the redundant active region and a boundary of the well region satisfies a critical dimension preset threshold.

6. The layout of the power device according to claim 1, characterized in that: The substrate includes a cutting path, and the distance between the redundant active area and the cutting path meets a preset critical dimension threshold.

7. The layout of a power device according to any one of claims 4 to 6, characterized in that: The preset threshold of the critical dimension is 0.1um to 100um.

8. A method for forming a power device, characterized in that: Transferring the pattern of the layout of the power device according to any one of claims 1 to 7 onto a substrate comprises: Providing a substrate, wherein the substrate defines an active region and an insulating region outside the active region; Disposing a plurality of redundant active regions in the insulating region; Performing a LOCOS process to form a field oxide layer in the redundant active region and the insulating region outside the active region; A chemical mechanical polishing process is performed to planarize a top surface of the field oxide layer.

9. The method for forming a power device according to claim 8, characterized in that: Before performing the LOCOS process, the process includes: forming a pad oxide layer and a hard mask layer in sequence, wherein the pad oxide layer covers the active area, the redundant active area and the insulating area in the substrate; forming a photoresist layer, wherein the photoresist layer covers the hard mask layer; Performing a photolithography process and a development process to form a patterned photoresist layer, wherein the patterned photoresist layer covers the hard mask layer of the active area and the redundant active area and exposes the hard mask layer outside the active area and the redundant active area; An etching process is performed, using the patterned photoresist layer as a mask, and etching the hard mask layer and the pad oxide layer in sequence until the surface of the substrate outside the active area and the redundant active area is exposed.

10. A power device, characterized in that: The power device is manufactured by the method for forming a power device as claimed in any one of claims 8 to 9.

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