Class D amplification circuit
By using four-terminal stacked ceramic capacitors of two capacitors in the low-pass filter circuit of the Class D amplification circuit, the total amount of capacitors is suppressed, the problem of the change in the cutoff frequency of the low-pass filter is solved, and the stable output of the sound signal is achieved.
Patent Information
- Application Number
- CN202380071142.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-11-24
- Filing Date
- 2023-09-01
- Publication Date
- 2025-05-13
AI Technical Summary
In a Class D amplification circuit, the capacitor capacitance of the low-pass filter circuit changes according to the applied voltage, resulting in a change in the cutoff frequency of the low-pass filter and the output sound signal characteristics are unstable.
A low-pass filter circuit with two capacitors is adopted, wherein the two capacitors are composed of a four-terminal stacked ceramic capacitor. Through a specific connection between a plurality of internal electrodes and an external electrode, the total amount of capacitors is suppressed and the cutoff frequency is stabilized.
Even if the voltage of the input signal changes, the desired characteristic sound signal can still be output, which improves the stability and quality of the signal.
Smart Images
Figure CN119999086A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a class D amplifier circuit. Background Art
[0002] It is known that a class D amplifier circuit amplifies a sound signal and outputs it to a load such as a speaker. For example, a class D amplifier circuit of a PWM modulation method is described in Patent Document 1. The class D amplifier circuit includes a PWM modulation circuit, a drive circuit, and a low-pass filter. The PWM modulation circuit is a circuit that outputs a PWM modulation signal. The drive circuit is a circuit that amplifies the PWM modulation signal and outputs the amplified PWM modulation signal. The low-pass filter circuit is a circuit that outputs an analog sound signal by removing the high-frequency component of the amplified PWM modulation signal. The low-pass filter circuit is composed of an inductor and a capacitor. The output analog sound signal is supplied to the load. When the analog signal is a signal representing sound and the load is a speaker, the load generates the sound represented by the analog signal.
[0003] Prior Art Literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-180695 Summary of the invention
[0006] Problems to be solved by the invention
[0007] The capacitance of the capacitor constituting the low-pass filter circuit of the class D amplifier circuit varies according to the voltage applied to the capacitor. If the capacitance of the capacitor varies according to the applied voltage, the cutoff frequency of the low-pass filter varies according to the pulse. If the cutoff frequency of the low-pass filter varies, the sound signal output to the output terminal may not have the desired characteristics.
[0008] Therefore, an object of the present invention is to provide a class D amplifier circuit that can output an output signal having desired characteristics even if the voltage of a signal input to a capacitor of a low-pass filter changes.
[0009] Means for solving problems
[0010] The class D amplifier circuit of the present invention comprises: a PWM modulation circuit; a drive circuit connected to the PWM modulation circuit; and a low-pass filter circuit connected to the drive circuit, wherein the low-pass filter circuit comprises an inductor, a first capacitor and a second capacitor, the first capacitor and the second capacitor comprise a dielectric and electrodes sandwiching the dielectric, the low-pass filter circuit comprises an input terminal, a first potential terminal, a second potential terminal and an output terminal, the input terminal is connected to the drive circuit, the first potential terminal is connected to a first potential, the second potential terminal is connected to a second potential lower than the first potential, the output terminal is connected to a load circuit, one external electrode of the first capacitor is connected to the first potential terminal, one external electrode of the second capacitor is connected to the second potential terminal, another external electrode of the first capacitor and another external electrode of the second capacitor are connected to the output terminal, one external electrode of the inductor is connected to the input terminal, and another external electrode of the inductor is connected to the output terminal.
[0011] Effects of the Invention
[0012] According to the present invention, it is possible to provide a class D amplifier circuit that can output an output signal having desired characteristics even if the voltage of a signal input to a capacitor of a low-pass filter varies. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 2 is a diagram showing a class D amplifier circuit according to the present invention.
[0014] Figure 2 It is a diagram showing the terminals of the inductor and the capacitor according to the present invention.
[0015] Figure 3 This is a diagram showing the relationship between the voltage applied to a capacitor and the capacitance of the capacitor.
[0016] Figure 4 This is a diagram showing a potential difference and the like when a signal is input to the low-pass filter circuit of the present invention.
[0017] Figure 5 This is a diagram showing a conventional class D amplifier circuit.
[0018] Figure 6 This is a diagram showing a state where a signal is input to a conventional low-pass filter circuit.
[0019] Figure 7 It is a perspective view showing a four-terminal multilayer ceramic capacitor according to the present invention.
[0020] Figure 8 This is a diagram showing at least a portion of the internal electrode of the present invention.
[0021] Fig. 9 It is a diagram showing a circuit configuration of a low-pass filter circuit according to the present invention.
[0022] Fig.10 yes Figure 7 II line cross-sectional view.
[0023] Fig.11 yes Figure 7 Cross-sectional view along line II-II.
[0024] Fig.12 The planar structure of the first internal electrode 10a is shown in FIG. Figure 7 Cross-sectional view along line III-III.
[0025] Fig.13 The planar structure of the second internal electrode 10b is shown in FIG. Figure 7 Cross-sectional view along line III-III.
[0026] Fig.14 The planar structure of the third internal electrode 10c is shown in FIG. Figure 7 Cross-sectional view along line III-III.
[0027] Fig.15 It is a diagram showing a class D amplifier circuit according to another embodiment of the present invention.
[0028] Fig.16 This is a diagram showing a potential difference and the like when a signal is input to a differential signal filter circuit according to another embodiment of the present invention. DETAILED DESCRIPTION
[0029] (Implementation method 1)
[0030] Hereinafter, embodiments of the present invention will be described based on the drawings. Figure 1 1 is a diagram showing an overview of a class D amplifier circuit 30 according to the present invention.
[0031] (Overview of Class D amplifier circuit)
[0032] The class D amplifier circuit 30 of this embodiment includes a PWM modulation circuit 32, a drive circuit 34 connected to the PWM modulation circuit 32, and a low-pass filter circuit 36 connected to the drive circuit 34. As described above, the PWM modulation circuit 32 outputs a PWM modulation signal. The drive circuit 34 amplifies the PWM modulation signal and outputs the amplified PWM modulation signal. The low-pass filter circuit 36 removes high-frequency components of the amplified PWM modulation signal.
[0033] (Outline of low-pass filter circuit)
[0034] The low-pass filter circuit 36 includes an inductor 40 and a capacitor 1. A load circuit 62 is connected to the low-pass filter circuit 36. A signal output from the low-pass filter circuit 36 is input to the load circuit 62.
[0035] Specifically, the low-pass filter circuit 36 includes an inductor 40 and at least two capacitors 1. The two capacitors 1 are a first capacitor 1a and a second capacitor 1b. Figure 1 In FIG. 1 , the first capacitor 1a is represented by C1. In addition, the second capacitor 1b is represented by C2.
[0036] Each capacitor 1 includes a dielectric and electrodes sandwiching the dielectric. That is, the capacitor 1 can be a capacitor that is a lumped constant circuit, such as a multilayer ceramic capacitor or a film capacitor.
[0037] (Terminals of low-pass filter circuit)
[0038] The low-pass filter circuit 36 has four external terminals. The four external terminals are an input terminal 50, a first potential terminal 52a, a second potential terminal 52b, and an output terminal 56. The input terminal 50 is connected to the drive circuit 34. The first potential terminal 52a is connected to a first potential. The second potential terminal is connected to a second potential. The output terminal 56 is connected to the load circuit 62. Here, the first potential can be set to, for example, a power supply voltage potential, and the second battery can be set to, for example, a GND (ground) potential.
[0039] (Connections within the low-pass filter circuit)
[0040] Reference Figure 2 Connections and the like of terminals inside the low-pass filter circuit 36 will be described. Figure 2 1 is a diagram showing the terminals of the inductor 40 and the capacitor 1. The inductor 40 includes two inductor external electrodes 42. One of the inductor external electrodes 42 is a first inductor external electrode 42a, and the other is a second inductor external electrode 42b. The first inductor external electrode 42a is connected to the input terminal 50. The second inductor external electrode 42b is connected to the output terminal 56.
[0041] The connection of the capacitor 1 is described. The first capacitor 1a and the second capacitor 1b each include two external electrodes 20. One of the external electrodes 20 of the first capacitor 1a is an external electrode (A) 20a, and the other is an external electrode (B) 20b. The external electrode (A) 20a is connected to the first potential terminal 52a, and the external electrode (B) 20b is connected to the output terminal 56.
[0042] Next, the second capacitor 1 b is described. One of the external electrodes 20 of the second capacitor 1 b is an external electrode (D) 20 d , and the other is an external electrode (C) 20 c . The external electrode (D) 20 d is connected to the second potential terminal 52 b , and the external electrode (C) 20 c is connected to the output terminal 56 .
[0043] (voltage and capacitance)
[0044] The class D amplifier circuit 30 of the present embodiment has the above-described configuration, and can output an output signal having desired characteristics even when the voltage of the signal input to the capacitor 1 included in the low-pass filter circuit 36 changes. Figure 3 This is a diagram showing the relationship between the voltage applied to a capacitor and the capacitance of the capacitor. Figure 3 The x-axis represents the voltage applied to the capacitor. Figure 3 The Y axis of the graph represents the capacitance of the capacitor. The capacitance of a capacitor, which is composed of a dielectric and electrodes sandwiching the dielectric, changes according to the applied voltage. Figure 3 As shown in point P2, if the voltage applied to the capacitor is relatively large, the capacitance of the capacitor becomes small. Figure 3 As shown at point P1 of FIG. 1 , if the voltage applied to the capacitor is relatively small, the capacitance of the capacitor increases. In this way, the capacitance of the capacitor changes according to the voltage applied to the capacitor.
[0045] In a class D amplifier circuit in which a low-pass filter circuit includes a capacitor that forms a lumped constant circuit, if the capacitance of the capacitor varies according to the voltage of an input pulse, it is difficult to obtain an output signal having desired characteristics. This is because the cutoff frequency of the low-pass filter circuit varies according to the voltage of the input pulse.
[0046] In contrast, in the class D amplifier circuit 30 of the present embodiment, even if the voltage of the signal input to the capacitor 1 of the low-pass filter circuit 36 changes, an output signal having desired characteristics can be output. Figure 4 This is a diagram showing the voltage and the like applied to each capacitor 1 when a pulse is input to the class D amplifier circuit 30 of the present embodiment. Figure 4 The X-axis represents time. In addition, Figure 4 The Y-axis represents the potential.
[0047] When the pulse input to the low-pass filter circuit 36 is Hi, the voltage applied to C2 as the second capacitor 1b increases ( Figure 4 On the contrary, the voltage applied to C1 as the first capacitor 1a becomes smaller ( Figure 4 Therefore, the capacitance reduction of C2 is greater than the capacitance reduction of C1.
[0048] On the contrary, when the pulse input to capacitor 1 is L, the voltage applied to C1 as the first capacitor 1a becomes larger ( Figure 4 On the contrary, the voltage applied to C2 as the second capacitor 1b becomes smaller ( Figure 4 Therefore, the capacitance reduction of C1 is greater than the capacitance reduction of C2.
[0049] Thus, in the low-pass filter circuit 36 of the present embodiment, when the reduction in capacitance is large for one of the capacitors C1 and C2, the reduction in capacitance is small for the other capacitor. As a result, the total amount of capacitance that varies according to the pulse can be suppressed as a whole for the low-pass filter circuit 36. Therefore, the variation in the cutoff frequency of the low-pass filter circuit 36 can be suppressed. Therefore, it is easy to obtain the desired characteristics for the output signal output to the output terminal 56.
[0050] This can be more clearly understood by comparing it with a conventional class D amplifier circuit. Figure 5 3 is a diagram showing a conventional class D amplifier circuit 301 .
[0051] The conventional class D amplifier circuit 301 includes a PWM modulation circuit 321, a drive circuit 341, a low-pass filter circuit 361, and a load circuit 621. The low-pass filter circuit 361 includes an inductor 401 and a capacitor 101. The capacitor 101 is Figure 5 denoted by C. One external electrode of the inductor 401 is connected to the input terminal 501 of the low-pass filter circuit 361. The other external electrode of the inductor 401 is connected to the output terminal 561 of the low-pass filter circuit 361.
[0052] The conventional low-pass filter circuit 361 includes only one capacitor. One external electrode of the capacitor 101 is connected to the second potential terminal 521 b. The potential of the second potential terminal 521 b can be set to GND (ground) potential. The other external electrode of the capacitor 101 is connected to the output terminal 561 .
[0053] Furthermore, a load circuit 621 such as a speaker is connected to the output terminal 561 .
[0054] exist Figure 5 In the conventional class D amplifier circuit 301 shown in FIG. 3 , a case where a pulse is input to the input terminal 501 of the low-pass filter circuit 361 is considered. Figure 6 1 is a diagram showing a voltage etc. applied to the capacitor 101 when a pulse is input to the conventional class D amplifier circuit 301 .
[0055] When the pulse input to the low-pass filter circuit 36 is Hi, the voltage applied to C as the capacitor 101 becomes larger ( Figure 6On the other hand, when the input pulse is L, the voltage applied to C becomes smaller ( Figure 6 d6). Therefore, when the pulse is Hi, the capacitance of C becomes smaller, and when the pulse is L, the capacitance of C becomes smaller. In this way, in the conventional class D amplifier circuit 301, the capacitance of the capacitor 101 changes according to the change of the voltage of the pulse. If the capacitance of the capacitor 101, i.e., C, changes according to the pulse, the cutoff frequency of the low-pass filter circuit 361 changes according to the pulse. If the cutoff frequency of the low-pass filter circuit 361 changes, the sound signal, for example, output to the output terminal 561 may not obtain the desired characteristics.
[0056] In contrast, in the class D amplifier circuit 30 of the present embodiment, two capacitors 1 are provided in the low-pass filter circuit 36. Therefore, even if the voltage of the pulse input to the low-pass filter circuit 36 varies greatly, the influence on the signal output from the output terminal 56 can be suppressed. Furthermore, for example, when the load circuit 62 connected to the output terminal 56 is a speaker and the output signal is a sound signal, a desired preferred sound output can be obtained.
[0057] In addition, various setting values in the class D amplifier circuit 30 of the present embodiment can be appropriately specified. As examples of setting values, the cutoff frequency can be set to 50 kHz or more and 100 kHz or less, the electrostatic capacitance of C1 as the first capacitor 1a can be set to 7uF, the electrostatic capacitance of C2 as the second capacitor can be set to 7uF, and the inductance of the inductor 40 can be set to 500nH. In addition, the capacitance ratio of the capacitor C1 to the capacitor C2 can be set to within ±50%, preferably within ±10%.
[0058] (Structure of capacitor)
[0059] Next, the structure of the capacitor 1 is described. The two capacitors 1 provided in the low-pass filter circuit 36, namely the first capacitor 1a and the second capacitor 1b, are composed of a four-terminal multilayer ceramic capacitor 1c. Figure 7 The overall structure of the four-terminal multilayer ceramic capacitor 1 c will be described.
[0060] (Outline of a four-terminal multilayer ceramic capacitor)
[0061] like Figure 7 As shown, a four-terminal multilayer ceramic capacitor 1 c includes a multilayer body 2 and external electrodes 20 .
[0062] (Definition of direction)
[0063] In the drawings, the L direction, the W direction, and the T direction are appropriately shown. The L direction is the length direction of the four-terminal multilayer ceramic capacitor 1c. The W direction is the width direction of the four-terminal multilayer ceramic capacitor 1c. The T direction is the height direction of the four-terminal multilayer ceramic capacitor 1c. Thus, Fig.10 The section shown is called the LT section. Fig.11 The cross section shown is called the WT cross section. Fig.12 , Fig.13 as well as Fig.14 It is called LW cross section. The length direction L, the width direction W and the height direction T do not necessarily need to be orthogonal to each other. The length direction L, the width direction W and the height direction T may also be intersecting to each other.
[0064] (Outer shape of laminate)
[0065] The stack 2 has a roughly rectangular parallelepiped shape. The stack 2 has two main surfaces 3, two end surfaces 4, and two side surfaces 5. The main surfaces 3 are surfaces that are opposite to each other in the height direction T. The end surfaces 4 are surfaces that are opposite to each other in the length direction L. The side surfaces 5 are surfaces that are opposite to each other in the width direction W. One of the two main surfaces 3 is set as the first main surface 3a, and the other is set as the second main surface 3b. One of the two end surfaces 4 is set as the first end surface 4a, and the other is set as the second end surface 4b. One of the two side surfaces 5 is set as the first side surface 5a, and the other is set as the second side surface 5b. Figure 7 The second main surface 3 b and the first side surface 5 a are shown.
[0066] It is preferable that the ridges and corners of the laminate 2 are rounded. The ridges refer to the portions where two surfaces of the laminate 2 intersect. The corners refer to the portions where three surfaces of the laminate 2 intersect. The size of the laminate 2 is not particularly limited.
[0067] (External Electrode)
[0068] The external electrodes 20 formed on the stack 2 include a first external electrode 20e, a second external electrode 20f, a third external electrode 20g, and a fourth external electrode 20h. The first external electrode 20e is mainly formed on the first end surface 4a of the stack 2, the second external electrode 20f is mainly formed on the first side surface 5a of the stack 2, the third external electrode 20g is mainly formed on the second side surface 5b of the stack 2, and the fourth external electrode 20h is mainly formed on the second end surface 4b of the stack 2.
[0069] Specifically, the first external electrode 20e is continuously formed on the entire first end surface 4a of the laminate 2, a part of the two main surfaces 3, and a part of the two side surfaces. The second external electrode 20f is continuously formed on a part of the first side surface 5a of the laminate 2 and a part of the two main surfaces 3. The third external electrode 20g is continuously formed on a part of the second side surface 5b of the laminate 2 and a part of the two main surfaces 3, similarly to the second external electrode 20f. The fourth external electrode 20h is continuously formed on the entire second end surface 4b of the laminate 2, a part of the two main surfaces 3, and a part of the two side surfaces, similarly to the first external electrode 20e.
[0070] (Overview of internal electrodes)
[0071] The laminate 2 includes a plurality of dielectrics 7 and a plurality of internal electrodes 10. Figure 8 , the internal electrode 10 included in the four-terminal multilayer ceramic capacitor 1c will be described. Figure 8 The diagram shows at least a part of the internal electrodes 10 provided in the four-terminal multilayer ceramic capacitor 1c. The internal electrodes 10 include at least one first internal electrode 10a, at least one second internal electrode 10b, and at least one third internal electrode 10c.
[0072] The first inner electrode 10a, the second inner electrode 10b and the third inner electrode 10c are arranged in this order in the height direction T. Figure 8 In the figure, each internal electrode 10 represents one layer. This is an example, and it is also possible to Figure 8 The structure shown is stacked repeatedly multiple times.
[0073] (Lead-out portion of internal electrode)
[0074] The internal electrode 10 has an opposing portion 11 and a lead portion 12. The opposing portion 11 is a portion where the internal electrode 10 overlaps with other internal electrodes 10 when viewed from the height direction T. The lead portion 12 is a portion led out from the opposing portion 11 in order to connect the internal electrode 10 to the external electrode 20. That is, the opposing portion 11 is connected to the external electrode 20 via the lead portion 12.
[0075] Specifically, the first inner electrode 10a has a first lead portion 12a extending in the longitudinal direction L. The first opposing portion 11a of the first inner electrode 10a is connected to the first outer electrode 20e via the first lead portion 12a.
[0076] Similarly, the second internal electrode 10b has a second lead portion 12b and a third lead portion 12c extending in the width direction W. The second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f via the second lead portion 12b. In addition, the second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g via the third lead portion 12c. In this way, the second internal electrode 10b is connected to the two external electrodes 20 in the width direction W.
[0077] The third inner electrode 10c has a fourth lead portion 12d extending in the longitudinal direction L. The third opposing portion 11c of the third inner electrode 10c is connected to the fourth outer electrode 20h via the fourth lead portion 12d.
[0078] As described above, each of the internal electrodes 10 is connected to the corresponding four external electrodes 20. The four external electrodes 20 correspond to the four terminals of the four-terminal multilayer ceramic capacitor 1c.
[0079] The correspondence between the two capacitors 1 included in the low-pass filter circuit 36 and the four-terminal multilayer ceramic capacitor 1 c will be described. Fig. 9 2 is a diagram showing a circuit configuration of the low-pass filter circuit 36. As described above, the first capacitor 1a and the second capacitor 1b included in the low-pass filter circuit 36 are configured as one four-terminal multilayer ceramic capacitor 1c.
[0080] The first capacitor 1a corresponds to a portion where the first internal electrode 10a and the second internal electrode 10b of the four-terminal multilayer ceramic capacitor 1c face each other. The second capacitor 1b corresponds to a portion where the second internal electrode 10b and the third internal electrode 10c of the four-terminal multilayer ceramic capacitor 1c face each other.
[0081] Therefore, the external electrode (A) 20 a of the first capacitor 1 a corresponds to the first external electrode 20 e of the four-terminal multilayer ceramic capacitor 1 c .
[0082] In addition, the external electrode (B) 20b of the first capacitor 1a corresponds to the second external electrode 20f and the third external electrode 20g of the four-terminal multilayer ceramic capacitor 1c. Similarly, the external electrode (C) 20c of the second capacitor 1b also corresponds to the second external electrode 20f and the third external electrode 20g of the four-terminal multilayer ceramic capacitor 1c. This is because the first capacitor 1a and the second capacitor 1b share the second internal electrode 10b.
[0083] Furthermore, the external electrode (D) 20 d of the second capacitor 1 b corresponds to the fourth external electrode 20 h of the four-terminal multilayer ceramic capacitor 1 c .
[0084] In summary, the four-terminal multilayer ceramic capacitor 1c includes a plurality of internal electrodes 10 and first to fourth external electrodes. The first external electrode 20e corresponds to one external electrode 20 of the first capacitor 1a connected to the first potential terminal 52a, namely, the external electrode (A) 20a. The fourth external electrode 20h corresponds to one external electrode 20 of the second capacitor 1b connected to the second potential terminal 52b, namely, the external electrode (D) 20d. The second external electrode 20f and the third external electrode 20g correspond to the other external electrode 20 of the first capacitor 1a, namely, the external electrode (B) 20b. In addition, the second external electrode 20f and the third external electrode 20g also correspond to the other external electrode 20 of the second capacitor 1b, namely, the external electrode (C) 20c.
[0085] The plurality of internal electrodes 10 include a first internal electrode 10a connected to the first external electrode 20e. In addition, the plurality of internal electrodes 10 include a second internal electrode 10b that is opposite to the first internal electrode 10a via the dielectric 7 and is connected to the second external electrode 20f and the third external electrode 20g. Furthermore, the plurality of internal electrodes 10 include a third internal electrode 10c that is opposite to the second internal electrode 10b via the dielectric 7 and is connected to the fourth external electrode 20h.
[0086] Hereinafter, the cross-sectional structure of the stacked body 2 will be described with reference to the cross-sectional view of the stacked body 2 .
[0087] (Internal structure of laminate (LT cross section))
[0088] based on Fig.10 The internal structure of the laminated body 2 will be described. Fig.10 yes Figure 7 FIG. 1 is a cross-sectional view taken along line II of a four-terminal multilayer ceramic capacitor 1 c shown in FIG. Fig.10 LT cross section of the four-terminal laminated ceramic capacitor 1c is shown. The laminated body 2 includes a plurality of dielectrics 7 and a plurality of internal electrodes 10. The plurality of dielectrics 7 and the plurality of internal electrodes 10 are laminated in the height direction T with respect to each other.
[0089] (Internal Electrode)
[0090] As described above, the internal electrode 10 includes the first internal electrode 10 a , the second internal electrode 10 b , and the third internal electrode 10 c .
[0091] In the LT cross section, the first opposing portion 11a of the first internal electrode 10a is connected to the first external electrode 20e formed on the first end surface 4a via the first lead portion 12a. In addition, the third opposing portion 11c of the third internal electrode 10c is connected to the fourth external electrode 20h formed on the second end surface 4b via the fourth lead portion 12d. On the other hand, the second internal electrode 10b is not connected to the external electrode 20 in the LT cross section. This is because the second internal electrode 10b is connected to the external electrode 20 at the side surface 5.
[0092] (Internal structure of laminate (WT cross section))
[0093] based on Fig.11 The internal structure of the laminated body 2 will be described. Fig.11 yes Figure 7 FIG. 1 is a cross-sectional view taken along line II-II of a four-terminal multilayer ceramic capacitor 1 c shown in FIG. Fig.11 WT cross section of the four-terminal multilayer ceramic capacitor 1c is shown.
[0094] In the WT cross section, the second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f formed on the first side surface 5a via the second lead portion 12b. In addition, the second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g formed on the second side surface 5b via the third lead portion 12c. In this way, the second internal electrode 10b is connected to the external electrodes 20 at both side surfaces 5.
[0095] On the other hand, the first internal electrode 10a and the third internal electrode 10c are not connected to the external electrode 20 in the WT cross section. This is because the first internal electrode 10a and the third internal electrode 10c are connected to the external electrode 20 at the end surface 4.
[0096] (Planar structure of internal electrode (LW cross section))
[0097] based on Figure 12 to Figure 14 Next, the planar structure of the internal electrode 10 will be described. The planar structure refers to the structure of the internal electrode 10 when viewed from the height direction T of the four-terminal multilayer ceramic capacitor 1c. Figure 12 to Figure 14 yes Figure 7 Cross-sectional view along line III-III. Figure 12 to Figure 14 FIG. 1 shows a LW cross section of a four-terminal multilayer ceramic capacitor 1 c .
[0098] (First Internal Electrode)
[0099] Fig.12 The planar structure of the first internal electrode 10 a is shown.
[0100] The first opposing portion 11a of the first internal electrode 10a is connected to the first external electrode 20e formed on the first end surface 4a via the first lead portion 12a. The length of the first lead portion 12a in the width direction W is shorter than the length of the first opposing portion 11a in the width direction W. In addition, the first internal electrode 10a is not connected to any external electrode 20 other than the first external electrode 20e.
[0101] (Second inner electrode)
[0102] Fig.13 The planar structure of the second internal electrode 10 b is shown.
[0103] The second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f formed on the first side surface 5a via the second lead portion 12b. In addition, the second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g formed on the second side surface 5b via the third lead portion 12c. The length of the second lead portion 12b in the longitudinal direction L and the length of the third lead portion 12c in the longitudinal direction L are shorter than the length of the second opposing portion 11b in the longitudinal direction L. In addition, the second internal electrode 10b is not connected to the external electrodes 20 other than the second external electrode 20f and the third external electrode 20g.
[0104] (Third inner electrode)
[0105] Fig.14 The planar structure of the third internal electrode 10c is shown.
[0106] The third opposing portion 11c of the third internal electrode 10c is connected to the fourth external electrode 20h formed on the second end surface 4b via the fourth lead portion 12d. The length of the fourth lead portion 12d in the width direction W is shorter than the length of the third opposing portion 11c in the width direction W. In addition, the third internal electrode 10c is not connected to any external electrode 20 other than the fourth external electrode 20h.
[0107] (Number of dielectric layers)
[0108] The number of dielectric layers 7 stacked on the stacked body 2 can be, for example, 5 or more layers and 2000 or less layers.
[0109] (Thickness of dielectric)
[0110] The thickness of the dielectric 7 can be set to, for example, 0.3 μm or more and 0.6 μm or less.
[0111] (Material of dielectric)
[0112] As the material of the dielectric 7, for example, dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. as main components can be used. In addition, materials containing Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. as auxiliary components added to these main components can also be used.
[0113] (Number of internal electrode layers)
[0114] The number of the internal electrodes 10 can be, for example, not less than 10 and not more than 2000. The number of layers of the internal electrodes 10 includes the number of layers of the first internal electrodes 10a and the number of layers of the second internal electrodes 10b.
[0115] (Thickness of internal electrode)
[0116] The thickness of the internal electrode 10 can be, for example, not less than 0.1 μm and not more than 5.0 μm, and preferably not less than 0.2 μm and not more than 2.0 μm.
[0117] (Material of internal electrode)
[0118] The material of the internal electrode 10 can be, for example, metal such as Ni, Cu, Ag, Pd, and Au, alloy of Ni and Cu, alloy of Ag and Pd, etc. In addition, the material of the internal electrode 10 may include dielectric particles of the same composition as the ceramic included in the dielectric 7 .
[0119] (Size of multilayer ceramic capacitors)
[0120] The size of the four-terminal multilayer ceramic capacitor 1c is not particularly limited. The size of the four-terminal multilayer ceramic capacitor 1c can be set, for example, as follows. The dimension of the length direction L of the four-terminal multilayer ceramic capacitor 1c including the stack 2 and the external electrode 20 is set to the L dimension. The L dimension is preferably greater than 0.25 mm and less than 1.0 mm. The dimension of the height direction T of the four-terminal multilayer ceramic capacitor 1c including the stack 2 and the external electrode 20 is set to the T dimension. The T dimension is preferably greater than 0.125 mm and less than 0.5 mm. The dimension of the width direction W of the four-terminal multilayer ceramic capacitor 1c including the stack 2 and the external electrode 20 is set to the W dimension. The W dimension is preferably greater than 0.125 mm and less than 0.5 mm.
[0121] (Layer structure of external electrode)
[0122] The external electrode 20 can be a multilayer structure. For example, in the case of a three-layer structure, it can be a base layer, an inner plating layer, and a surface plating layer. The base layer can be, for example, a sintered layer of a material containing a glass component and a metal. In addition, the inner plating layer can be a Ni plating layer. In addition, the surface plating layer can be a Sn plating layer.
[0123] (Method for manufacturing multilayer ceramic capacitor)
[0124] A method for manufacturing the four-terminal multilayer ceramic capacitor 1 c will be described.
[0125] (Fabrication of stacked blocks)
[0126] Ceramic green sheets and electrode paste for the internal electrodes 10 are prepared.
[0127] (Application of ointment)
[0128] The electrode paste is applied to the ceramic green sheet in a desired pattern. The electrode paste can be applied to the ceramic green sheet by, for example, screen printing, gravure printing, etc. Thus, a ceramic green sheet for the inner layer portion on which the paste is printed is obtained.
[0129] (Cascade)
[0130] A given number of ceramic green sheets without the pattern of the internal electrode 10 printed thereon are stacked. Thus, a portion corresponding to the outer layer portion is produced. Ceramic green sheets for the inner layer portion coated with paste are sequentially stacked thereon. Thus, a portion corresponding to the inner layer portion is stacked. Furthermore, a given number of ceramic green sheets for another outer layer portion are stacked thereon. Thus, a laminated sheet is produced. The laminated sheet is pressed in the height direction by isostatic pressing or the like to produce a laminated block.
[0131] (Preparation of laminated sheets)
[0132] The stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by roller grinding or the like.
[0133] (Firing)
[0134] Next, the stacked small pieces are fired to produce the stacked body 2. The firing temperature depends on the materials of the dielectric 7 and the internal electrode 10, but is preferably 900°C or higher and 1400°C or lower.
[0135] (External Electrode)
[0136] Next, the external electrodes 20 are formed. First, a conductive paste that becomes a base layer is applied to a desired position of the laminate 2 and sintered to form a base layer. Then, a Ni plating layer is formed on the base layer, and then a Sn plating layer is formed on the Ni plating layer. The Ni plating layer becomes an inner plating layer, and the Sn plating layer becomes a surface plating layer.
[0137] As described above, the four-terminal multilayer ceramic capacitor 1 c included in the class D amplifier circuit 30 can be manufactured.
[0138] (Implementation method 2)
[0139] The following is based on Fig.15 as well as Fig.16 Embodiment 2 of the present invention will be described. Fig.15 is a diagram showing a class D amplifier circuit according to Embodiment 2. Fig.16 1 is a diagram showing a potential difference when a signal is input to a differential signal filter circuit of Embodiment 2. In the following description, the differences from Embodiment 1 are mainly described. In Embodiment 2, a filter circuit having two capacitors 1 is used as a filter for differential signals. The structure of the class D amplifier circuit 30 of Embodiment 2 is described in sequence below.
[0140] (Drive circuit)
[0141] The class D amplifier circuit 30 of the second embodiment includes a PWM modulation circuit (not shown), a first drive circuit 34a connected to the PWM modulation circuit, a second drive circuit 34b connected to the PWM modulation circuit, and a differential signal filter circuit 38 connected to the first drive circuit 34a and the second drive circuit 34b. In this way, the class D amplifier circuit 30 includes two drive circuits 34. In addition, the first drive circuit 34a is OUTP, and the second drive circuit 34b is OUTN.
[0142] (Differential signal filter circuit)
[0143] The differential signal filter circuit 38 includes two inductors 40 and two capacitors 1. The two inductors 40 are a first inductor 40a and a second inductor 40b. The two capacitors 1 are a first capacitor 1a and a second capacitor 1b. The first capacitor 1a and the second capacitor 1b include a dielectric 7 and internal electrodes 10 sandwiching the dielectric 7.
[0144] (Terminal connection)
[0145] The differential signal filter circuit 38 includes two input terminals 50 and two output terminals 56. Specifically, the differential signal filter circuit 38 includes a first input terminal 50a, a second input terminal 50b, a first output terminal 56a, a second output terminal 56b, and a reference potential terminal 54.
[0146] The first input terminal 50a is connected to the first drive circuit 34a, and the second input terminal 50b is connected to the second drive circuit 34b. In addition, the reference potential terminal 54 is connected to a reference potential such as ground. Furthermore, the first output terminal 56a and the second output terminal 56b are connected to the load circuit 62.
[0147] (Capacitor)
[0148] The connection of the capacitor 1 is described. One external electrode 20i of the first capacitor 1a is connected to the first input terminal 50a, and one external electrode 20j of the second capacitor 1b is connected to the second input terminal 50b. In addition, the other external electrode 20k of the first capacitor 1a and the other external electrode 20l of the second capacitor 1b are connected to the reference potential terminal 54.
[0149] (Inductor)
[0150] The connection of the inductor 40 is described. One external electrode 42d of the first inductor 40a, which is one of the two inductors 40, is connected to the first input terminal 50a, and the other external electrode 42c of the first inductor 40a is connected to the first drive circuit 34a. In addition, one external electrode 42f of the second inductor 40b is connected to the second input terminal 50b, and the other external electrode 42e of the second inductor 40b is connected to the second drive circuit 34b.
[0151] (Four-terminal multilayer ceramic capacitor)
[0152] Further, the first capacitor 1 a and the second capacitor 1 b included in the differential signal filter circuit 38 are constituted by a single four-terminal multilayer ceramic capacitor 1 c , similarly to the case of the low-pass filter circuit 36 of the first embodiment.
[0153] In the class D amplifier circuit 30 of the second embodiment, even if the voltage of the signal input to the capacitor 1 of the differential signal filter circuit 38 changes, it is possible to output an output signal having desired characteristics. Figure 5 1 is a diagram showing voltages and the like applied to capacitors 1 when a pulse is input to the class D amplifier circuit 30 of the present embodiment. Figure 5 The X-axis represents time. In addition, Figure 5 The Y-axis represents the potential.
[0154] When the pulse input to the first capacitor 1a of the differential signal filter circuit 38 is Hi, the voltage applied to C1 as the first capacitor 1a increases ( Fig.16 On the contrary, the voltage applied to C2 as the second capacitor 1b becomes smaller ( Fig.16 Therefore, the capacitance reduction of C1 is greater than the capacitance reduction of C2.
[0155] On the contrary, when the pulse input to the first capacitor 1a of the differential signal filter circuit 38 is L, the voltage applied to C1 as the first capacitor 1a becomes small ( Fig.16 On the contrary, the voltage applied to C2 as the second capacitor 1b becomes larger ( Fig.16 Therefore, the capacitance reduction of C2 is greater than the capacitance reduction of C1.
[0156] Thus, in the differential signal filter circuit 38 of the present embodiment, when the amount of reduction in capacitance is large for one of the capacitors C1 and C2, the amount of reduction in capacitance becomes small for the other capacitor. As a result, the total amount of capacitance that varies according to the pulse can be suppressed as the differential signal filter circuit 38 as a whole. Therefore, the variation in the characteristics of the differential signal filter circuit 38 can be suppressed. Therefore, it is easy to obtain the desired characteristics for the output signals output to the first output terminal 56a and the second output terminal 56b.
[0157] In the class D amplifier circuit 30 of the second embodiment, various setting values can be appropriately defined in the same manner as in the first embodiment. Examples of the setting values can be the same as in the first embodiment, for example.
[0158] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes and deformation|transformation are possible.
[0159] <1> A class D amplifier circuit comprising: a PWM modulation circuit; a drive circuit connected to the PWM modulation circuit; and a low-pass filter circuit connected to the drive circuit.
[0160] in,
[0161] The low-pass filter circuit includes an inductor, a first capacitor, and a second capacitor.
[0162] The first capacitor and the second capacitor include a dielectric and electrodes sandwiching the dielectric.
[0163] The low-pass filter circuit includes an input terminal, a first potential terminal, a second potential terminal, and an output terminal.
[0164] The input terminal is connected to the drive circuit.
[0165] The first potential terminal is connected to a first potential,
[0166] The second potential terminal is connected to a second potential lower than the first potential,
[0167] The output terminal is connected to a load circuit,
[0168] One external electrode of the first capacitor is connected to the first potential terminal,
[0169] One external electrode of the second capacitor is connected to the second potential terminal,
[0170] The other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the output terminal,
[0171] One external electrode of the inductor is connected to the input terminal,
[0172] The other external electrode of the inductor is connected to an output terminal.
[0173] <2> The class D amplifier circuit according to <1>,
[0174] The first capacitor and the second capacitor are formed by a four-terminal multilayer ceramic capacitor.
[0175] The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes.
[0176] The first external electrode is an external electrode of the first capacitor connected to the first potential terminal,
[0177] The fourth external electrode is an external electrode of the second capacitor connected to the second potential terminal.
[0178] The second external electrode and the third external electrode are another external electrode of the first capacitor and another external electrode of the second capacitor,
[0179] The plurality of internal electrodes include a first internal electrode connected to the first external electrode,
[0180] The plurality of internal electrodes include a second internal electrode that is opposed to the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode.
[0181] The plurality of internal electrodes include a third internal electrode that is opposed to the second internal electrode via a dielectric and is connected to the fourth external electrode.
[0182] <3> A class D amplifier circuit having:
[0183] PWM modulation circuit; a first drive circuit connected to the PWM modulation circuit; a second drive circuit connected to the PWM modulation circuit; and a differential signal filter circuit connected to the first drive circuit and the second drive circuit,
[0184] The differential signal filter circuit includes a first inductor, a second inductor, a first capacitor and a second capacitor.
[0185] The first capacitor and the second capacitor include a dielectric and electrodes sandwiching the dielectric.
[0186] The differential signal filter circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a reference potential terminal.
[0187] The first input terminal is connected to the first drive circuit,
[0188] The second input terminal is connected to the second drive circuit,
[0189] The reference potential terminal is connected to the reference potential.
[0190] The first output terminal and the second output terminal are connected to a load circuit.
[0191] One external electrode of the first capacitor is connected to the first output terminal,
[0192] One external electrode of the second capacitor is connected to the second output terminal,
[0193] The other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the reference potential terminal,
[0194] One external electrode of the first inductor is connected to the first input terminal,
[0195] The other external electrode of the first inductor is connected to the first driving circuit,
[0196] One external electrode of the second inductor is connected to the second input terminal,
[0197] The other outer electrode of the second inductor is connected to the second driving circuit.
[0198] <4> According to the class D amplifier circuit described in <3>,
[0199] The first capacitor and the second capacitor are formed by a four-terminal multilayer ceramic capacitor.
[0200] The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes.
[0201] The first external electrode is an external electrode of the first capacitor connected to the first output terminal,
[0202] The fourth external electrode is an external electrode of the second capacitor connected to the second output terminal,
[0203] The second external electrode and the third external electrode are another external electrode of the first capacitor, and further, are another external electrode of the second capacitor.
[0204] The plurality of internal electrodes include a first internal electrode connected to the first external electrode,
[0205] The plurality of internal electrodes include a second internal electrode that is opposed to the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode.
[0206] The plurality of internal electrodes include a third internal electrode that is opposed to the second internal electrode via a dielectric and is connected to the fourth external electrode.
[0207] <5> The class D amplifier circuit according to any one of <1> to <4>,
[0208] The load circuit is a speaker.
[0209] <6> The class D amplifier circuit according to any one of <1> to <5>,
[0210] A difference between the capacitance of the first capacitor and the capacitance of the second capacitor is within ±50%.
[0211] <7> The class D amplifier circuit according to <2> or <4>,
[0212] The first external electrode and the fourth external electrode are arranged on end surfaces of the four-terminal multilayer ceramic capacitor.
[0213] The second external electrode and the third external electrode are arranged on side surfaces of the four-terminal multilayer ceramic capacitor.
[0214] Description of Reference Numerals
[0215] 1 Capacitor (Multilayer Ceramic Capacitor)
[0216] 2 Laminated body
[0217] 3 Main side
[0218] 4 End face
[0219] 5 Side
[0220] 7 Dielectric
[0221] 10 Internal Electrode
[0222] 11 Opposing part
[0223] 12 Lead-out
[0224] 20 External electrodes
[0225] 30 Class D amplifier circuit
[0226] 32 PWM modulation circuit
[0227] 34. Driving circuit
[0228] 36 Low pass filter circuit
[0229] 38 Differential signal filter circuit
[0230] 40 Inductor
[0231] 42 Inductor external electrode
[0232] 50 Input terminals
[0233] 54 Reference potential terminal
[0234] 56 Output terminals
[0235] 58 Power Supply
[0236] 60 Ground
[0237] 62 Load Circuit
[0238] T Height direction
[0239] L Length direction
[0240] W Width direction
[0241] E1 First potential (power supply)
[0242] E2 Second potential (GND).
Claims
1. A class D amplifier circuit comprising: a PWM modulation circuit; a drive circuit connected to the PWM modulation circuit; and a low-pass filter circuit connected to the drive circuit. in, The low-pass filter circuit includes an inductor, a first capacitor, and a second capacitor. The first capacitor and the second capacitor include a dielectric and electrodes sandwiching the dielectric. The low-pass filter circuit includes an input terminal, a first potential terminal, a second potential terminal, and an output terminal. The input terminal is connected to the drive circuit. The first potential terminal is connected to a first potential, The second potential terminal is connected to a second potential lower than the first potential, The output terminal is connected to a load circuit, One external electrode of the first capacitor is connected to the first potential terminal, One external electrode of the second capacitor is connected to the second potential terminal, The other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the output terminal, One external electrode of the inductor is connected to the input terminal, The other external electrode of the inductor is connected to an output terminal.
2. The class D amplifier circuit according to claim 1, wherein: The first capacitor and the second capacitor are formed by a four-terminal multilayer ceramic capacitor. The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes. The first external electrode is an external electrode of the first capacitor connected to the first potential terminal, The fourth external electrode is an external electrode of the second capacitor connected to the second potential terminal. The second external electrode and the third external electrode are another external electrode of the first capacitor and another external electrode of the second capacitor, The plurality of internal electrodes include a first internal electrode connected to the first external electrode, The plurality of internal electrodes include a second internal electrode that is opposed to the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode. The plurality of internal electrodes include a third internal electrode that is opposed to the second internal electrode via a dielectric and is connected to the fourth external electrode.
3. A class D amplifier circuit, comprising: PWM modulation circuit; a first drive circuit connected to the PWM modulation circuit; a second drive circuit connected to the PWM modulation circuit; and a differential signal filter circuit connected to the first drive circuit and the second drive circuit, The differential signal filter circuit includes a first inductor, a second inductor, a first capacitor, and a second capacitor. The first capacitor and the second capacitor include a dielectric and electrodes sandwiching the dielectric. The differential signal filter circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a reference potential terminal. The first input terminal is connected to the first drive circuit, The second input terminal is connected to the second drive circuit, The reference potential terminal is connected to the reference potential. The first output terminal and the second output terminal are connected to a load circuit. One external electrode of the first capacitor is connected to the first output terminal, One external electrode of the second capacitor is connected to the second output terminal, The other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the reference potential terminal, One external electrode of the first inductor is connected to the first input terminal, The other external electrode of the first inductor is connected to the first driving circuit, One external electrode of the second inductor is connected to the second input terminal, The other outer electrode of the second inductor is connected to the second driving circuit.
4. The class D amplifier circuit according to claim 3, wherein: The first capacitor and the second capacitor are formed by a four-terminal multilayer ceramic capacitor. The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes. The first external electrode is an external electrode of the first capacitor connected to the first output terminal, The fourth external electrode is an external electrode of the second capacitor connected to the second output terminal, The second external electrode and the third external electrode are another external electrode of the first capacitor, and further, are another external electrode of the second capacitor. The plurality of internal electrodes include a first internal electrode connected to the first external electrode, The plurality of internal electrodes include a second internal electrode that is opposed to the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode. The plurality of internal electrodes include a third internal electrode that is opposed to the second internal electrode via a dielectric and is connected to the fourth external electrode.
5. The class D amplifier circuit according to any one of claims 1 to 4, wherein: The load circuit is a speaker.
6. The class D amplifier circuit according to any one of claims 1 to 5, wherein: A difference between the capacitance of the first capacitor and the capacitance of the second capacitor is within ±50%.
7. The class D amplifier circuit according to claim 2 or claim 4, wherein: The first external electrode and the fourth external electrode are arranged on end surfaces of the four-terminal multilayer ceramic capacitor. The second external electrode and the third external electrode are arranged on side surfaces of the four-terminal multilayer ceramic capacitor.
Citation Information
Patent Citations
PWM modulation type class d amplifier
JP2007180695A