Monolithic integrated MEMS micro differential pressure chip and preparation method thereof

Abstract

According to the monolithic integrated MEMS micro differential pressure chip, a plurality of first injection regions (10), a second injection region (11), an all-dielectric isolation structure (6), a collector region (8), a base region (9), an emitter region (7) and a buried layer (1) are arranged on a first SOI silicon wafer, and correspondingly matched metal leads (13) are arranged on the second injection region (11), the collector region (8), the base region (9) and the emitter region (7). A second double-parabolic silicon wafer (5) is connected to the first SOI silicon wafer, and the monolithic integrated MEMS micro differential pressure chip is prepared through photoetching, injection, annealing, etching, film forming and sputtering processes. The invention has the advantages of simple structure, convenience in preparation and the like, and provides an efficient and economical solution for manufacturing a high-performance and high-reliability MEMS pressure chip.

Description

Technical Field

[0001] The present invention belongs to the field of MEMS, and specifically relates to a monolithic integrated MEMS micro differential pressure chip based on FDI process and a preparation method thereof.

[0002] Background Art: (Fully Dielectric Isolation) MEMS (Micro-Electro-Mechanical System) is an integrated device based on micro-nano technology, which integrates mechanical structures, sensors, and electronic circuits in a tiny chip, featuring miniaturization, low power consumption, and high performance, and is widely used in the fields of sensing and actuation. MEMS pressure chips are the specific application of MEMS technology in pressure sensing, which utilize the piezoresistive effect or capacitance change principle of silicon to accurately measure environmental or medium pressure. It has the advantages of small size, high precision, and fast response, and is widely used in fields such as automotive, medical, and industrial control.

[0003] With the continuous expansion of the application scope, the demand for MEMS pressure chips in micro pressure measurement is increasing day by day, especially in fields such as medical devices, consumer electronics, and industrial control, where the requirements for high precision, high sensitivity, and miniaturization are becoming increasingly strict.

[0004] However, due to the limitations of process capabilities, the stability and measurement accuracy of MEMS pressure chips in the micro pressure range often fail to meet these requirements. Specifically, the miniaturized manufacturing of pressure sensors is difficult, the signal output is weak and vulnerable to noise interference, resulting in inaccurate measurement.

[0005] In order to meet the requirements brought by the application side, MEMS micro differential pressure chips have gradually changed from flat film structures to beam film / island film structures. However, restricted by the current process capabilities, the process of MEMS beam film / island film pressure chips is complex, the manufacturing difficulty is high, it is difficult to ensure high consistency within the wafer, and the stability and accuracy during micro pressure measurement are difficult to fully meet the requirements. The main manifestations are that the miniaturized manufacturing of sensors is complex, the signal output is weak and vulnerable to noise interference, thus affecting the measurement accuracy. Summary of the Invention

[0006] The present invention aims to overcome the deficiencies in the prior art and provides a monolithic integrated MEMS micro differential pressure chip structure and a preparation method thereof.

[0007] The present application provides the following technical solutions: A monolithic integrated MEMS differential pressure chip based on the FDI process, characterized in that: it includes a group of first implantation regions provided in the middle of the first top layer silicon of the first SOI wafer, and a second implantation region is electrically connected to one side of each first implantation region. A pair of spaced-apart all-dielectric isolation structures are respectively provided at both ends of the first top layer silicon. A collector region, a base region, and an N+-type buried layer are provided on the first top layer silicon between each pair of all-dielectric isolation structures. An emitter region is also provided on the base region. Corresponding metal leads are provided on the second implantation region, the collector region, the base region, and the emitter region. A groove-like structure with an opening downward is provided on the bottom surface of the middle of the first top layer silicon. A second double-polished silicon wafer is bonded to the bottom surface of the first top layer silicon. A cavity is provided on the second double-polished silicon wafer. One end of the cavity is communicated with the groove-like structure, and the other end is communicated with the bottom surface of the second double-polished silicon wafer.

[0008] On the basis of the above technical solution, the following further technical solutions may be available: The buried layer is located on the ground surface of the first top layer silicon below the collector region and the base region.

[0009] The cavity is integrally in the shape of a conical hole structure with a smaller upper part and a larger lower part.

[0010] An oxide layer is provided on the connection surface between the first top layer silicon and the second double-polished silicon wafer.

[0011] A preparation method of a monolithic integrated MEMS differential pressure chip based on the FDI process, characterized in that: it includes the following steps: S1. Take the first SOI wafer, and an buried oxide layer and a substrate layer are sequentially provided at the bottom of the first top layer silicon. A group of N+-type buried layers are formed on the first top layer silicon by using photolithography, implantation, annealing, and etching processes in sequence. S2. The SOI wafer prepared in step S1 is used to form a shallow cavity groove-like structure on the first top layer silicon by photolithography and etching processes in sequence. S3. Take the second double-polished silicon wafer, and oxidize the upper and lower surfaces of the second double-polished silicon wafer to form an oxide layer. S4. The second double-polished silicon wafer is wafer-level vacuum bonded to the first top layer silicon, and then the buried oxide layer and the substrate layer are removed. S5. A group of all-dielectric isolation structures are formed on the first top layer silicon by photolithography, etching, and oxidation processes in sequence. S6. The collector region, the base region, the first implantation region, and the second implantation region of the amplifier circuit are formed on the first top layer silicon by photolithography and implantation processes in sequence. S7. The emitter region is formed on the base region by photolithography and implantation processes in sequence. S8. A group of contact holes corresponding to the second implantation region, the collector region, the base region, and the emitter region are formed on the first top layer silicon by film formation, photolithography, etching, and sputtering processes in sequence. A conductive metal lead is provided in each contact hole. S9. Anisotropically etch a cavity upward from the bottom of the second double-polished silicon wafer through an anisotropic silicon etching process; S10. Use a BOE etching process to remove the oxide layer between the groove and the groove-like structure and the oxide layer on the bottom surface of the second double-polished silicon wafer, so that the cavity is connected to the groove-like structure and finally becomes a through-hole-like structure, thereby forming a MEMS differential pressure chip.

[0012] Advantages of the invention: The structure of the present invention is simple and easy to prepare, and it can be compatible with advanced integrated circuits and MEMS technologies, having good process compatibility and supporting mass production. The MEMS pressure chip prepared by this method has remarkable high integration and excellent signal sensitivity, and can effectively improve the sensing accuracy. At the same time, the chip has a relatively high structural strength, ensuring its long-term stability in different application environments. In addition, this process also simplifies the integration process with the sensor system, facilitating the realization of a highly integrated sensor module. Description of the drawings

[0013] Figure 1 is a schematic diagram after completing step S1 of the present invention; Figure 2 is a schematic diagram after completing step S2; Figure 3 is a schematic diagram after completing step S3; Figure 4 is a schematic diagram after completing step S4; Figure 5 is a schematic diagram after completing step S5; Figure 6 is a schematic diagram after completing step S8; Figure 7 Schematic diagram of completing step S9; Figure 8 Schematic diagram of completing step S10. Detailed implementation manners

[0014] As Figure 1-8 shown, a method for fabricating a monolithic integrated MEMS differential pressure chip based on an FDI process includes the following steps: S1. Take a first SOI silicon wafer, with a buried oxide layer 3 and a substrate layer 4 successively provided at the bottom of the first top silicon 2, and form a group of N+ buried layers 1 on the first top silicon 2 by using lithography, implantation, annealing, and etching processes in sequence.

[0015] S2. Form a shallow cavity groove-like structure 2a on the first top silicon (2) of the SOI silicon wafer prepared in step S1 by using lithography and etching processes in sequence.

[0016] S3. Take the second double-polished silicon wafer (5), oxidize the upper and lower surfaces of the second double-polished silicon wafer (5) to form an oxide layer 5a.

[0017] S4. Bond the second double-polished silicon wafer 5 and the first top silicon layer 2 at the wafer level in a vacuum, and then remove the buried oxide layer 3 and the substrate layer 4.

[0018] S5. Form a set of all-dielectric isolation structures 6 on the first top silicon layer 2 through photolithography, etching, and oxidation processes in sequence.

[0019] S6. Form the collector region 8, base region 9, first implantation region 10, and second implantation region 11 of the amplifier circuit on the first top silicon layer 2 through photolithography and implantation processes in sequence. The first implantation region 10 and the second implantation region 11 are arranged side by side and are electrically connected.

[0020] S7. Form the emitter region 7 on the base region 9 through photolithography and implantation processes in sequence.

[0021] S8. Form a set of contact holes 12 corresponding to the second implantation region 11, collector region 8, base region 9, and emitter region 7 on the first top silicon layer 2 through film formation, photolithography, etching, and sputtering processes in sequence. A conductive metal lead 13 is provided in each contact hole 12.

[0022] S9. Corrode a cavity 14 upward from the bottom of the second double-polished silicon wafer 5 through an anisotropic silicon etching process.

[0023] S10. Use the BOE etching process to remove the oxide layer 5a between the cavity 14 and the groove structure 2a and the oxide layer 5a on the bottom surface of the second double-polished silicon wafer 5, so that the cavity 14 communicates with the groove structure 2a and finally becomes a through-hole structure, thereby forming a MEMS differential pressure chip.

[0024] A monolithic integrated MEMS differential pressure chip based on the FDI process, which includes a first top silicon layer 2. A set of first implantation regions 10 are provided in the middle of the first top silicon layer 2. A second implantation region 11 is electrically connected to one side of each first implantation region 10. A pair of spaced all-dielectric isolation structures 6 are respectively provided at both ends of the first top silicon layer 2. A collector region 8, a base region 9, and a buried layer 1 are provided on the first top silicon layer 2 between each pair of all-dielectric isolation structures 6. The N+-type buried layer 1 is located on the ground surface of the first top silicon layer 2 below the collector region 8 and the base region 9.

[0025] An emitter region 7 is also provided on the base region 9. Corresponding metal leads 13 are provided on the second implantation region 11, collector region 8, base region 9, and emitter region 7. A groove structure 2a with an opening downward is provided on the bottom surface in the middle of the first top silicon layer 2. A second double-polished silicon wafer 5 is bonded to the bottom surface of the first top silicon layer 2. An oxide layer 5a is provided on the connection surface between the first top silicon layer 2 and the second double-polished silicon wafer 5.

[0026] A cavity 14 is provided on the second double-polished silicon wafer 5. One end of the cavity 14 communicates with the groove-like structure 2a. The cavity 14 is integrally in the shape of a tapered hole structure with a smaller upper part and a larger lower part, and the other end thereof communicates with the bottom surface of the second double-polished silicon wafer 5.

Claims

1. A monolithic integrated MEMS micro differential pressure chip based on FDI technology, characterized by: The invention comprises a first top silicon layer (2) of a first SOI silicon wafer having a group of first injection regions (10) in the middle, a second injection region (11) electrically connected to one side of each first injection region (10), a pair of spaced all-dielectric isolation structures (6) respectively arranged at both ends of the first top silicon layer (2), a collector region (8), a base region (9) and a buried layer (1) arranged on the first top silicon layer (2) between each pair of all-dielectric isolation structures (6), an emitter region (7) also arranged on the base region (9), corresponding matching metal leads (13) arranged on the second injection region (11), the collector region (8), the base region (9) and the emitter region (7), a groove structure (2a) opening downwardly arranged on the bottom surface of the middle of the first top silicon layer (2), a second double-polished silicon wafer (5) bonded to the bottom surface of the first top silicon layer (2), a cavity (14) arranged on the second double-polished silicon wafer (5), one end of the cavity (14) being connected to the groove structure (2a), and the other end being connected to the bottom surface of the second double-polished silicon wafer (5).

2. According to the FDI process-based monolithic integrated MEMS micro differential pressure chip of claim 1, characterized in that: The N+ buried layer (1) is located on the first top silicon (2) ground surface below the collector region (8) and the base region (9).

3. According to the FDI process-based monolithic integrated MEMS micro differential pressure chip of claim 1, characterized in that: The cavity (14) is in the form of a conical hole structure that is smaller at the top and larger at the bottom.

4. The monolithic integrated MEMS micro differential pressure chip based on FDI process according to claim 1, characterized in that: An oxide layer (5a) is provided on the connection surface between the first top silicon layer (2) and the second double-polished silicon wafer (5).

5. A method for preparing a monolithic integrated MEMS micro differential pressure chip based on FDI process disclosed in claim 1, characterized in that: The following steps are involved: S1, taking a first SOI silicon wafer, providing a buried oxide layer (3) and a substrate layer (4) at the bottom of a first top silicon layer (2), and forming a group of N+ buried layers (1) on the first top silicon layer (2) by photolithography, implantation, annealing, and etching processes; S2, forming a shallow cavity groove structure (2a) on the first top silicon layer (2) of the SOI silicon wafer prepared in step S1 by photolithography and etching processes in sequence; S3, taking a second double-polished silicon wafer (5), and performing oxidation on the upper and lower surfaces of the second double-polished silicon wafer (5) to form an oxide layer (5a); S4, performing wafer-level vacuum bonding on the second double-polished silicon wafer (5) and the first top silicon layer (2), and then removing the buried oxide layer (3) and the substrate layer (4); S5, forming a set of full dielectric isolation structures (6) on the first top silicon layer (2) by sequentially performing photolithography, etching, and oxidation processes; S6, forming a collector region (8), a base region (9), a first injection region (10) and a second injection region (11) of the amplifier circuit on the first top silicon layer (2) by photolithography and injection processes in sequence; S7, forming an emitter region (7) on the base region (9) by sequentially performing photolithography and implantation processes; S8 forms a group of contact holes (12) distributed corresponding to the second injection region (11), the collector region (8), the base region (9) and the emitter region (7) on the first top silicon layer (2) by film formation, photolithography, etching and sputtering processes in sequence, and a conductive metal lead (13) is provided in each contact hole (12); S9, etching a cavity (14) upward from the bottom of the second double-polished silicon wafer (5) through an anisotropic silicon etching process; S10, using a BOE etching process to remove the oxide layer (5a) between the groove body (14) and the groove-shaped structure (2a) and the oxide layer (5a) on the bottom surface of the second double-polished silicon wafer (5), so that the cavity (14) and the groove-shaped structure (2a) are connected, and finally form a through-hole structure, thereby forming a MEMS micro differential pressure chip.

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