Chip power consumption analysis optimization method and system

Abstract

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuit design verification, and particularly to a method and system for chip power consumption analysis and optimization. Background Art

[0002] With the rapid development of integrated circuit technology, the chip size has been continuously reduced, the number of transistors has increased significantly, and the chip performance has been greatly improved. However, the power consumption problem has become an important challenge that needs to be solved urgently in chip design, especially in power-sensitive fields such as mobile devices and Internet of Things devices. High power consumption not only leads to excessive energy consumption, but also may cause thermal management and reliability problems, seriously restricting the expansion of chip performance and application scenarios. Therefore, power consumption analysis and optimization have gradually become a key link in chip design.

[0003] In related technical means, chip power consumption analysis and optimization are usually achieved through multi-stage analysis and improvement. Static power consumption analysis is used in the design stage to evaluate the leakage characteristics of the circuit; dynamic power consumption analysis combines timing simulation with circuit switching activity data to evaluate the power consumption performance of the circuit during actual operation. These analyses rely on the power consumption models generated by EDA tools, and the power consumption is reduced by manually optimizing the architecture, algorithm, or circuit design. The prior art has realized the power consumption estimation and optimization of the chip in the design stage, and improved the overall energy efficiency ratio of the circuit.

[0004] For the above technical solutions, although the power consumption hotspots of the chip can be found and preliminarily optimized by combining static and dynamic analyses, there is a problem that it is difficult to quickly generate an optimization path for complex circuit structures during the positioning of power consumption hotspots and the circuit optimization and reconstruction. Summary of the Invention

[0005] In order to improve the problem that it is difficult to quickly generate an optimization path for complex circuit structures during the positioning of power consumption hotspots and the circuit optimization and reconstruction, this application provides a method and system for chip power consumption analysis and optimization.

[0006] The present invention provides a method for optimizing chip power consumption analysis, including: obtaining circuit structure information of the chip, performing topological analysis on the circuit structure information to generate a module topology diagram and a functional logic diagram of the circuit; performing static power consumption characteristic analysis on each module in the module topology diagram to obtain static power consumption data of each module, performing dynamic behavior simulation on the functional logic diagram, and performing dynamic power consumption characteristic analysis on the simulation result in combination with the timing signal of the chip to generate dynamic power consumption data; inputting the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, performing statistical analysis on the overall power consumption distribution of the chip to generate a global power consumption distribution diagram, and identifying a power consumption hot spot area according to the global power consumption distribution diagram; performing working mode optimization analysis on the power consumption hot spot area to obtain working mode parameters, using the working mode parameters to reconstruct the critical path in the circuit structure information to generate reconstructed circuit structure information, and based on the reconstructed circuit structure information, performing dynamic behavior simulation on the functional logic diagram again to generate simulation power consumption data; comparing and analyzing the simulation power consumption data with the dynamic power consumption data, and generating a power consumption optimization scheme based on the comparison result.

[0007] As a preferred solution, the step of obtaining circuit structure information of the chip, performing topological analysis on the circuit structure information to generate a module topology diagram and a functional logic diagram of the circuit includes: decoding the circuit design file of the chip through a parsing tool to obtain a plurality of circuit modules and a plurality of signal flow paths; based on all the signal flow paths, using a depth-first search algorithm to identify the connection relationship between all the circuit modules to generate a module topology diagram of the chip; applying a finite state machine analysis method to perform functional analysis on each circuit module to obtain the functional requirements and working conditions of each module, and constructing a functional logic diagram of the circuit according to the functional requirements and the working conditions.

[0008] As a preferred solution, the steps of analyzing the static power consumption characteristics of each module in the module topology diagram to obtain the static power consumption data of each module, performing dynamic behavior simulation on the functional logic diagram, and analyzing the dynamic power consumption characteristics of the simulation results in combination with the timing signals of the chip to generate dynamic power consumption data include: parsing the circuit structure of each module in the module topology diagram through register transfer level analysis to obtain module power consumption parameters and logic paths, and using a SPICE circuit simulation tool to perform static power consumption analysis on the module power consumption parameters and the logic paths to obtain a power consumption analysis result; calculating the static power consumption of the corresponding module based on the power consumption analysis result to obtain the static power consumption data of each module; applying a Verilog simulation tool to perform dynamic behavior simulation on the functional logic diagram to obtain a simulation excitation signal and power consumption characteristics, and performing timing calibration on the simulation excitation signal to obtain a calibration signal, and using the power consumption characteristics to simulate the dynamic power consumption distribution of the calibration signal to obtain power consumption simulation data; inputting the power consumption simulation data and the timing signals of the chip into a power consumption modeling tool for dynamic behavior simulation to obtain dynamic power consumption characteristic data, and using the analytic hierarchy process based on signal power consumption classification to perform timing correlation on the dynamic power consumption characteristic data to obtain the power consumption change curves of each module under different working states; analyzing the power consumption fluctuation range and change trend of each circuit module using the power consumption change curves to generate dynamic power consumption data.

[0009] As a preferred solution, the steps of parsing the circuit structure of each module in the module topology diagram through register transfer level analysis to obtain module power consumption parameters and logic paths, and using a SPICE circuit simulation tool to perform static power consumption analysis on the module power consumption parameters and the logic paths to obtain a power consumption analysis result include: using a register transfer level analysis tool to parse the circuit structure of each module in the module topology diagram to obtain voltage supply parameters and node capacitances, performing correlation analysis on the voltage supply parameters and the node capacitances to obtain module power consumption parameters; extracting the logic paths of each module in the module topology diagram through timing analysis to obtain the logic paths of each module; using a SPICE circuit simulation tool to perform static power consumption calculation on the module power consumption parameters and the logic paths to obtain static power consumption values and leakage current characteristics; comprehensively analyzing the static power consumption values and the leakage current characteristics to obtain a power consumption analysis result.

[0010] As a preferred solution, the step of inputting the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, statistically analyzing the power consumption distribution of the entire chip, generating a global power consumption distribution map, and identifying the power consumption hot spot area according to the global power consumption distribution map includes: classifying the static power consumption data and the dynamic power consumption data according to time, module, and working state to obtain the classified data, inputting the classified data into a preset power consumption distribution analysis model, in the power consumption distribution analysis model, performing hierarchical processing on the classified data through a preset plurality of power consumption classification criteria, generating power consumption distribution parameters based on the hierarchical result, using the k-means clustering algorithm to divide the power consumption area of the power consumption distribution parameters to obtain the power consumption density and the distribution range, and generating the power consumption distribution curve of each circuit module based on the power consumption density and the distribution range; using the power consumption distribution mapping algorithm based on Monte Carlo simulation to summarize the power consumption distribution curves of all circuit modules to obtain the global power consumption distribution map of the entire chip, and identifying the power consumption hot spot area in the chip by marking the area with power consumption higher than the preset threshold according to the global power consumption distribution map.

[0011] As a preferred solution, the step of performing an operating mode optimization analysis on the power consumption hot spot area to obtain operating mode parameters, using the operating mode parameters to reconstruct the critical path in the circuit structure information to generate the reconstructed circuit structure information, and based on the reconstructed circuit structure information, re-performing a dynamic behavior simulation on the functional logic diagram to generate simulation power consumption data includes: using the segmentation clustering method to divide the power consumption hot spot area to obtain a plurality of sub-areas, applying the area power consumption analysis method based on grid division to analyze the power consumption characteristics of each sub-area to obtain area power consumption parameters, and generating corresponding operating mode parameters based on the area power consumption parameters; calibrating and adjusting the operating mode parameters through a timing optimization algorithm to obtain optimization parameters and scheduling parameters, inputting the optimization parameters and the scheduling parameters into the circuit structure information, and combining the gate-level optimization algorithm based on Boolean network optimization to reconstruct the critical path to obtain the reconstructed circuit structure; updating the signal flow path and module behavior in the functional logic diagram according to the reconstructed circuit structure to obtain the updated circuit structure information, and inputting the updated circuit structure information into a dynamic simulation model to generate simulation power consumption data.

[0012] As a preferred solution, the step of comparing and analyzing the simulated power consumption data with the dynamic power consumption data and generating a power consumption optimization solution based on the comparison result includes: comparing and analyzing the simulated power consumption data and the dynamic power consumption data through a data comparison and analysis tool, extracting the similar and different parts in the simulated power consumption data and the dynamic power consumption data to obtain a comparison result; using a difference analysis method to identify the circuit modules with significant power consumption changes in the comparison result and generating corresponding power consumption optimization solutions.

[0013] The present application provides a chip power consumption analysis and optimization system, including: an acquisition unit for acquiring the circuit structure information of a chip, performing topological analysis on the circuit structure information, and generating a module topology diagram and a functional logic diagram of the circuit; a simulation unit for performing static power consumption characteristic analysis on each module in the module topology diagram to obtain the static power consumption data of each module, performing dynamic behavior simulation on the functional logic diagram, and performing dynamic power consumption characteristic analysis on the simulation result in combination with the timing signal of the chip to generate dynamic power consumption data; an analysis unit for inputting the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, performing statistical analysis on the overall power consumption distribution of the chip, generating a global power consumption distribution diagram, and identifying a power consumption hot spot area according to the global power consumption distribution diagram; a reconstruction unit for performing working mode optimization analysis on the power consumption hot spot area to obtain working mode parameters, using the working mode parameters to reconstruct the critical path in the circuit structure information, generating the reconstructed circuit structure information, and based on the reconstructed circuit structure information, performing dynamic behavior simulation on the functional logic diagram again to generate simulated power consumption data; an optimization unit for comparing and analyzing the simulated power consumption data with the dynamic power consumption data and generating a power consumption optimization solution based on the comparison result.

[0014] Compared with the prior art, the present application has the following beneficial effects: accurate analysis and fast optimization. By acquiring the circuit structure information of the chip and performing topological analysis to generate a module topology diagram and a functional logic diagram, the design structure of the chip can be comprehensively understood; through static power consumption characteristic analysis and dynamic behavior simulation, and performing dynamic power consumption characteristic analysis in combination with the timing signal, the power consumption performance of the chip in actual operation can be accurately evaluated; by inputting a preset power consumption distribution analysis model to generate a global power consumption distribution diagram, the power consumption hot spot area can be intuitively identified. By performing working mode optimization analysis on the power consumption hot spot area to obtain working mode parameters and reconstructing the critical path in the circuit structure information to generate the optimized circuit structure information; through the comparison and analysis of the simulated power consumption data and the dynamic power consumption data, the optimization effect can be comprehensively evaluated, and a power consumption optimization solution can be generated based on the comparison result, thereby improving the energy efficiency ratio of the chip and improving the problem that it is difficult to quickly generate an optimization path for a complex circuit structure when positioning the power consumption hot spot and optimizing and reconstructing the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] The structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0017] Figure 1 is a schematic flowchart of a method for optimizing chip power consumption analysis provided by an embodiment of the present invention; Figure 2 is a schematic block diagram of the structure of a system for optimizing chip power consumption analysis provided by an embodiment of the present invention.

[0018] Description of the reference numerals: 10. A system for optimizing chip power consumption analysis; 11. An acquisition unit; 12. A simulation unit; 13. An analysis unit; 14. A reconstruction unit; 15. An optimization unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0020] The flowchart shown in the drawings is only an example, and does not necessarily include all the contents and operations / steps, nor does it necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, combined, or partially merged, so the actual execution order may be changed according to the actual situation.

[0021] It should also be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0022] It should also be further understood that the term "and / or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0023] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and through specific embodiments.

[0024] Embodiment 1: As Figure 1 shown, this application provides a method for optimizing chip power consumption analysis, including steps S100 to S500.

[0025] Step S100: Obtain the circuit structure information of the chip, perform topological analysis on the circuit structure information, and generate a module topology diagram and a functional logic diagram of the circuit.

[0026] In this step, first obtain the design files of the chip, which contain the circuit structure information of the chip, including the connection relationships and functional descriptions of each module. Then, use a topological analysis tool to analyze the circuit structure information to generate a module topology diagram, showing the connections and relative positions between each module; at the same time, generate a functional logic diagram for describing the functions and logical relationships of each module. Specifically, by parsing the netlist and layout files in the design files, the hierarchical structure information of the circuit can be extracted and presented in a graphical form. These graphical representations help engineers understand the circuit design and provide basic data for subsequent analysis and optimization.

[0027] For example, when processing an embedded processor chip, by parsing its design files, a topology diagram and a functional logic diagram including multiple functional modules such as a CPU core, a memory module, and a peripheral interface module can be generated, which help engineers better understand the overall design structure of the chip.

[0028] Step S200: Perform static power consumption characteristic analysis on each module in the module topology diagram to obtain the static power consumption data of each module, perform dynamic behavior simulation on the functional logic diagram, and perform dynamic power consumption characteristic analysis on the simulation results in combination with the timing signals of the chip to generate dynamic power consumption data.

[0029] In this step, a static power analysis tool is used to analyze each module, evaluate its power consumption characteristics in different operating states, and obtain the static power consumption data of each module. Then, a dynamic behavior simulation is performed on the functional logic diagram. Combining with timing signals, the dynamic power consumption characteristics of the chip during actual operation are analyzed to generate dynamic power consumption data. Specifically, the static power consumption of each module can be simulated using a SPICE simulation tool to evaluate the leakage current and short-circuit current in different operating states. Then, a timing simulation tool (such as ModelSim) is used to perform a dynamic behavior simulation on the functional logic diagram, and combined with the clock signal and data input of the chip, its dynamic power consumption performance is evaluated.

[0030] For example, when analyzing a memory module, the leakage current and short-circuit current in different storage states can be evaluated using a SPICE simulation tool. Then, a dynamic behavior simulation is performed through ModelSim, and combined with the timing signals of read and write operations, its dynamic power consumption characteristics are evaluated.

[0031] Step S300: Input the static power consumption data and dynamic power consumption data into a preset power consumption distribution analysis model, perform a statistical analysis on the overall power consumption distribution of the chip, generate a global power consumption distribution map, and identify the power consumption hot spots based on the global power consumption distribution map.

[0032] In this step, the static power consumption data and dynamic power consumption data obtained in the previous step are input into the power consumption distribution analysis model. This model will perform a statistical analysis on the overall power consumption of the chip based on the input data, generate a global power consumption distribution map, and help engineers visualize the power consumption distribution of each area of the chip. Specifically, the power consumption distribution analysis model can use a method based on area division to divide the chip into multiple areas. The power consumption data of each area is analyzed through weighted average and superposition by the model to obtain the global power consumption distribution map. By observing the power consumption distribution map, the power consumption hot spots can be intuitively identified.

[0033] For example, when analyzing a graphics processing unit (GPU) chip, by inputting the static and dynamic power consumption data of each module into the power consumption distribution analysis model, a global power consumption distribution map showing different colors and intensities can be generated, thereby identifying the hot spots where power consumption is concentrated.

[0034] Step S400: Conduct an analysis on the operating mode optimization of the power consumption hot spots to obtain the operating mode parameters. Use the operating mode parameters to reconstruct the critical path in the circuit structure information to generate the reconstructed circuit structure information. Based on the reconstructed circuit structure information, perform a dynamic behavior simulation on the functional logic diagram again to generate the simulated power consumption data.

[0035] In this step, a detailed analysis of the working modes of the identified power consumption hotspots is carried out to evaluate the power consumption performance under different working modes and optimize their working mode parameters. Then, the critical paths in the circuit structure information are reconstructed using these optimized parameters to generate the optimized circuit structure information. Specifically, by analyzing the workload distribution and usage patterns of the power consumption hotspots and combining low-power design techniques (such as power gating, clock gating, etc.), the working mode parameters are optimized and the critical paths are reconstructed. For example, the logic gate design on the critical path is adjusted and the power control strategy is optimized.

[0036] For example, when analyzing a network processor chip, by optimizing the working mode of its high-speed data transmission module, the power consumption during data transmission can be reduced. By adjusting the logic gate design and power control strategy on the critical path, the optimized circuit structure information is generated and re-simulated to verify the power consumption optimization effect.

[0037] Step S500: Compare and analyze the simulated power consumption data with the dynamic power consumption data, and generate a power consumption optimization plan based on the comparison results.

[0038] In this step, the reconstructed circuit structure information is subjected to dynamic behavior simulation to generate simulated power consumption data. Then, the simulated power consumption data is compared and analyzed with the previous dynamic power consumption data to evaluate the optimization effect. Specifically, by performing a difference analysis between the simulated power consumption data and the dynamic power consumption data, the optimization effect can be quantified, potential problems in the optimization process can be identified, and further optimization plans can be proposed based on the analysis results.

[0039] For example, during the power consumption optimization process, if the simulation results show that the power consumption reduction in some areas is not obvious, further optimization can be carried out for these areas, such as re-adjusting the logic gate design or optimizing the power control strategy.

[0040] In this embodiment, by obtaining the circuit structure information of the chip and performing topological analysis on the circuit structure information, a module topology diagram and a functional logic diagram of the circuit are generated. Then, static power consumption characteristics analysis is performed on each module in the module topology diagram to obtain the static power consumption data of each module. Dynamic behavior simulation is performed on the functional logic diagram, and dynamic power consumption characteristics analysis is performed on the simulation results in combination with the timing signals of the chip to generate dynamic power consumption data. Next, the static power consumption data and the dynamic power consumption data are input into a preset power consumption distribution analysis model to perform statistical analysis on the overall power consumption distribution of the chip, generate a global power consumption distribution diagram, and identify power consumption hot spots according to the global power consumption distribution diagram. Subsequently, working mode optimization analysis is performed on the power consumption hot spots to obtain working mode parameters, and the critical paths in the circuit structure information are reconstructed using the working mode parameters to generate the reconstructed circuit structure information. Based on the reconstructed circuit structure information, dynamic behavior simulation is performed on the functional logic diagram again to generate simulation power consumption data. Finally, the simulation power consumption data is compared and analyzed with the dynamic power consumption data, and a power consumption optimization scheme is generated based on the comparison results. The comprehensive analysis and optimization of the chip power consumption are realized, especially in the identification and optimization of power consumption hot spots, which is more accurate. By combining dynamic behavior simulation and static power consumption characteristics analysis, the power consumption of the chip in actual operation can be more accurately reflected. At the same time, through working mode optimization and circuit reconstruction, efficient optimization can be carried out for critical paths, thereby further improving the energy efficiency ratio and overall performance of the chip, and effectively solving the problem in the prior art that it is difficult to quickly generate an optimization path for complex circuit structures.

[0041] Embodiment 2: In step S100, a circuit design file of the chip is decoded by a parsing tool to obtain a number of circuit modules and a number of signal flow paths.

[0042] The circuit design file of the chip is decoded by a parsing tool to specify the circuit modules and signal flow paths inside the chip. Specifically, by parsing the netlist and layout file in the design file, the physical layout and connection method of all circuit modules are identified, and the signal flow paths of each module are extracted.

[0043] For example, by parsing the design file of an SoC chip, the CPU, GPU, memory controller, and various peripheral modules therein, as well as the signal flow paths between these modules, can be extracted, providing a data basis for subsequent topology diagram generation.

[0044] Based on all signal flow paths, the connection relationships between all circuit modules are identified using the depth-first search algorithm to generate a module topology diagram of the chip.

[0045] Traverse and analyze the extracted signal flow paths through the depth - first search algorithm to identify the connection relationships between all circuit modules. Specifically, traverse each node in the signal flow path, record its upstream and downstream connected modules, construct a complete module connection graph, and generate the module topology diagram of the chip.

[0046] For example, when analyzing a certain communication processor chip, using the depth - first search algorithm, the connection relationships between the DSP core and other peripheral modules in the chip can be identified, generating a complete module topology diagram to show the connection and interaction methods of each module.

[0047] Apply the finite - state machine analysis method to perform functional analysis on each circuit module, obtain the functional requirements and working conditions of each module, and construct the functional logic diagram of the circuit according to the functional requirements and working conditions.

[0048] Perform functional analysis on the circuit module through the finite - state machine analysis method to identify the functional requirements and working conditions of each module. Specifically, by defining states and transition rules, simulate the working behavior of the circuit module under different input conditions, obtain the functional requirements and working conditions of each module, and construct the functional logic diagram of the circuit.

[0049] For example, in the analysis of an embedded controller, applying the finite - state machine method can analyze the state transition rules of its various functional modules in different working modes, construct a comprehensive functional logic diagram to help engineers understand the functional logic structure of the chip.

[0050] In step S200, analyze the circuit structure of each module in the module topology diagram through register - transfer - level analysis to obtain the module power - consumption parameters and logical paths. Use the SPICE circuit simulation tool to perform static power - consumption analysis on the module power - consumption parameters and logical paths to obtain the power - consumption analysis results.

[0051] Analyze the circuit structure of each module in the module topology diagram through the register - transfer - level analysis tool to identify the power - consumption parameters and logical paths of the module. Specifically, by analyzing the register - transfer - level design files, extract the register configurations and transfer paths of each module to obtain the power - consumption parameters and logical paths.

[0052] For example, when analyzing a storage controller module, through register - transfer - level analysis, its register configuration and data transfer path can be identified, obtaining the power - consumption parameters and logical paths of the module, providing data input for subsequent power - consumption simulation.

[0053] Calculate the static power consumption of the corresponding module based on the power - consumption analysis results to obtain the static power - consumption data of each module.

[0054] By summarizing and calculating the power consumption analysis results, the static power consumption of each module is obtained. Specifically, by analyzing the static power consumption data such as leakage current and short-circuit current in the simulation results, the static power consumption of each module in different working states is summarized and calculated.

[0055] For example, for a network interface module, by analyzing the leakage current data in its power consumption simulation results, the static power consumption in different data transmission modes is calculated to obtain the static power consumption data of this module.

[0056] Apply the Verilog simulation tool to perform dynamic behavior simulation on the functional logic diagram to obtain simulation excitation signals and power consumption characteristics, perform timing calibration on the simulation excitation signals to obtain calibration signals, and use the power consumption characteristics to simulate the dynamic power consumption distribution of the calibration signals to obtain power consumption simulation data.

[0057] Perform dynamic behavior simulation on the functional logic diagram through the Verilog simulation tool to generate simulation excitation signals and power consumption characteristics. Specifically, by simulating the behavior of the chip under different workloads, record the power consumption characteristics at each time point, and perform timing calibration on the generated simulation excitation signals to obtain calibration signals.

[0058] For example, when simulating a multi-core processor, through Verilog simulation, excitation signals and power consumption characteristics during parallel computing of multiple cores can be generated. Through timing calibration, calibration signals and power consumption simulation data for power consumption distribution simulation are obtained.

[0059] Input the power consumption simulation data and the timing signals of the chip into the power consumption modeling tool for dynamic behavior simulation to obtain dynamic power consumption characteristic data, and use the analytic hierarchy process based on signal power consumption classification to perform timing correlation on the dynamic power consumption characteristic data to obtain the power consumption change curves of each module in different working states.

[0060] By inputting the power consumption simulation data and timing signals into the power consumption modeling tool for dynamic behavior simulation, dynamic power consumption characteristic data is generated. Specifically, by dynamically simulating the power consumption performance of the chip under various working conditions, record and analyze the power consumption data to generate the power consumption change curves of each module.

[0061] For example, when analyzing a video processor, by simulating its dynamic behavior through the power consumption modeling tool, the power consumption change curves of the video processing module at different resolutions and frame rates can be obtained to help understand its power consumption characteristics.

[0062] Use the power consumption change curves to analyze the power consumption fluctuation range and change trend of each circuit module to generate dynamic power consumption data.

[0063] By analyzing the power consumption change curve, the power consumption fluctuation range and change trend of each circuit module are identified. Specifically, through statistical analysis methods, the peaks and valleys in the power consumption change curve are identified to generate dynamic power consumption data.

[0064] For example, when analyzing a wireless communication chip, by statistically analyzing the fluctuation range in its power consumption change curve, the power consumption changes under different signal strengths can be identified to obtain its dynamic power consumption data.

[0065] Among them, the steps of parsing the circuit structure of each module in the module topology diagram through register transfer level (RTL) analysis to obtain module power consumption parameters and logic paths, and using SPICE circuit simulation tools to perform static power consumption analysis on the module power consumption parameters and logic paths to obtain the power consumption analysis results include: using RTL analysis tools to parse the circuit structure of each module in the module topology diagram to obtain voltage supply parameters and node capacitances, and performing correlation analysis on the voltage supply parameters and node capacitances to obtain module power consumption parameters.

[0066] Parse the circuit structure of each module in the module topology diagram through RTL analysis tools to obtain voltage supply parameters and node capacitances. Specifically, by analyzing the voltage supply and node capacitance configurations in the RTL design file and performing correlation analysis, module power consumption parameters are obtained.

[0067] For example, when analyzing a data processing unit, through RTL analysis tools, its voltage supply parameters and node capacitance configurations can be extracted, and correlation analysis can be performed to obtain the power consumption parameters of the module, providing data input for subsequent power consumption simulation.

[0068] Extract the logical paths of each module in the module topology diagram through timing analysis to obtain the logical paths of each module.

[0069] Analyze the module topology diagram through timing analysis tools to extract the logical paths of each module. Specifically, by parsing the timing information in the design file, the signal transmission paths of each module are identified to obtain their logical paths.

[0070] For example, when analyzing a signal processing chip, through timing analysis, the signal transmission paths of its various functional modules can be extracted to obtain the logical path of each module, providing basic data for subsequent power consumption simulation.

[0071] Use SPICE circuit simulation tools to perform static power consumption calculations on module power consumption parameters and logical paths to obtain static power consumption values and leakage current characteristics.

[0072] The static power consumption of the module is calculated for the power consumption parameters and logical paths through a SPICE circuit simulation tool. Specifically, through static simulation, the leakage current characteristics and static power consumption values of each module under different working conditions are obtained.

[0073] For example, when statically simulating an audio processor, the leakage current and static power consumption values under different audio processing modes are calculated through a SPICE tool to obtain the power consumption characteristic data of the module.

[0074] A comprehensive analysis of the static power consumption value and the leakage current characteristics is performed to obtain the power consumption analysis result.

[0075] By analyzing the static power consumption values and leakage current characteristics of each module under different working states, its power consumption performance can be comprehensively understood. Specifically, by comparing the static power consumption data of each module under high-load and low-load states, the changing trend of its leakage current is evaluated, and a power consumption analysis report is generated based on these data.

[0076] For example, in a low-power sensor chip, by comprehensively analyzing its static power consumption value and leakage current characteristics, the power consumption changes under different sensor working modes can be identified, and a detailed power consumption analysis result can be generated to guide subsequent optimization design work.

[0077] In step S300, the static power consumption data and the dynamic power consumption data are classified according to time, module, and working state to obtain the classified data. The classified data is input into a preset power consumption distribution analysis model. In the power consumption distribution analysis model, the classified data is hierarchically processed through a preset multiple power consumption classification criteria, power consumption distribution parameters are generated based on the hierarchical results, the k-means clustering algorithm is used to divide the power consumption distribution parameters into power consumption regions to obtain the power consumption density and distribution range, and a power consumption distribution curve of each circuit module is generated based on the power consumption density and distribution range.

[0078] By classifying the static power consumption data and the dynamic power consumption data according to time, module, and working state, the power consumption performance under different conditions can be more clearly identified and processed. Specifically, through the preset power consumption classification criteria, the classified data is hierarchically processed to obtain accurate power consumption distribution parameters, and the k-means clustering algorithm is used to divide these parameters into regions to generate the power consumption density and distribution range.

[0079] For example, in a processor chip, by classifying its power consumption data according to the execution time of each computing task, the involved modules, and the working state, and applying the k-means clustering algorithm, a power consumption distribution curve under different task modes can be generated to provide a more targeted optimization direction.

[0080] The power consumption distribution curves of all circuit modules are summarized using a power consumption distribution mapping algorithm based on Monte Carlo simulation to obtain the global power consumption distribution map of the entire chip. Regions with power consumption higher than a preset threshold are identified based on the global power consumption distribution map to identify power consumption hotspots in the chip.

[0081] By summarizing the power consumption distribution curves of all circuit modules through a power consumption distribution mapping algorithm based on Monte Carlo simulation, the global power consumption distribution map of the entire chip can be accurately obtained. Specifically, by simulating the power consumption distribution of the chip under different random conditions, mapping analysis is performed on the power consumption data of all circuit modules to obtain the global power consumption distribution map.

[0082] For example, in an artificial intelligence chip, through the Monte Carlo simulation method, comprehensive analysis of the power consumption data during the execution of different algorithms can generate a global power consumption distribution map and identify power consumption hotspots to help optimize the energy efficiency of key modules.

[0083] In step S400, the power consumption hotspots are divided into multiple sub-regions using the segmentation clustering method. The power consumption characteristics of each sub-region are analyzed using a region power consumption analysis method based on grid partitioning to obtain region power consumption parameters, and corresponding working mode parameters are generated based on the region power consumption parameters.

[0084] Dividing the power consumption hotspots into multiple sub-regions through the segmentation clustering method can more accurately analyze and optimize these regions. Specifically, by dividing the power consumption hotspots into multiple sub-regions and applying a region power consumption analysis method based on grid partitioning, the power consumption characteristics of each sub-region are evaluated, and corresponding region power consumption parameters are generated.

[0085] For example, in the optimization of a high-performance processor, the power consumption concentrated region can be divided into several sub-regions using the segmentation clustering method. The power consumption characteristics of each sub-region are analyzed through the grid partitioning method to obtain detailed working mode parameters, providing data support for subsequent optimization.

[0086] The working mode parameters are calibrated and adjusted through a timing optimization algorithm to obtain optimization parameters and scheduling parameters. The optimization parameters and scheduling parameters are input into the circuit structure information, and the critical path is reconstructed in combination with a gate-level optimization algorithm based on Boolean network optimization to obtain the reconstructed circuit structure.

[0087] Calibrating and adjusting the working mode parameters through a timing optimization algorithm can better optimize the power consumption distribution. Specifically, through detailed timing calibration and adjustment of the working mode parameters, optimization parameters and scheduling parameters are obtained. In combination with a gate-level optimization algorithm based on Boolean network optimization, the critical path in the circuit structure information is reconstructed to generate an optimized circuit structure.

[0088] For example, when optimizing a graphics processing chip, by using a timing optimization algorithm to calibrate its operating mode parameters under different graphics processing tasks and reconstructing the critical path through a gate-level optimization algorithm, its power consumption efficiency can be significantly improved, resulting in a better circuit structure.

[0089] Update the signal flow path and module behavior in the functional logic diagram according to the reconstructed circuit structure to obtain the updated circuit structure information, and input the updated circuit structure information into the dynamic simulation model to generate simulation power consumption data.

[0090] Verify its power consumption optimization effect by updating the reconstructed circuit structure information into the functional logic diagram and re-simulating. Specifically, by adjusting the signal flow path and module behavior, input the updated circuit structure information into the dynamic simulation model for power consumption simulation to obtain the updated simulation power consumption data.

[0091] For example, during the optimization process of a memory controller, by updating its circuit structure information and re-simulating, the power consumption performance of the new design in actual operation can be verified, and the optimized simulation power consumption data can be generated.

[0092] In step S500, use a data comparison and analysis tool to compare and analyze the simulation power consumption data and the dynamic power consumption data, extract the similar and different parts in the simulation power consumption data and the dynamic power consumption data, and obtain the comparison result.

[0093] By using a data comparison and analysis tool to compare and analyze the simulation power consumption data and the dynamic power consumption data, the optimization effect can be comprehensively evaluated. Specifically, by analyzing the power consumption data in simulation and actual operation, identify the similarities and differences, and generate the comparison and analysis result.

[0094] For example, after optimizing an embedded chip, through a comparison and analysis tool, the similar parts and differences between the simulation data and the actual power consumption data can be identified to evaluate the effect of the optimization scheme.

[0095] Use the difference analysis method to identify the circuit modules with significant power consumption changes in the comparison result and generate the corresponding power consumption optimization scheme.

[0096] Use the difference analysis method to conduct a detailed analysis of the parts with significant power consumption changes in the comparison result, identify the circuit modules that need further optimization, and generate a targeted power consumption optimization scheme. Specifically, through the high-power consumption areas identified in the comparison and analysis, propose corresponding improvement measures to form an optimization scheme.

[0097] For example, during the power consumption optimization process of a communication chip, through difference analysis, identify the modules with significant power consumption changes in the high data transmission mode and generate the corresponding optimization scheme to improve its energy efficiency.

[0098] In this embodiment, by obtaining the circuit design file of the chip and decoding it, circuit modules and signal flow paths are extracted. Combining the depth-first search algorithm and the finite state machine analysis method, a module topology diagram and a functional logic diagram are generated. Through register transfer level analysis and SPICE simulation tools, a detailed static power consumption analysis of the circuit structure is carried out to obtain the static power consumption data of each module. Using Verilog simulation tools and power consumption modeling tools, a dynamic behavior simulation of the functional logic diagram is performed to generate dynamic power consumption characteristic data. Through Monte Carlo simulation and k-means clustering algorithm, the power consumption data is summarized and analyzed to generate a global power consumption distribution map and identify the power consumption hot spots. Further, through the segmentation clustering method and the timing optimization algorithm, the working mode of the hot spot area is optimized, the critical path is reconstructed, and the circuit structure information is updated. Finally, through the data comparison and analysis tool, the simulated power consumption data and the dynamic power consumption data are compared and analyzed to generate a power consumption optimization scheme, thereby improving the energy efficiency and performance of the chip and realizing refined power consumption optimization management.

[0099] Embodiment 3: As Figure 2 shown, the present application also provides a chip power consumption analysis and optimization system 10, including an acquisition unit 11, a simulation unit 12, an analysis unit 13, a reconstruction unit 14, and an optimization unit 15.

[0100] The acquisition unit 11 is mainly used to obtain the circuit structure information of the chip, perform topological analysis on the circuit structure information, and generate a module topology diagram and a functional logic diagram of the circuit.

[0101] The simulation unit 12 is mainly used to perform static power consumption characteristic analysis on each module in the module topology diagram to obtain the static power consumption data of each module, perform dynamic behavior simulation on the functional logic diagram, and perform dynamic power consumption characteristic analysis on the simulation results in combination with the timing signals of the chip to generate dynamic power consumption data.

[0102] The analysis unit 13 is mainly used to input the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, perform statistical analysis on the overall power consumption distribution of the chip, generate a global power consumption distribution map, and identify the power consumption hot spots according to the global power consumption distribution map.

[0103] The reconstruction unit 14 is mainly used to perform working mode optimization analysis on the power consumption hot spot area to obtain working mode parameters, use the working mode parameters to reconstruct the critical path in the circuit structure information, generate the reconstructed circuit structure information, and based on the reconstructed circuit structure information, perform dynamic behavior simulation on the functional logic diagram again to generate simulated power consumption data.

[0104] The optimization unit 15 is mainly used to compare and analyze the simulated power consumption data and the dynamic power consumption data, and generate a power consumption optimization scheme based on the comparison result.

[0105] In this embodiment, the acquisition unit 11 acquires the circuit structure information of the chip, performs topological analysis on it, generates the module topology diagram and functional logic diagram of the circuit, and provides basic data for subsequent power consumption analysis and optimization. The simulation unit 12 uses a static power consumption characteristic analysis tool to analyze each module in the module topology diagram to obtain the static power consumption data of each module. At the same time, the simulation unit 12 also performs dynamic behavior simulation on the functional logic diagram, combines the timing signals of the chip, and generates dynamic power consumption data. The analysis unit 13 inputs the static power consumption data and dynamic power consumption data into a preset power consumption distribution analysis model, statistically analyzes the overall power consumption distribution of the chip, generates a global power consumption distribution diagram, and identifies the power consumption hot spot areas according to the global power consumption distribution diagram. The reconstruction unit 14 performs working mode optimization analysis on the power consumption hot spot areas to obtain working mode parameters, uses these parameters to reconstruct the critical paths in the circuit structure information, and generates the reconstructed circuit structure information. Based on the reconstructed circuit structure information, the simulation unit 12 performs dynamic behavior simulation again to generate simulation power consumption data. The optimization unit 15 compares and analyzes the simulation power consumption data with the dynamic power consumption data, extracts the similar and different parts, generates a power consumption optimization scheme based on the comparison result, and finally improves the energy efficiency and performance of the chip. Through a systematic analysis and optimization process, it is possible to effectively identify and optimize the power consumption hot spot areas, and achieve refined power consumption management and optimization.

[0106] It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described system and each unit can refer to the corresponding processes in the foregoing embodiment of a chip power consumption analysis and optimization method, and will not be elaborated herein.

[0107] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip power consumption analysis and optimization method, characterized in that: include: Obtaining circuit structure information of the chip, performing topological analysis on the circuit structure information, and generating a module topological diagram and a functional logic diagram of the circuit; Performing static power consumption characteristic analysis on each module in the module topology diagram to obtain static power consumption data of each module, performing dynamic behavior simulation on the functional logic diagram, performing dynamic power consumption characteristic analysis on the simulation result in combination with the timing signal of the chip, and generating dynamic power consumption data; Inputting the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, performing statistical analysis on the power consumption distribution of the entire chip, generating a global power consumption distribution map, and identifying power consumption hot spots according to the global power consumption distribution map; Performing an operating mode optimization analysis on the power consumption hotspot area to obtain operating mode parameters, reconstructing the critical path in the circuit structure information using the operating mode parameters to generate reconstructed circuit structure information, and re-performing a dynamic behavior simulation on the functional logic diagram based on the reconstructed circuit structure information to generate simulated power consumption data; The simulated power consumption data is compared and analyzed with the dynamic power consumption data, and a power consumption optimization solution is generated based on the comparison result.

2. The chip power consumption analysis and optimization method according to claim 1, characterized in that: The steps of obtaining the circuit structure information of the chip, performing topological analysis on the circuit structure information, and generating a module topological diagram and a functional logic diagram of the circuit include: Decode the circuit design file of the chip through the parsing tool to obtain several circuit modules and several signal flow paths; Based on all the signal flow paths, a depth-first search algorithm is used to identify the connection relationship between all the circuit modules, and a module topology diagram of the chip is generated; The finite state machine analysis method is applied to perform functional analysis on each circuit module to obtain the functional requirements and working conditions of each module, and a functional logic diagram of the circuit is constructed according to the functional requirements and the working conditions.

3. The chip power consumption analysis and optimization method according to claim 1, characterized in that: The steps of performing static power consumption characteristic analysis on each module in the module topology diagram to obtain static power consumption data of each module, performing dynamic behavior simulation on the functional logic diagram, performing dynamic power consumption characteristic analysis on the simulation result in combination with the timing signal of the chip, and generating dynamic power consumption data include: The circuit structure of each module in the module topology diagram is analyzed by register transfer level analysis to obtain module power consumption parameters and logic paths, and a SPICE circuit simulation tool is used to perform static power consumption analysis on the module power consumption parameters and the logic paths to obtain power consumption analysis results; Calculate the static power consumption of the corresponding module based on the power consumption analysis result to obtain the static power consumption data of each module; Using a Verilog simulation tool to perform dynamic behavior simulation on the functional logic diagram to obtain a simulation excitation signal and a power consumption characteristic, and performing timing calibration on the simulation excitation signal to obtain a calibration signal, and using the power consumption characteristic to perform dynamic power consumption distribution simulation on the calibration signal to obtain power consumption simulation data; Input the power consumption simulation data and the timing signal of the chip into the power consumption modeling tool for dynamic behavior simulation to obtain dynamic power consumption characteristic data, and use the hierarchical analysis method based on signal power consumption classification to perform timing correlation on the dynamic power consumption characteristic data to obtain the power consumption change curve of each module under different working states; The power consumption variation curve is used to analyze the power consumption fluctuation range and variation trend of each circuit module to generate dynamic power consumption data.

4. The chip power consumption analysis and optimization method according to claim 3, characterized in that: The step of parsing the circuit structure of each module in the module topology diagram by register transfer level analysis to obtain module power consumption parameters and logic paths, and performing static power consumption analysis on the module power consumption parameters and the logic paths by using a SPICE circuit simulation tool to obtain power consumption analysis results includes: Analyzing the circuit structure of each module in the module topology diagram using a register transfer level analysis tool to obtain voltage supply parameters and node capacitance, and correlating the voltage supply parameters with the node capacitance to obtain module power consumption parameters; Extracting the logic path of each module in the module topology diagram through timing analysis to obtain the logic path of each module; Using a SPICE circuit simulation tool to calculate the static power consumption of the module power consumption parameters and the logic path to obtain a static power consumption value and a leakage current characteristic; The static power consumption value and the leakage current characteristic are comprehensively analyzed to obtain a power consumption analysis result.

5. The chip power consumption analysis and optimization method according to claim 1, characterized in that: The step of inputting the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, performing statistical analysis on the power consumption distribution of the entire chip, generating a global power consumption distribution map, and identifying power consumption hot spots according to the global power consumption distribution map includes: The static power consumption data and the dynamic power consumption data are classified according to time, module and working state to obtain classified data, and the classified data is input into a preset power consumption distribution analysis model. In the power consumption distribution analysis model, the classified data is hierarchically processed according to a plurality of preset power consumption classification standards, and power consumption distribution parameters are generated based on the hierarchical results. The power consumption distribution parameters are divided into power consumption areas using a k-means clustering algorithm to obtain power consumption density and distribution range, and power consumption distribution curves of each circuit module are generated based on the power consumption density and distribution range; The power consumption distribution curves of all circuit modules are summarized using a power consumption distribution mapping algorithm based on Monte Carlo simulation to obtain a global power consumption distribution map of the entire chip. According to the global power consumption distribution map, areas with power consumption higher than a preset threshold are marked to identify power consumption hotspots in the chip.

6. The chip power consumption analysis and optimization method according to claim 1, characterized in that: The step of performing working mode optimization analysis on the power consumption hotspot area to obtain working mode parameters, reconstructing the critical path in the circuit structure information using the working mode parameters to generate reconstructed circuit structure information, and re-performing dynamic behavior simulation on the functional logic diagram based on the reconstructed circuit structure information to generate simulation power consumption data includes: The power consumption hotspot area is divided into multiple sub-areas by using a segmentation clustering method, and the power consumption characteristics of each sub-area are analyzed by using a regional power consumption analysis method based on grid division to obtain regional power consumption parameters, and corresponding working mode parameters are generated based on the regional power consumption parameters; Calibrate and adjust the working mode parameters through a timing optimization algorithm to obtain optimization parameters and scheduling parameters, input the optimization parameters and scheduling parameters into circuit structure information, and reconstruct the critical path in combination with a gate-level optimization algorithm based on Boolean network optimization to obtain a reconstructed circuit structure; The signal flow path and module behavior in the functional logic diagram are updated according to the reconstructed circuit structure to obtain updated circuit structure information, and the updated circuit structure information is input into a dynamic simulation model to generate simulation power consumption data.

7. The chip power consumption analysis and optimization method according to claim 1, characterized in that: The step of comparing and analyzing the simulation power consumption data with the dynamic power consumption data, and generating a power consumption optimization solution based on the comparison result, includes: Comparing and analyzing the simulated power consumption data and the dynamic power consumption data by using a data comparison and analysis tool, extracting similarities and differences between the simulated power consumption data and the dynamic power consumption data, and obtaining a comparison result; A difference analysis method is used to identify circuit modules with significant power consumption changes in the comparison results and generate corresponding power consumption optimization solutions.

8. A chip power consumption analysis and optimization system, characterized in that: include: An acquisition unit, used to acquire circuit structure information of a chip, perform topological analysis on the circuit structure information, and generate a module topology diagram and a functional logic diagram of the circuit; A simulation unit, used to perform static power consumption characteristic analysis on each module in the module topology diagram to obtain static power consumption data of each module, perform dynamic behavior simulation on the functional logic diagram, perform dynamic power consumption characteristic analysis on the simulation result in combination with the timing signal of the chip, and generate dynamic power consumption data; An analysis unit, configured to input the static power consumption data and the dynamic power consumption data into a preset power consumption distribution analysis model, perform statistical analysis on the power consumption distribution of the entire chip, generate a global power consumption distribution map, and identify power consumption hot spots according to the global power consumption distribution map; A reconstruction unit, configured to perform an operation mode optimization analysis on the power consumption hotspot area to obtain operation mode parameters, reconstruct a key path in the circuit structure information using the operation mode parameters to generate reconstructed circuit structure information, and re-perform a dynamic behavior simulation on the functional logic diagram based on the reconstructed circuit structure information to generate simulation power consumption data; The optimization unit is used to compare and analyze the simulation power consumption data with the dynamic power consumption data, and generate a power consumption optimization solution based on the comparison result.

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