Brain-like chip compiling method and device, electronic equipment and storage medium

Abstract

The invention provides a brain-like chip compiling method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that on the basis of the topological connection relation between neuron nodes and synaptic connection nodes in a target computational graph, all neuron unit nodes in the target computational graph are grouped, and multiple target routing groups are obtained, carrying out segmentation optimization on a weight matrix of target synaptic connection nodes in the target calculation graph to obtain an optimized weight matrix of the target synaptic connection nodes, and allocating a routing coordinate for indicating the position of a calculation core of each target routing group in the brain-like chip for each target routing group, and further generating configuration information of the calculation core and an executable file comprising a binary instruction which can be identified by the brain-like chip. According to the brain-like chip compiling method and device, the electronic equipment and the storage medium, the brain-like chip compiling efficiency and configuration accuracy can be improved, calculation resource allocation of the brain-like chip can be optimized, and the brain-like chip compiling method and device have wide application prospects.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a brain-like chip compilation method, device, electronic device and storage medium. Background Art

[0002] As a carrier of brain-like computing, the design principle of brain-like chips is deeply inspired by the structure of biological brains. It aims to achieve efficient large-scale parallel computing by simulating neurons and the synaptic connections between them. Brain-like chips usually integrate a variety of hardware modules, including neuron computing circuits, synaptic computing circuits, storage modules for storing weight data and neuron attributes, as well as control modules, scheduling modules and routing modules responsible for coordinating the work of various components. The hardware modules in brain-like chips together constitute a computing core, and multiple computing cores are connected through the network on chip (NoC) to form a complete brain-like chip architecture. The computing cores are arranged in an array and data communication between each other is achieved through the network on chip. The output generated by the computing core can be directly transmitted to one or more other cores, or it can be transmitted to the outside of the chip.

[0003] By compiling brain-like chips, application models (such as neural network models) can be converted into binary instructions that can be recognized by the hardware modules of the brain-like chips, so that the algorithms can be deployed in the brain-like chips.

[0004] When compiling a brain-like chip, it is necessary to deeply understand the hardware architecture of the brain-like chip and the computing requirements of the application model to ensure the correct mapping and configuration. However, since the structure of the application model is usually complex and changeable, there is a huge design space when mapping the application model to the hardware module of the brain-like chip, resulting in low efficiency and prone to configuration errors when compiling the brain-like chip based on the traditional brain-like chip compilation method in the related technology. Therefore, how to improve the efficiency and configuration accuracy of brain-like chip compilation is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] The present invention provides a brain-like chip compilation method, device, electronic device and storage medium, which are used to solve the defects of low efficiency and easy configuration errors in the prior art when compiling brain-like chips, and to improve the efficiency and configuration accuracy of brain-like chip compilation.

[0006] The present invention provides a brain-like chip compilation method, comprising the following steps.

[0007] Based on the topological connection relationship between neuron nodes and synaptic connection nodes in the target computational graph, group each neuron unit node in the target computational graph to obtain multiple target routing groups. Any neuron node in the target computational graph represents a neuron unit in the brain-inspired chip, and any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-inspired chip. The unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes; Partition and optimize the weight matrix of the target synaptic connection node in the target computational graph to obtain the optimized weight matrix of the target synaptic connection node; Assign routing coordinates for each target routing group to indicate the position of each target routing group in the computing core of the brain-inspired chip. Then, based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node, generate the configuration information of the computing core; Generate an executable file based on the configuration information of the computing core. The executable file includes binary instructions recognizable by the brain-inspired chip.

[0008] The present invention also provides a brain-inspired chip compilation device, including the following modules: A routing grouping module, configured to group each neuron unit node in the target computational graph to obtain multiple target routing groups. Any neuron node in the target computational graph represents a neuron unit, and any synaptic connection node in the target computational graph represents a synaptic connection unit. The unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes; A weight optimization module, configured to partition and optimize the weight matrix of the target synaptic connection node in the target computational graph to obtain the optimized weight matrix of the target synaptic connection node; A configuration generation module, configured to assign routing coordinates for each target routing group to indicate the position of each target routing group in the computing core of the brain-inspired chip. Then, based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node, generate the configuration information of the computing core; A file generation module, configured to generate an executable file based on the configuration information of the computing core. The executable file includes binary instructions recognizable by the brain-inspired chip.

[0009] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method for compiling a brain-inspired chip as described in any one of the above is implemented.

[0010] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method for compiling a brain-inspired chip as described in any one of the above is implemented.

[0011] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the method for compiling a brain-inspired chip as described in any one of the above is implemented.

[0012] The method for compiling a brain-inspired chip, device, electronic device, and storage medium provided by the present invention group the neuron unit nodes in a target computation graph to obtain a plurality of target routing groups, and partition and optimize the weight matrix of the target synaptic connection nodes in the target computation graph to obtain the optimized weight matrix of the target synaptic connection nodes. Furthermore, routing coordinates for indicating the position of each target routing group in the computing cores of the brain-inspired chip are assigned to each target routing group. Based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection nodes, configuration information of the computing cores is generated. Based on the configuration information of the computing cores, an executable file is generated, which can improve the efficiency and configuration accuracy of brain-inspired chip compilation, optimize the computing resource allocation of the brain-inspired chip, and has broad application prospects. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0014] Figure 1 is one of the flow diagrams of the method for compiling a brain-inspired chip provided by the present invention.

[0015] Figure 2 is another flow diagram of the method for compiling a brain-inspired chip provided by the present invention.

[0016] Figure 3 is one of the connection diagrams of the target computation graph in the method for compiling a brain-inspired chip provided by the present invention.

[0017] Figure 4 is another connection diagram of the target computation graph in the method for compiling a brain-inspired chip provided by the present invention.

[0018] Figure 5 It is one of the combination methods of the hardware unit combinations corresponding to the complex operators in the compilation method of the brain-inspired chip provided by the present invention.

[0019] Figure 6 It is the second combination method of the hardware unit combinations corresponding to the complex operators in the compilation method of the brain-inspired chip provided by the present invention.

[0020] Figure 7 It is the third combination method of the hardware unit combinations corresponding to the complex operators in the compilation method of the brain-inspired chip provided by the present invention.

[0021] Figure 8 It is a schematic flow chart of generating a target computation graph in the compilation method of the brain-inspired chip provided by the present invention.

[0022] Figure 9 It is a schematic diagram of the evolution of the target computation graph in the compilation method of the brain-inspired chip provided by the present invention.

[0023] Figure 10 It is a schematic structural diagram of the target routing group in the compilation method of the brain-inspired chip provided by the present invention.

[0024] Figure 11 It is a corresponding relationship diagram between the target computation graph and the structure of the computing cores in the brain-inspired chip in the neural network deployment method provided by the present invention.

[0025] Figure 12 It is a schematic flow chart of segmenting and optimizing the target synaptic connection nodes in the compilation method of the brain-inspired chip provided by the present invention.

[0026] Figure 13 It is a schematic flow chart of performing row-column transformation on the synaptic connection nodes in the compilation method of the brain-inspired chip provided by the present invention.

[0027] Figure 14 It is a schematic structural diagram of the brain-inspired chip compilation device provided by the present invention.

[0028] Figure 15 It is a schematic structural diagram of the electronic device provided by the present invention. Specific Embodiments

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0030] In the description of the invention, it should be noted that unless otherwise clearly specified or defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same kind, and do not limit the number of objects. For example, the first object can be one or multiple. In addition, in the description of the present application, " / " represents at least one of the connected objects, and the character " / " generally represents an "or" relationship between the associated objects before and after.

[0032] It should be noted that as the carrier of brain-like computing, the design principle of the brain-like chip is deeply inspired by the structure of the biological brain, aiming to achieve efficient large-scale parallel computing by simulating neurons and their synaptic connections. Such a chip usually integrates multiple modules, including neuron computing circuits, synaptic computing circuits, a storage module for storing weight data and neuron attributes and other information, as well as a control module, a scheduling module, and a routing module responsible for coordinating the work of each component. These modules together form a computing core, and multiple computing cores are connected through a Network on Chip (NoC) to form a complete brain-like chip architecture. The computing cores are arranged in an array form to achieve data communication with each other through the on-chip network; the output generated by the computing cores can be directly transmitted to one or more other cores, or transmitted to the outside of the chip. In addition, multiple brain-like chips can also be cascaded in an array form and communicate efficiently between chips through a specially designed protocol, thereby constructing a larger-scale computing system.

[0033] Deploying application models (such as neural network models) to brain-like chips can be achieved by compiling brain-like chips. When deploying application models to brain-like chips based on traditional brain-like chip compilation methods in related technologies, there are still the following shortcomings: First, most of the commonly used neural network models are designed and trained based on mainstream deep learning frameworks (such as TensorFlow, PyTorch, and SpikingJelly, etc.). The main target hardware platforms of the above frameworks are usually central processing units (CPUs) and graphics processing units (GPUs), not brain-like chips. The neural network models designed and trained based on the above mainstream deep learning frameworks cannot be directly deployed and run on brain-like chips, and additional conversion and adaptation work is required.

[0034] Secondly, when compiling brain-like chips, it is necessary to deeply understand the hardware architecture of brain-like chips and the computing requirements of application models to ensure the correct mapping and configuration. However, since the structure of application models is usually complex and changeable, there is a huge design space when mapping application models to the hardware modules of brain-like chips. As a result, when compiling brain-like chips based on traditional brain-like chip compilation methods in related technologies, it is necessary to configure each neuron and synapse in detail, which is not only inefficient but also prone to configuration errors, thus affecting the compilation efficiency and the reliability of the compiled brain-like chips.

[0035] Finally, the traditional brain-like chip compilation method in the related art lacks optimization and adaptation for the hardware characteristics of brain-like chips. Brain-like chips have unique hardware architectures, such as large-scale parallel computing units and low-power design. If these hardware characteristics are not fully utilized when compiling brain-like chips, the hardware resources of brain-like chips will not be fully utilized, and their unique architectural advantages will not be fully utilized.

[0036] Therefore, the compilation technology of brain-like chips has become a bottleneck for the development, efficient utilization and widespread application of brain-like chips. The traditional brain-like chip compilation method based on related technologies is difficult to automatically, accurately and efficiently convert the application model into executable code for brain-like chips, especially when dealing with large-scale and complex neural network models. The optimization and scheduling problems in the compilation process of brain-like chips are particularly prominent. Therefore, how to improve the compilation efficiency and configuration reliability of brain-like chips is a technical problem that needs to be solved urgently in this field.

[0037] Combine the following Figures 1 - 13 The present invention describes the brain-like chip compilation method provided by the present invention.

[0038] Figure 1 This is one of the flow charts of the brain-like chip compilation method provided by the present invention. Figure 2It is the second flowchart of the compilation method of the brain-inspired chip provided by the present invention. As Figure 1 and Figure 2 shown, the method includes the following: Step 101 groups each neuron unit node in the target computational graph based on the topological connection relationship between neuron nodes and synaptic connection nodes in the target computational graph, obtaining multiple target routing groups. Any neuron node in the target computational graph represents a neuron unit in the brain-inspired chip, any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-inspired chip, and the unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes.

[0039] It should be noted that the execution subject of the embodiments of the present invention is a brain-inspired chip compilation device. The above-mentioned brain-inspired chip compilation device can be configured in an electronic device such as a computer or a server.

[0040] Specifically, the compilation method of the brain-inspired chip provided by the present invention is used to convert the target computational graph into binary instructions executable by the brain-inspired chip.

[0041] It should be noted that the neuron unit and the synaptic connection unit are important hardware units in the brain-inspired chip. In the brain-inspired chip, the combination of the neuron unit and the synaptic connection unit constitutes the basic architecture of the brain-inspired chip.

[0042] Among them, the neuron unit is usually implemented as a circuit with multiple inputs. The input signal acts on the membrane level accumulation process of the neuron, thereby affecting its output state. The output of the neuron unit is usually an analog signal or a digital signal, depending on the design and implementation method of the chip.

[0043] The types of neuron units in the embodiments of the present invention may include, but are not limited to, basic (Neuron) neuron units, IF (integrate-and-fire) neuron units, LIF (leaky integrate-and-fire) neuron units, continuous spiking neuron units, periodic spiking neuron units, etc. The encapsulation of the neuron unit includes not only input-output characteristics but also the update logic of the internal state. Each neuron unit will ultimately call the update method of the parent MetaNeuron.

[0044] The synaptic connection unit in the brain-inspired chip is used to connect neuron units and transmit signals. The synaptic connection unit mimics the synaptic connections between biological neurons, meaning that signals can only be transmitted from one neuron unit to another via this synaptic connection unit and cannot be transmitted in the reverse direction. The synaptic connection unit is usually implemented as a circuit with programmable weights. These weights can be adjusted through training to change the transmission strength of the synaptic connection unit for input signals.

[0045] The types of synaptic connection units in the embodiments of the present invention may include basic synaptic connection units, fully connected synaptic connection units, convolutional synaptic connection units, and 2D matrix multiplication synaptic connection units, etc. Different types of synaptic connection units are suitable for different network connection methods and neural network models. For example, the fully connected synaptic connection unit corresponds to the fully connected in the neural network, and the convolutional synaptic connection unit corresponds to the convolutional connection in the neural network.

[0046] Figure 3 It is one of the connection schematic diagrams of the target computation graph in the brain-inspired chip compilation method provided by the present invention. Figure 4 It is the second connection schematic diagram of the target computation graph in the brain-inspired chip compilation method provided by the present invention. As Figure 3 and Figure 4 shown, the hardware nodes in the target computation graph in the embodiments of the present invention may include neuron nodes and synaptic connection nodes. Any neuron node in the target computation graph represents a neuron unit in the brain-inspired chip, and any synaptic connection node in the target computation graph represents a synaptic connection unit in the brain-inspired chip.

[0047] The input side of any synaptic connection node can only be connected to one neuron node, and the output side of the above synaptic connection node can also only be connected to one neuron node, indicating that the forward direction of any synaptic connection unit can only be connected to one neuron unit, and the backward direction of the above synaptic connection unit can also only be connected to one neuron unit.

[0048] The input side and the output side of any neuron node can be respectively connected to one or more synaptic connection nodes, indicating that the neuron unit represented by the above neuron node can have one or more inputs and one or more outputs.

[0049] It should be noted that Figure 3 and Figure 4 The numbers in represent the identification information of the hardware nodes in the target computation graph, Figure 3 and Figure 4 The identification information of the hardware nodes shown in is only illustrative.

[0050] It should be noted that the target computation graph in the embodiments of the present invention can be generated based on various methods. For example, the target computation graph can be designed by chip engineers based on actual requirements.

[0051] Optionally, the target computation graph in the embodiments of the present invention can be generated based on the network structure of the target neural network and the target mapping relationship. Among them, the above-mentioned target neural network can be designed and trained based on mainstream deep learning frameworks (such as TensorFlow, PyTorch, and SpikingJelly, etc.), and the above-mentioned target neural network can be determined based on actual requirements.

[0052] It should be noted that in the target mapping relationship, complex operators in the neural network can be equivalently replaced by a combination of hardware units connecting one or more synaptic connection units and one or more neuron units according to the conversion method. When the hardware unit combination corresponding to the complex operator is regarded as a whole, the above-mentioned hardware unit combination can receive the outputs of one or more neuron units and output them to one or more synaptic connection units. It can be understood that the input-side behavior of the hardware unit combination corresponding to the complex operator is similar to that of the synaptic connection unit because it receives the outputs from the neuron units; the output-side behavior of the hardware unit combination corresponding to the complex operator is similar to that of the neuron unit because it transmits the output to the synaptic connection unit. The combination method of the hardware unit combination corresponding to the complex operator can be any combination method that satisfies the connection rules of the neuron unit and the synaptic connection unit.

[0053] It can be understood that in a neural network, an operator usually refers to a function or operator that performs specific operations on data. The above-mentioned specific operations can include but are not limited to mathematical operations, transformations, and activation functions, etc., for implementing various functions in the neural network. The types of operators in the neural network can include but are not limited to convolution operators (ConvolutionOperator), pooling operators (Pooling Operator), fully connected operators (Fully Connected Operator), activation operators (Activation Function), Dropout operators, Softmax operators, loss function operators, arithmetic operators (including addition, subtraction, multiplication, division, etc., for performing basic mathematical operations), and linear algebra operators (such as matrix multiplication, transpose, inversion, etc., for processing vectors and matrices), etc. By combining these operators, an efficient and accurate neural network can be constructed.

[0054] It should be noted that in the embodiments of the present invention, the types of operators in the neural network may also include input node operators and output node operators. The input node operator represents the data input port of the neural network, and the output node operator represents the data output port of the neural network. The input node operator is responsible for receiving external data and passing the data to other operators, and the output node operator is used to send the received data to external devices. The input node in the target computation graph may represent the input node operator in the target neural network, and the output node in the target computation graph may represent the output node operator in the target neural network.

[0055] It should be noted that in the embodiments of the present invention, the types of operators in the neural network may also include complex operators. A complex operator is an encapsulation of operators with specific logical functions in the neural network.

[0056] Figure 5 is one of the combination ways of the hardware unit combinations corresponding to the complex operators in the brain-inspired chip compilation method provided by the present invention. As Figure 5 shown, the hardware unit combination corresponding to the complex operator may be a combination of a synaptic connection unit and a neuron unit.

[0057] Figure 6 is the second combination way of the hardware unit combinations corresponding to the complex operators in the brain-inspired chip compilation method provided by the present invention. As Figure 6 shown, the hardware unit combination corresponding to the complex operator may be a combination of two synaptic connection units and a neuron unit.

[0058] Figure 7 is the third combination way of the hardware unit combinations corresponding to the complex operators in the brain-inspired chip compilation method provided by the present invention. As Figure 7 shown, the hardware unit combination corresponding to the complex operator may be a combination of multiple synaptic connection units and multiple neuron units.

[0059] For example, bit operation operators, as a type of complex operator, include BitwiseAND operators, BitwiseOR operators, and BitwiseXOR operators. Arithmetic operators, as a type of complex operator, include SpikingAdd operators, SpikingSub operators, SpikingAvgPool1d operators, SpikingMaxPool1d operators, etc. These complex operators overall implement specific functional logics, and the internal build method predefines conversion methods for equivalently replacing themselves with specific hardware unit combinations while maintaining the same external connection relationships as the original operators.

[0060] It should be noted that Figures 4 - 7The numbers therein represent the identification information of hardware units. Figures 4 - 7 The identification information of the shown hardware units is only illustrative.

[0061] Figure 8 It is a schematic flowchart of generating a target computation graph in the compilation method of the brain-inspired chip provided by the present invention. As Figure 8 shown, the specific steps of generating the target computation graph include: based on the network structure of the target neural network, generating an original computation graph corresponding to the target neural network. Any operator node in the original computation graph represents an operator in the target neural network, and the unidirectional arrow used to connect two operator nodes in the original computation graph represents the input-output relationship between the two operator nodes.

[0062] It should be noted that a computation graph is a data structure used to represent the composition structure and connection relationship of a neural network. A computation graph is a directed graph. The nodes in the computation graph represent the operators in the neural network, and the edges represent the connection relationships between the operators. Except for the input nodes and output nodes, the in-degree and out-degree of each node are both greater than 0. The edges represent the execution order and data flow direction of the operators through unidirectional arrows.

[0063] By analyzing the network structure of the target neural network, an original computation graph corresponding to the target neural network can be generated.

[0064] For a type of operator nodes in the original computation graph, based on the first mapping sub-relationship in the target mapping relationship, the type of operator nodes are replaced with hardware unit nodes. For a second type of operator nodes in the original computation graph, based on the second mapping sub-relationship in the target mapping relationship, the second type of operator nodes are replaced with complex operator nodes, obtaining an intermediate computation graph corresponding to the target neural network. The first mapping sub-relationship is used to describe the mapping relationship between a type of operators in the neural network and the hardware units in the brain-inspired chip, and the second mapping sub-relationship is used to describe the mapping relationship between the second type of operators in the neural network and the complex operators. The first type of operators and the second type of operators in the neural network are predefined. Any type of operator node in the original computation graph represents a type of operator, any second type of operator node in the original computation graph represents a second type of operator, and any complex operator node in the intermediate computation graph represents a complex operator.

[0065] It should be noted that the first mapping sub-relationship in the embodiments of the present invention can be determined based on prior knowledge and / or actual situations. The first mapping sub-relationship is shown in Table 1.

[0066] Table 1 Schematic Table of the First Mapping Sub-relationship

[0067] It should be noted that some operations are defined by objects in Pytorch or SpikingJelly, and this operator can be called to perform operations; while others are defined using mathematical operators (+, -, ×, / ). The operator in the embodiment of the present invention also supports some forms of calculation using operators, that is, the brain-inspired chip can perform these forms of calculation.

[0068] For a type of operator node in the original computation graph, based on the first mapping sub-relationship in the target mapping relationship, the type of operator node is replaced one-to-one with a hardware unit. During the replacement process, all attributes and configuration information of the type of operator node will be accurately transferred to the hardware unit node to ensure that the converted hardware unit node is completely consistent with the original type of operator node in function.

[0069] The second mapping sub-relationship in the embodiment of the present invention can be determined based on prior knowledge and / or actual situations. The second mapping sub-relationship is shown in Table 2.

[0070] Table 2 Schematic Table of the Second Mapping Sub-relationship

[0071] For the type-two operator nodes in the original computation graph, there is no hardware unit node that can be directly and equivalently replaced for the above type-two operators. Therefore, during the construction stage of the target neural network, the type-two operators are regarded as an indivisible whole. Before the target neural network is deployed to the brain-inspired chip, the type-two operators are approximately replaced with complex operators to ensure that after generating the target computation graph based on the target neural network, the brain-inspired chip can be accurately compiled based on the target computation graph.

[0072] The conversion between the type-two operator nodes and the complex operator nodes strictly follows the principle of equivalent replacement, that is, to ensure that the output result under the same input conditions is consistent with the original target neural network. The specific conversion rules are shown in Table 2. During the conversion process, the structure information and weight data of the type-two operators will be appropriately adjusted and mapped to be applicable to the complex operators and the corresponding hardware unit groups, while maintaining the consistency of the data flow structure and the accuracy of the operation results.

[0073] It should be noted that when replacing the type-one operator nodes in the original computation graph with hardware unit nodes and replacing the type-two operator nodes with complex operator nodes, the external connection relationships of the type-one operator nodes and the type-two operator nodes are retained.

[0074] Based on the third mapping sub-relationship in the target mapping relationship, the complex operator nodes in the intermediate computation graph are replaced with hardware units to obtain the target computation graph. The third mapping sub-relationship is used to describe the mapping relationship between the complex operators in the neural network and the hardware units in the brain-inspired chip.

[0075] It should be noted that the third mapping sub-relationship in the embodiments of the present invention can be determined based on prior knowledge and / or actual situations. The third mapping sub-relationship is shown in Table 3.

[0076] Table 3 Schematic Table of the Third Mapping Sub-relationship

[0077] Figure 9 is a schematic diagram of the evolution of the target computation graph in the compilation method of the brain-inspired chip provided by the present invention. As Figure 9 shown, the evolution process of the original computation graph corresponding to the target neural network evolving into an intermediate computation graph and then into a target computation graph is as Figure 9 shown. Figure 9 The dashed arrows in it represent the replacement correspondence relationships between a type of operator and hardware units, and between a type-two operator and complex operators and hardware units. Figure 9 The dashed box in it shows that the complex operator of pulse addition is equivalently replaced by the connection combination of two basic synaptic connection units and one basic neuron unit, and the basic synaptic connection unit 1 and the basic synaptic connection unit 2 are connected to the basic neuron unit 1, and the external connection relationship of the original operator is retained.

[0078] It can be understood that Figure 9 in the original computation graph, the IFNode node 1, the IFNode node 2, and the IFNode node 3 all represent an IFNode operator, the addition node 1 represents an addition operator, and the 2D convolution node represents a convolution node. As shown in Table 1, the IFNode node 1, the IFNode node 2, the IFNode node 3, and the 2D convolution node are all type-one operator nodes. As shown in Table 2, the addition node 1 is a type-two operator node.

[0079] It should be noted that when replacing the complex operator nodes in the intermediate computation graph with hardware unit nodes, the external connection relationships of the complex operator nodes are retained.

[0080] Through the abstract design of hardware units, the embodiments of the present invention realize the modular encapsulation of operators in the neural network, making each operator in the neural network an independent module with clear functions and interfaces, which is convenient for management and reuse, and can convert the neural network into a computation graph more accurately and efficiently. On this basis, the embodiments of the present invention formulate the connection rules between hardware units, realize the conversion between hardware units and operators in the neural network, and improve the flexibility of brain-inspired chip compilation.

[0081] In the embodiments of the present invention, based on the topological connection relationships of neuron nodes and synaptic connection nodes in the target computation graph, each neuron node in the target computation graph can be grouped through numerical calculations, mathematical statistics, etc. to obtain multiple target routing groups.

[0082] As an optional embodiment, each neuron unit node in the target computational graph is grouped to obtain a plurality of target routing groups, including: for each neuron node in the target computational graph, each successor neuron node of each neuron node is determined as an original routing group, and each neuron node is determined as the input neuron node of the original routing group. The successor neuron node of a neuron node is a neuron node located on the output side of the neuron node and connected through a synaptic connection node. Any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-inspired chip.

[0083] Traverse each original routing group. When there are the same neuron nodes in any two original routing groups, merge and deduplicate the two original routing groups to obtain an intermediate routing group, and determine the input neuron nodes that are not in the intermediate routing group among the input neuron nodes of the two original routing groups as the input neuron nodes of the intermediate routing group.

[0084] Traverse each intermediate routing group. When any intermediate routing group includes any neuron node and the successor neuron node of any neuron node, determine the successor neuron node of any neuron node as a sub-routing group in any intermediate routing group, and determine any neuron node as the input neuron node of the sub-routing group in any intermediate routing group.

[0085] Determine each original routing group, each intermediate routing group, and each sub-routing group in each intermediate routing group as each target routing group.

[0086] Figure 10 It is a schematic structural diagram of the target routing group in the brain-inspired chip compilation method provided by the present invention. As Figure 10 shown, the successor neuron node of neuron node A is neuron node B, the successor neuron nodes of neuron node B are neuron node C and neuron node D respectively, and the successor neuron node of neuron node C is neuron node D. Therefore, neuron node B can be determined as the original routing group 3, the input neuron node of the original routing group 3 is determined as neuron node A, neuron node C and neuron node D are determined as the original routing group 1, the input neuron node of the original routing group 1 is determined as neuron node B, neuron node D is determined as the original routing group 2, and the input node of the original routing group 2 is determined as neuron node C.

[0087] Since both the original routing group 1 and the original routing group 2 include neuron node D, resulting in a situation of routing group nesting, the original routing group 1 and the original routing group 2 can be merged and deduplicated to obtain an intermediate routing group including neuron node C and neuron node D, and neuron node B is determined as the input neuron node of the above intermediate routing group.

[0088] Since the above intermediate routing group includes neuron node C and the successor neuron node D of neuron node C, neuron node D can be determined as a sub-routing group in the above intermediate routing group, and neuron node C can be determined as the input neuron node of the sub-routing group in the above intermediate routing group.

[0089] Furthermore, the original routing group 3 including neuron node B can be determined as target routing group 3, the intermediate routing group including neuron node C and neuron node D can be determined as target routing group 1, and the routing group including neuron node D (the sub-routing group in the above intermediate routing group 1) can be determined as target routing group 2.

[0090] It should be noted that Figure 10 the unidirectional arrows in represent the synaptic connection nodes between two neural nodes. Since there is no involvement of synaptic connection nodes, they are omitted in the figure.

[0091] In the embodiment of the present invention, by performing reasonable arrangement and alignment operations on the sub-packets in the original routing group, it is ensured that each target routing group meets the routing rules.

[0092] Step 102: Split and optimize the weight matrix of the target synaptic connection nodes in the target computational graph to obtain the optimized weight matrix of the target synaptic connection nodes.

[0093] In the embodiment of the present invention, the synaptic connection nodes in the target computational graph that meet the preset conditions can be determined as the target synaptic connection nodes. Furthermore, based on numerical calculation, the weight matrix of the target synaptic connection nodes in the target computational graph can be split and optimized to obtain the optimized weight matrix of the target synaptic connection nodes.

[0094] Figure 11 is a correspondence diagram between the target computational graph and the structure of the computing cores in the brain-inspired chip provided by the present invention. As Figure 11 shown, the neuron nodes in the target computational graph represent the neuron units in the brain-inspired chip, and the neuron units are the neuron computing circuits of the computing cores in the brain-inspired chip. The synaptic connection nodes in the target computational graph represent the synaptic connection units in the brain-inspired chip, and the attribute weight matrix of the synaptic connection units is stored in the crossbar array of the computing cores in the brain-inspired chip.

[0095] As an optional embodiment, the weight matrix of the target synaptic connection node in the target computational graph is partitioned and optimized to obtain the optimized weight matrix of the target synaptic connection node, including: for any neuron node in the target computational graph, when there are several forward neuron nodes for any neuron node, each synaptic connection node between any neuron node and each forward neuron node of any neuron node is determined as each original synaptic connection node corresponding to any neuron node, and the forward neuron node of any neuron node is the neuron node connected to the input side of any neuron node through the synaptic connection node.

[0096] When the weight matrix of any original synaptic connection node corresponding to any neuron node is a block diagonal matrix, any original synaptic connection node corresponding to any neuron node is determined as the first target synaptic connection node among the target synaptic connection nodes corresponding to any neuron node, and other original synaptic connection nodes corresponding to any neuron node except any original synaptic connection node are determined as the second target synaptic connection nodes among the target synaptic connection nodes corresponding to any neuron node. The elements in the non-zero sub-matrix located on the main diagonal of the block diagonal matrix are not all 0 values, and all other elements except the non-zero sub-matrix located on the main diagonal of the block diagonal matrix are 0 values.

[0097] Each sub-matrix on the main diagonal of the weight matrix of the first target synaptic connection node corresponding to any neuron node is respectively determined as the optimized weight matrix of the first target synaptic connection node corresponding to any neuron node.

[0098] Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any neuron node, the weight matrix of the second target synaptic connection node corresponding to any neuron node is a plurality of sub-matrices in the column dimension, which is used as the optimized weight matrix of the second target synaptic connection node corresponding to any neuron node. The number of the optimized weight matrices of the second target synaptic connection node corresponding to any neuron node is the same as the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any neuron node.

[0099] Based on the column dimension, the corresponding relationship between the columns of the optimized weight matrix of the first target synaptic connection node and the optimized weight matrix of the second target synaptic connection node corresponding to any neuron node is determined.

[0100] Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any neuron node, the output of the forward neuron node connected to the input side of any neuron node through the first target synaptic connection node is divided into multiple sub-outputs, and the one-to-one corresponding relationship between each sub-output and the optimized weight matrix of the target synaptic connection node corresponding to any neuron node is determined.

[0101] Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any neuron node, create multiple sub-synaptic connection nodes between any neuron node and each neuron node of any neuron node in the target computational graph, and determine the one-to-one correspondence between each sub-synaptic connection node and each sub-output. The number of sub-synaptic connection nodes between any neuron node and each neuron node of any neuron node is the same as the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any neuron node. Each sub-synaptic connection node between any neuron node and each neuron node of any neuron node represents the computational task between each sub-output and the optimized weight matrix of the target synaptic connection node corresponding to any neuron node.

[0102] It should be noted that the synaptic connection unit in the brain-inspired chip is used to connect neuron units. The output of a neuron unit is a vector. If the output of neuron unit 1 has a length of , and the output of neuron unit 2 has a length of , and synaptic connection unit 1 is used to connect neuron 1 and neuron 2, then synaptic connection unit 1 has a weight matrix with a size of . For any neuron unit with several forward neuron units, its output is , where is the output of the forward neuron unit, is the weight matrix of the synaptic connection unit connecting the forward neuron unit and this neuron unit, represents the activation function of this neuron unit, and is used to identify the forward neuron unit of this neuron unit.

[0103] Figure 12 Figure 12 is a schematic flow diagram of segmenting and optimizing the target synaptic connection node in the brain-inspired chip compilation method provided by the present invention. As shown in (1) of , if the input side of neuron node C in the target computational graph is respectively connected to neuron node A and neuron node B through synaptic connection nodes, then both neuron node A and neuron node B are forward neuron nodes of neuron node C.

[0104] Correspondingly, the synaptic connection node 1 between neuron node A and neuron node C and the synaptic connection node 2 between neuron node B and neuron node C can be respectively determined as the original synaptic connection nodes corresponding to neuron node C.

[0105] ​It can be understood that after the operation results obtained by the output of neuron node A through the operation corresponding to synaptic connection node 1 and the operation results obtained by the output of neuron node B through the operation corresponding to synaptic connection node 2 are respectively input into neuron node C, neuron node C can calculate the sum of the above operation results and substitute it into the activation function of neuron node C for calculation. Figure 12 The operation corresponding to synaptic connection node 1 in Figure 12 can be a 2D matrix multiplication operation, and the operation corresponding to synaptic connection node 2 can be a fully connected operation.

[0106] The weight matrices of synaptic connection node 1 and synaptic connection node 2 are obtained respectively. As Figure 12 shown in Figure (2) in Figure 12 , the weight matrix of synaptic connection node 1 can be represented as multiple sub-matrices, and only the sub-matrices on the main diagonal are non-zero matrices, and the rest of the sub-matrices are zero matrices. Therefore, it can be determined that the weight matrix of synaptic connection node 1 is a block diagonal matrix, indicating that there is a waste of computing resources in the weight matrix of synaptic connection node 1. Synaptic connection node 1 can be determined as the first target synaptic connection node corresponding to neuron node C.

[0107] It should be noted that the weight matrix of synaptic connection node 2 is not a block diagonal matrix. Therefore, synaptic connection node 2 can be determined as the second target synaptic connection node corresponding to neuron node C.

[0108] As Figure 12 shown in Figure (2) in Figure 12 , when the weight matrix of synaptic connection node 1 can be divided into three block diagonal matrices, each non-zero sub-matrix on the main diagonal of the weight matrix of synaptic connection node 1: non-zero sub-matrix S1, non-zero sub-matrix S2, and non-zero sub-matrix S3 can be respectively determined as the optimized weight matrices of synaptic connection node 1. The weight matrix of synaptic connection node 2 can be divided into 3 sub-matrices in the column dimension, which are sub-matrix S4-1, sub-matrix S4-2, and sub-matrix S4-3 respectively.

[0109] As Figure 12As shown in Figure (2), S1 of the weight matrix of synaptic connection node 1 and sub-matrix S4-1 in the weight matrix of synaptic connection node 2 are in the same column dimension, and the corresponding relationship between the non-zero sub-matrix S1 of the weight matrix of synaptic connection node 1 and sub-matrix S4-1 in the weight matrix of synaptic connection node 2 can be determined; similarly, the non-zero sub-matrix S2 of the weight matrix of synaptic connection node 1 and sub-matrix S4-2 in the weight matrix of synaptic connection node 2 are in the same column dimension, and the corresponding relationship between S2 of the weight matrix of synaptic connection node 1 and sub-matrix S4-2 in the weight matrix of synaptic connection node 2 can be determined. The non-zero sub-matrix S3 of the weight matrix of synaptic connection node 1 and sub-matrix S4-3 in the weight matrix of synaptic connection node 2 are in the same column dimension, and the corresponding relationship between S3 of the weight matrix of synaptic connection node 1 and sub-matrix S4-3 in the weight matrix of synaptic connection node 2 can be determined.

[0110] Since neuron node A is connected to neuron node C through the first target synaptic connection node (synaptic connection node 1), when the weight matrix of synaptic connection node 1 is composed of three non-zero sub-matrices located on the main diagonal and all other elements in the weight matrix of synaptic connection node 1 are 0, the output of neuron node A can be divided into three sub-outputs, namely sub-output A-1, sub-output A-2, and sub-output A-3, and the corresponding relationship between sub-output A-1 and the non-zero sub-matrix S1 of the weight matrix of synaptic connection node 1 and sub-matrix S4-1 in the weight matrix of synaptic connection node 2 can be determined, the corresponding relationship between sub-output A-2 and the non-zero sub-matrix S2 of the weight matrix of synaptic connection node 1 and sub-matrix S4-2 in the weight matrix of synaptic connection node 2 can be determined, and the corresponding relationship between sub-output A-3 and the non-zero sub-matrix S3 of the weight matrix of synaptic connection node 1 and sub-matrix S4-3 in the weight matrix of synaptic connection node 2 can be determined.

[0111] As Figure 12 shown in Figure (3), after obtaining the optimized weight matrices of synaptic connection node 1 and synaptic connection node 2 and determining the one-to-one correspondence between the sub-output of neuron node A and the optimized weight matrices of synaptic connection node 1 and synaptic connection node 2, when the weight matrix of synaptic connection node 1 can be divided into a block diagonal matrix, three sub-synaptic connection nodes, namely sub-synaptic connection node 1, sub-synaptic connection node 2, and sub-synaptic connection node 3, can be created between neuron node C and neuron node A and neuron node B in the target computational graph, and the corresponding relationship between sub-synaptic connection node 1 and sub-output A-1 of neuron node A can be determined, the corresponding relationship between sub-synaptic connection node 2 and sub-output A-2 of neuron node A can be determined, and the corresponding relationship between sub-synaptic connection node 3 and sub-output A-3 of neuron node A can be determined.

[0112] After creating three sub-synaptic connection nodes between neuron node C and neuron node A and neuron node B in the target computational graph, the sub-input C-1 of neuron node C can be obtained by calculating the sum of the calculation result obtained by performing a 2D matrix multiplication operation on the sub-output A-1 of neuron node A and the non-zero sub-matrix S1 of the weight matrix of synaptic connection node 1, and the calculation result obtained by performing a fully connected operation on the output B of neuron node B and the sub-matrix S4-1 in the weight matrix of synaptic connection node 2.

[0113] It should be noted that the output of neuron node A is the matrix To calculate the matrix multiplication then the matrix is tiled by row dimension. Then several copies are replicated and arranged on the diagonal of the weight matrix of the synaptic connection node. The non-zero sub-matrices S1, S2, and S3 of the weight matrix of synaptic connection node 1 are several copies generated by replication. . The sub-output A-1 of neuron node A is only the first row of the matrix , the sub-output A-2 of neuron node A is the second row of the matrix , and the sub-output A-3 of neuron node A is the third row of the matrix .

[0114] Similarly, the sub-input C-2 of neuron node C can be obtained by calculating the sum of the calculation result obtained by performing a 2D matrix multiplication operation on the sub-output A-2 of neuron node A and the non-zero sub-matrix S2 of the weight matrix of synaptic connection node 1, and the calculation result obtained by performing a fully connected operation on the output B of neuron node B and the sub-matrix S4-2 in the weight matrix of synaptic connection node 2. The sub-input C-3 of neuron node C can be obtained by calculating the sum of the calculation result obtained by performing a 2D matrix multiplication operation on the sub-output A-3 of neuron node A and the non-zero sub-matrix S3 of the weight matrix of synaptic connection node 1, and the calculation result obtained by performing a fully connected operation on the output B of neuron node B and the sub-matrix S4-3 in the weight matrix of synaptic connection node 2.

[0115] In an embodiment of the present invention, for a specific synaptic connection node, such as a synaptic connection node representing a 2D matrix multiplication element, its weight matrix is arranged in a diagonal form by multiple non-zero sub-matrices, and the rest are all zeros. Therefore, it is a block diagonal matrix with the property of being splittable.

[0116] For a general synaptic connection node, if its weight matrix is a sparse matrix, the weight matrix of the above synaptic connection node can be converted into a block diagonal matrix through the following embodiments. At this time, the synaptic connection node can be split, converted into multiple sub-synaptic connection nodes, and redundant zeros in the weight matrix can be removed. Through the above method, without changing the computing structure, as many non-zero parts as possible in the weight matrix can be deployed to the crossbar array of the computing core. The scale of the weight matrix of the synaptic connection node deployed to the crossbar array of the computing core is significantly reduced. Under the condition of the same size of crossbar array hardware resources, a larger weight matrix can be stored, saving the hardware resources of the computing core and improving the computing resource utilization rate and computing efficiency of the brain-inspired chip.

[0117] As an optional embodiment, for any neuron node in the target computation graph, when there are several forward neuron nodes for any neuron node, each synaptic connection node between any neuron node and each forward neuron node of any neuron node is determined as each original synaptic connection node corresponding to any neuron node. Before the forward neuron node of any neuron node is a neuron node connected to the input side of any neuron node through a synaptic connection node, the method further includes: performing row and column transformations on the weight matrix of the synaptic connection node in the target computation graph.

[0118] Performing row and column transformations on the weight matrix of the synaptic connection node in the target computation graph includes: for any synaptic connection node in the target computation graph, when the weight matrix of any synaptic connection node is a sparse matrix, grouping the columns in the weight matrix of any synaptic connection node based on the union-find algorithm to obtain the column grouping result of the weight matrix of any synaptic connection node.

[0119] Based on the column grouping result of the weight matrix of any synaptic connection node, performing column transformation on the weight matrix of any synaptic connection node, arranging the columns belonging to the same group in the weight matrix of any synaptic connection node together, and obtaining each column transformation matrix corresponding to any synaptic connection node.

[0120] Performing row transformation on each column transformation matrix corresponding to any synaptic connection node column, arranging the rows with all elements being 0 values in each column transformation matrix corresponding to any synaptic connection node column together, and arranging the rows with all elements not being all 0 values in each column transformation matrix corresponding to any synaptic connection node column together, and obtaining each row transformation matrix corresponding to any synaptic connection node.

[0121] For any synaptic connection node, a matrix in which all elements in each row transformation matrix corresponding to the synaptic connection node are not all 0 is determined as a non-zero sub-matrix in each row transformation matrix corresponding to the synaptic connection node. When the number of non-zero sub-matrices in each row transformation matrix corresponding to any synaptic connection node is 1, the row transformation matrices corresponding to each row of the synaptic connection node are spliced, and through row transformation, the non-zero sub-matrices in each row transformation matrix corresponding to the synaptic connection node are arranged along the main diagonal to obtain the weight matrix after row and column transformation of the synaptic connection node.

[0122] Figure 13 It is a schematic flowchart of row and column transformation of synaptic connection nodes in the compilation method of the brain-like chip provided by the present invention. As Figure 13 shown, for any synaptic connection node in the target computational graph, when the size of the weight matrix of the synaptic connection node is 12×12, if the elements in the weight matrix of the synaptic connection node include 0 values and non-0 values, when the 0 values in any two columns of the weight matrix of the synaptic connection node are in the same row, it can be determined that the above two columns belong to the same group, and then the column grouping result of the weight matrix of the synaptic connection node can be obtained.

[0123] By grouping the columns of the weight matrix of the synaptic connection node, it can be identified which rows in the weight matrix of the synaptic connection node can be combined to form a non-zero sub-matrix for independent processing.

[0124] Based on the column grouping result of the weight matrix of the synaptic connection node, column transformation is performed on the weight matrix of the synaptic connection node, and the columns belonging to the same group in the weight matrix of the synaptic connection node are arranged together to obtain each column transformation matrix corresponding to the synaptic connection node.

[0125] Row transformation is performed on each column transformation matrix corresponding to the synaptic connection node. The rows in which all elements in each column transformation matrix corresponding to the synaptic connection node are 0 are arranged together, and the rows in which all elements in each column transformation matrix corresponding to the synaptic connection node are not all 0 are arranged together to obtain each row transformation matrix corresponding to the synaptic connection node.

[0126] A matrix in which all elements in each row transformation matrix corresponding to the synaptic connection node are not all 0 is determined as a non-zero sub-matrix in each row transformation matrix corresponding to the synaptic connection node. When the number of non-zero sub-matrices in each row transformation matrix corresponding to the synaptic connection node is 1, the row transformation matrices corresponding to each row of the synaptic connection node are spliced, and through row transformation, the non-zero sub-matrices in each row transformation matrix corresponding to the synaptic connection node are arranged along the main diagonal of the matrix to obtain the weight matrix after row and column transformation of the synaptic connection node.

[0127] As Figure 13 shown, the weight matrix after row-column transformation corresponding to the above synaptic connection nodes is a block diagonal matrix, and the non-zero sub-matrices in each row transformation matrix corresponding to the above synaptic connection nodes are equivalent to Figure 13 the non-zero sub-matrix S1, non-zero sub-matrix S2, and non-zero sub-matrix S3 in

[0128] In the embodiments of the present invention, by appropriately adjusting the weight matrix of the synaptic connection nodes in the target computational graph, the weight matrix of the synaptic connection nodes can be effectively deployed on the crossbar array of the computing core, thereby achieving the purpose of improving computing efficiency and reducing resource waste.

[0129] Step 103: Assign routing coordinates for each target routing group to indicate the position of each target routing group in the computing core of the brain-inspired chip, and then generate the configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection nodes.

[0130] It should be noted that in the embodiments of the present invention, the neuron nodes in the target computational graph are grouped for routing to determine the arrangement of the neuron nodes in each target routing group in the computing core, and then the address of each neuron in the neuron RAM of the computing core can be assigned.

[0131] In the embodiments of the present invention, the synaptic connection nodes in the target computational graph are grouped to determine the arrangement of the inputs of each target routing group in the inputs of the computing core and assign the order of the synaptic connection nodes in the inputs of the computing core. The synaptic connection unit of the computing core corresponds to the output destination of the forward neuron nodes in the target computational graph. At the same time, the same address is assigned to the inputs shared by all neuron nodes or sub-routing groups in each target routing group, and the above operations are recursively performed on the sub-routing groups.

[0132] Due to the characteristics of the brain-inspired chip, the routing coordinates need to be assigned according to certain rules.

[0133] The routing structure in the brain-inspired chip is a five-level quadtree. Each computing core can be indexed by a two-dimensional routing coordinate (x, y), where both x and y are 5-bit numbers. When setting the destination of a neuron, multicast can be achieved by setting several bits at the end of the routing coordinate of the target computing core to be undetermined (denoted by the symbol "*"). For example, setting the routing coordinate of the target computing core to (010**,100**) means that the data will be sent to (01000,10000) to (01000,10111), (01001,10000) to (01001,10011), (01010,10000) to (01001,10011), (01011,10000) to (01001,10011), a total of 16 computing cores.

[0134] In view of this function, the brain-inspired chip requires that the number of computing cores occupied by each routing group needs to be a power of 2. At the same time, the routing coordinate serial number of the first computing core it uses needs to end with several 0s (if computing cores are used, the number of 0s at the end needs to be greater than ).

[0135] At the same time, the brain-inspired chip also requires that in each layer of the five-level quadtree, the data flow between routing nodes cannot form a loop. For example, routing group 1 → routing group 2 → routing group 3 → routing group 1. This requires allocating routing coordinates to routing groups in the order of topological sorting.

[0136] In the embodiments of the present invention, based on the nesting relationship between target routing groups, through numerical calculation, mathematical statistics, conditional judgment, etc., routing coordinates for indicating the positions of computing cores of each target routing group in the brain-inspired chip can be allocated to each target routing group.

[0137] As an optional embodiment, allocating routing coordinates for indicating the positions of computing cores of each target routing group in the brain-inspired chip to each target routing group includes: determining the number of computing cores required for each target routing group.

[0138] Based on the topological relationship between neuron nodes and synapse connection nodes in the target computation graph and the number of computing cores required for each target routing group, allocate routing coordinates to each target routing group.

[0139] Specifically, when allocating routing coordinates to a target routing group in the embodiments of the present invention, considering that the target routing groups have a nested structure, in order to make the routing coordinates of each target routing group meet the above requirements, the routing coordinate allocation of the target routing group should be carried out according to the following process: First, determine the number of computing cores required for each target routing group.

[0140] Due to the multicast function of the brain-inspired chip, the number of computing cores required for each target routing group is not simply the sum of the computing cores required for all sub-routing groups and neuron nodes in that target routing group. After performing a topological sort on the neuron nodes in the target routing group, the positions of the neuron nodes in the target routing group need to be determined sequentially according to the order and alignment requirements, and finally the number of computing cores required for that target routing group is determined. Since the target routing group is a nested structure, this step is a bottom-up recursive process.

[0141] It should be noted that in order to meet the rules of the routing structure of the brain-inspired chip, in the embodiments of the present invention, it is necessary to determine the number of computing cores required for the target routing group based on the topological sort of the target routing group. For any routing group, the number of computing cores required for each sub-routing group is rounded up to the nearest power of 2 in sequence. For any sub-routing group, the subscript of its first computing core in the above target routing group needs to be an integer multiple of the rounded-up number of computing cores required for that sub-routing group. After the positions of all sub-routing groups of the target routing group are determined, the number of computing cores required for the above target routing group can be determined.

[0142] Since there is an upper limit to the number of computing cores of a single brain-inspired chip. Therefore, when the remaining number of computing cores of the brain-inspired chip is not sufficient to accommodate all target routing groups, the allocation can continue starting from the first computing core of the next brain-inspired chip.

[0143] Considering the existence of sub-routing groups, the number of computing cores required for the target routing group is not simply the sum of the computing cores required for the neuron nodes it contains. During the topological sort and alignment process of the sub-routing groups, additional computing core requirements will be generated. After adding this part of the additional requirements to the number of computing cores required for the neuron nodes, the total number of computing cores required for that target routing group is obtained.

[0144] According to the topological relationship between the neuron nodes and synaptic connection nodes in the target computation graph, the starting coordinates of the computing cores are set for each target routing group, and then the routing coordinates of each target routing group can be obtained based on the number of computing cores required for each target routing group.

[0145] It should be noted that since the target routing group is a nested structure, this step is a top-down recursive process.

[0146] After allocating routing coordinates for each target routing group, configuration information can be generated for each used computing core. The above configuration information includes but is not limited to weight data, computing core attributes, and neuron unit information, etc.

[0147] The weight data can be determined based on the input neurons and output neurons connected within the computational core. If there is a synapse that directly connects the input and the output, the weight matrix data of the synapse is used; otherwise, the weight of this part is set to zero.

[0148] All computing cores in the same routing group share the same property settings, such as random number seeds, etc. These properties have been defined in the previous steps, and the computing core only needs to apply the corresponding properties of the routing group to which it belongs.

[0149] Neuron unit information contains the properties of the neuron unit and the details of its output destination. The properties of the neuron unit are determined by the configuration information carried by the neuron node in the target computation graph. The output destination information involves the routing coordinates of the computation kernel and its order in the input. By locating the routing group where the output destination of the neuron unit is located, the routing coordinates of the group are obtained as part of the target information; at the same time, the synaptic distribution within the relevant routing group is found to obtain the order of the neurons in the input of the routing group to form the target information of the complete neuron.

[0150] Step 104: Generate an executable file based on the configuration information of the computing core, where the executable file includes binary instructions recognizable by the brain-like chip.

[0151] It should be noted that although the configuration information of the computing kernel comprehensively describes the target computing graph, this configuration information is only a data structure that is easy for humans to understand and check, and cannot be directly executed on brain-like chips.

[0152] Therefore, in the embodiment of the present invention, after generating the configuration information of the computing core in the brain-like chip, the configuration information of the computing core can be converted into corresponding machine code according to the instruction set of the brain-like chip and following specific rules. The generated machine code is stored in the form of a file. These data can be downloaded to the brain-like chip and executed.

[0153] The embodiment of the present invention obtains multiple target routing groups by grouping the neuron unit nodes in the target computation graph, and segmenting and optimizing the weight matrix of the target synaptic connection nodes in the target computation graph to obtain the optimized weight matrix of the target synaptic connection nodes, and then assigns routing coordinates for indicating the position of the computing core of each target routing group in the brain-like chip to each target routing group. Based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group and the optimized weight matrix of the target synaptic connection nodes, the configuration information of the computing core is generated. Based on the configuration information of the computing core, an executable file is generated, which can improve the efficiency and configuration accuracy of brain-like chip compilation, optimize the computing resource allocation of brain-like chips, and has broad application prospects.

[0154] In the brain-inspired chip compilation method provided by the present invention, by recording the states of neurons and synapses in a neural network at each simulation time step, cycle-accurate simulation of a neural network based on the hardware computing principle of a brain-inspired chip can be achieved, which can provide detailed data support for subsequent analysis and optimization, not only improving the efficiency of neural network debugging and performance optimization, but also effectively shortening the entire development cycle.

[0155] In the brain-inspired chip compilation method provided by the present invention, the unique hardware architecture of the brain-inspired chip and the advantages of routing communication are fully utilized, and in the compilation of larger-scale brain-inspired chips, the scalability of the brain-inspired chip is significantly improved.

[0156] As an optional embodiment, after obtaining a plurality of target routing groups, the method further includes: obtaining the optimal weight bit width of the weight matrix of each target routing group.

[0157] Obtaining the optimal weight bit width of the weight matrix of each target routing group includes: obtaining the maximum value and the minimum value of the weight matrix of each target routing group.

[0158] When the maximum value of the weight matrix of each target routing group is in the first numerical interval and the minimum value of the weight matrix of each target routing group is in the second numerical interval, it is determined that the optimal weight bit width of the weight matrix of each target routing group is the first preset value.

[0159] When the maximum value of the weight matrix of each target routing group is in the third numerical interval and the minimum value of the weight matrix of each target routing group is in the fourth numerical interval, it is determined that the optimal weight bit width of the weight matrix of each target routing group is the second preset value.

[0160] When the maximum value of the weight matrix of each target routing group is in the fifth numerical interval and the minimum value of the weight matrix of each target routing group is in the sixth numerical interval, it is determined that the optimal weight bit width of the weight matrix of each target routing group is the third preset value.

[0161] When the maximum value of the weight matrix of each target routing group is in the seventh numerical interval and the minimum value of the weight matrix of each target routing group is in the eighth numerical interval, it is determined that the optimal weight bit width of the weight matrix of each target routing group is the fourth preset value.

[0162] In the embodiments of the present invention, by utilizing the hardware characteristic that a brain-inspired chip can support multiple weight bit widths, the maximum value and the minimum value of the weight matrix of each target routing group are obtained to obtain the optimal weight bit width of each target routing group, so that under the condition of the same size of crossbar array hardware resources, a larger weight matrix can be stored, saving the hardware resources of the computing cores in the brain-inspired chip.

[0163] It should be noted that the first numerical range may include a numerical range not greater than 1; the second numerical range includes a numerical range greater than 0; the value of the first preset value may be 1 bit.

[0164] The third numerical range may include a numerical range not greater than 1; the fourth numerical range may include a numerical range less than 0 and not less than -2; the value of the second preset value may be 2 bits.

[0165] The fifth numerical range may include a numerical range greater than 1 and not greater than 7; the sixth numerical range may include a numerical range less than -2 and not less than -8; the value of the third preset value may be 4 bits.

[0166] The seventh numerical range may include a numerical range greater than 7 and not greater than 127, and the eighth numerical range may include a numerical range less than -8 and not less than -128; the value of the fourth preset value may be 8 bits.

[0167] In the embodiments of the present invention, is used to identify the target routing group,

[0168] For the th target routing group, it is preset that the optimal weight bit width of the weight matrix of the th target routing group is 8 bits.

[0169] The maximum value and the minimum value of the weight matrix of the th target routing group are obtained through numerical calculation.

[0170] In the case of and , it is determined that the optimal weight bit width of the weight matrix of the th target routing group is 1 bit.

[0171] In the case of and , it is determined that the optimal weight bit width of the weight matrix of the th target routing group is 2 bits.

[0172] In the case of and , it is determined that the weight bit width of the weight matrix of the th target routing group is 4 bits.

[0173] In the case of and , it is determined that the optimal weight bit width of the weight matrix of the th target routing group is 8 bits.

[0174] After obtaining the optimal weight bit width of the weight matrix of the th target routing group, through numerical calculation, based on the optimal weight bit width of the weight matrix of the th target routing group, the weight matrix of the th target routing group is segmented and optimized to obtain the optimized weight matrix of the th target routing group.

[0175] Figure 14 FIG. is a schematic structural diagram of the brain-inspired chip compilation device provided by the present invention. The following combines Figure 14 to describe the brain-inspired chip compilation device provided by the present invention. The brain-inspired chip compilation device described below can be mutually corresponding and referred to with the brain-inspired chip compilation method provided by the present invention described above. As Figure 14 shown, the device includes: a routing grouping module 1401, a weight optimization module 1402, a configuration generation module 1403, and a file generation module 1404.

[0176] The routing grouping module 1401 is configured to group each neuron unit node in the target computation graph to obtain a plurality of target routing groups. Any neuron node in the target computation graph represents a neuron unit, any synaptic connection node in the target computation graph represents a synaptic connection unit, and a unidirectional arrow used to connect two hardware nodes in the target computation graph represents the input-output relationship between the two hardware nodes.

[0177] The weight optimization module 1402 is configured to segment and optimize the weight matrix of the target synaptic connection node in the target computation graph to obtain the optimized weight matrix of the target synaptic connection node.

[0178] The configuration generation module 1403 is configured to assign routing coordinates for indicating the position of the computing core of each target routing group in the brain-inspired chip to each target routing group, and then generate configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node.

[0179] The file generation module 1404 is configured to generate an executable file based on the configuration information of the computing core. The executable file includes binary instructions recognizable by the brain-inspired chip.

[0180] Specifically, the routing grouping module 1401, the weight optimization module 1402, the configuration generation module 1403, and the file generation module 1404 are electrically connected.

[0181] In the brain-inspired chip compilation device in the embodiments of the present invention, by grouping each neuron unit node in the target computational graph to obtain multiple target routing groups, and by splitting and optimizing the weight matrix of the target synaptic connection nodes in the target computational graph to obtain the optimized weight matrix of the target synaptic connection nodes, and then assigning routing coordinates for indicating the positions of the computing cores in the brain-inspired chip to each target routing group, based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection nodes, generating the configuration information of the computing cores, and based on the configuration information of the computing cores, generating an executable file, it can improve the efficiency and configuration accuracy of brain-inspired chip compilation, optimize the computing resource allocation of the brain-inspired chip, and has broad application prospects.

[0182] Figure 15 Illustrates a schematic physical structure diagram of an electronic device, as Figure 15 shown. The electronic device may include: a processor 1510, a communication interface 1520, a memory 1530, and a communication bus 1540. Among them, the processor 1510, the communication interface 1520, and the memory 1530 communicate with each other through the communication bus 1540. The processor 1510 can call the logical instructions in the memory 1530 to execute the brain-inspired chip compilation method, and the method includes: based on the topological connection relationship between the neuron nodes and the synaptic connection nodes in the target computational graph, grouping each neuron unit node in the target computational graph to obtain multiple target routing groups. Any neuron node in the target computational graph represents a neuron unit in the brain-inspired chip, and any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-inspired chip. The unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes; splitting and optimizing the weight matrix of the target synaptic connection nodes in the target computational graph to obtain the optimized weight matrix of the target synaptic connection nodes; assigning routing coordinates for indicating the positions of the computing cores in the brain-inspired chip to each target routing group, and then based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection nodes, generating the configuration information of the computing cores; based on the configuration information of the computing cores, generating an executable file, and the executable file includes binary instructions recognizable by the brain-inspired chip.

[0183] In addition, when the logical instructions in the above-mentioned memory 1530 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0184] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the brain-like chip compilation method provided by the above-mentioned various methods. The method includes: based on the topological connection relationship between neuron nodes and synaptic connection nodes in the target computational graph, grouping each neuron unit node in the target computational graph to obtain multiple target routing groups. Any neuron node in the target computational graph represents a neuron unit in the brain-like chip, and any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-like chip. The unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes; dividing and optimizing the weight matrix of the target synaptic connection node in the target computational graph to obtain the optimized weight matrix of the target synaptic connection node; assigning routing coordinates for indicating the position of each target routing group in the computing core of the brain-like chip to each target routing group, and then generating configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node; generating an executable file based on the configuration information of the computing core, and the executable file includes binary instructions recognizable by the brain-like chip.

[0185] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a brain-inspired chip compilation method provided by the above-mentioned various methods. The method includes: grouping each neuron unit node in the target computational graph based on the topological connection relationship between neuron nodes and synaptic connection nodes in the target computational graph, to obtain a plurality of target routing groups. Any neuron node in the target computational graph represents a neuron unit in the brain-inspired chip, and any synaptic connection node in the target computational graph represents a synaptic connection unit in the brain-inspired chip. The unidirectional arrow used to connect two hardware nodes in the target computational graph represents the input-output relationship between the two hardware nodes; partitioning and optimizing the weight matrix of the target synaptic connection node in the target computational graph to obtain the optimized weight matrix of the target synaptic connection node; allocating routing coordinates for each target routing group to indicate the position of each target routing group in the computing core of the brain-inspired chip, and then generating configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node; generating an executable file based on the configuration information of the computing core, and the executable file includes binary instructions recognizable by the brain-inspired chip.

[0186] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

[0187] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solutions, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0188] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A brain-like chip compilation method, characterized in that: include: Based on the topological connection relationship between the neuron nodes and the synaptic connection nodes in the target computing graph, the neuron unit nodes in the target computing graph are grouped to obtain multiple target routing groups, wherein any neuron node in the target computing graph represents a neuron unit in the brain-like chip, any synaptic connection node in the target computing graph represents a synaptic connection unit in the brain-like chip, and the one-way arrow in the target computing graph used to connect two hardware nodes represents the input-output relationship between the two hardware nodes; Segmenting and optimizing the weight matrix of the target synaptic connection node in the target calculation graph to obtain the optimized weight matrix of the target synaptic connection node; Assigning routing coordinates for indicating the location of the computing core of each target routing group in the brain-like chip to each target routing group, and then generating configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node; Based on the configuration information of the computing core, an executable file is generated, wherein the executable file includes binary instructions recognizable by the brain-like chip.

2. The brain-like chip compilation method according to claim 1, characterized in that: After obtaining the plurality of target routing groups, the method further comprises: Obtaining the optimal weight bit width of the weight matrix of each target routing group; The obtaining of the optimal weight bit width of the weight matrix of each target routing group includes: Obtaining the maximum and minimum values ​​of the weight matrix of each target routing group; When the maximum value of the weight matrix of each target routing group is within a first numerical interval and the minimum value of the weight matrix of each target routing group is within a second numerical interval, determining the optimal weight bit width of the weight matrix of each target routing group to be a first preset value, the first numerical interval includes: When the maximum value of the weight matrix of each target routing group is within the third numerical interval and the minimum value of the weight matrix of each target routing group is within the fourth numerical interval, determining the optimal weight value bit width of the weight matrix of each target routing group to be a second preset value; When the maximum value of the weight matrix of each target routing group is within the fifth numerical interval and the minimum value of the weight matrix of each target routing group is within the sixth numerical interval, determining the optimal weight value bit width of the weight matrix of each target routing group to be a third preset value; When the maximum value of the weight matrix of each target routing group is within the seventh numerical interval and the minimum value of the weight matrix of each target routing group is within the eighth numerical interval, the optimal weight bit width of the weight matrix of each target routing group is determined to be a fourth preset value.

3. The brain-like chip compilation method according to claim 1, characterized in that: The step of grouping the neuron unit nodes in the target computation graph to obtain a plurality of target routing groups includes: For each neuron node in the target computation graph, each successor neuron node of each neuron node is determined as an original routing group, and each neuron node is determined as an input neuron node of the original routing group, the successor neuron node of the neuron node is a neuron node located at the output side of the neuron node and connected to the neuron node through a synaptic connection node, and any synaptic connection node in the target computation graph represents a synaptic connection unit in the brain-like chip; Traversing each of the original routing groups, if there are identical neuron nodes in any two original routing groups, merging the two original routing groups and removing duplicates to obtain an intermediate routing group, and determining the input neuron nodes in the input neuron nodes of the two original routing groups that are not in the intermediate routing group as the input neuron nodes of the intermediate routing group; Traversing each of the intermediate routing groups, in the case that any intermediate routing group includes any neuron node and a successor neuron node of the any neuron node, determining the successor neuron node of the any neuron node as a sub-routing group in the any intermediate routing group, and determining the any neuron node as an input neuron node of the sub-routing group in the any intermediate routing group; Each of the original routing groups, each of the intermediate routing groups, and each of the sub-routing groups in each of the intermediate routing groups are determined as each of the target routing groups.

4. The brain-like chip compilation method according to claim 1, characterized in that: The segmenting and optimizing the weight matrix of the target synaptic connection node in the target computation graph to obtain the optimized weight matrix of the target synaptic connection node includes: For any neuron node in the target computation graph, when there are several forward neuron nodes in the any neuron node, each synaptic connection node between the any neuron node and each forward neuron node of the any neuron node is determined as each original synaptic connection node corresponding to the any neuron node, and the forward neuron node of the any neuron node is a neuron node connected to the input side of the any neuron node through a synaptic connection node; In the case where the weight matrix of any original synaptic connection node corresponding to any neuron node is a block diagonal matrix, the any original synaptic connection node corresponding to any neuron node is determined as a first target synaptic connection node among target synaptic connection nodes corresponding to any neuron node, and the other original synaptic connection nodes corresponding to any neuron node except the any original synaptic connection node are determined as second target synaptic connection nodes among target synaptic connection nodes corresponding to any neuron node, the elements in the submatrix located on the main diagonal of the block diagonal matrix are not all 0, and the elements in the block diagonal matrix except the non-zero submatrix located on the main diagonal are all 0; Determine each submatrix on the main diagonal of the weight matrix of the first target synaptic connection node corresponding to any neuron node as the optimized weight matrix of the first target synaptic connection node corresponding to any neuron node; Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any one of the neuron nodes, the weight matrix of the second target synaptic connection node corresponding to any one of the neuron nodes is divided into a plurality of sub-matrices in the column dimension as the optimized weight matrix of the second target synaptic connection node corresponding to any one of the neuron nodes, and the number of the optimized weight matrices of the second target synaptic connection node corresponding to any one of the neuron nodes is the same as the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any one of the neuron nodes; Determine, based on the column dimension, a correspondence between a weight matrix after optimization of a first target synaptic connection node and a weight matrix column after optimization of a second target synaptic connection node corresponding to any one of the neuron nodes; Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to the any neuron node, the output of the forward neuron node connected to the input side of the any neuron node through the first target synaptic connection node is divided into a plurality of sub-outputs, and a one-to-one correspondence between each of the sub-outputs and the optimized weight matrix of the target synaptic connection node corresponding to the any neuron node is determined; Based on the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any one of the neuron nodes, multiple sub-synaptic connection nodes are created between any one of the neuron nodes and each of the neuron nodes of any one of the neuron nodes in the target calculation graph, and a one-to-one correspondence between each of the sub-synaptic connection nodes and each of the sub-outputs is determined, the number of sub-synaptic connection nodes between any one of the neuron nodes and each of the neuron nodes of any one of the neuron nodes is the same as the number of non-zero sub-matrices in the weight matrix of the first target synaptic connection node corresponding to any one of the neuron nodes, and each sub-synaptic connection node between any one of the neuron nodes and each of the neuron nodes of any one of the neuron nodes represents a calculation task between each of the sub-outputs and the optimized weight matrix of the target synaptic connection node corresponding to any one of the neuron nodes.

5. The brain-like chip compilation method according to claim 4, characterized in that: For any neuron node in the target computation graph, when there are several forward neuron nodes in the any neuron node, each synaptic connection node between the any neuron node and each forward neuron node of the any neuron node is determined as each original synaptic connection node corresponding to the any neuron node, and the forward neuron node of the any neuron node is before the neuron node connected to the input side of the any neuron node through the synaptic connection node, the method further includes: Performing a row-column transformation on the weight matrix of the synaptic connection nodes in the target computation graph; The performing row-column transformation on the weight matrix of the synaptic connection nodes in the target computation graph includes: For any synaptic connection node in the target computation graph, when the weight matrix of any synaptic connection node is a sparse matrix, grouping the columns in the weight matrix of any synaptic connection node based on a union-find algorithm to obtain a column grouping result of the weight matrix of any synaptic connection node; Based on the column grouping result of the weight matrix of any synaptic connection node, the weight matrix of any synaptic connection node is transformed into a column, the columns belonging to the same group in the weight matrix of any synaptic connection node are arranged together, and each column transformation matrix corresponding to the any synaptic connection node is obtained; Performing row transformation on each column transformation matrix corresponding to any synaptic connection node column, arranging rows in which all elements in each column transformation matrix corresponding to any synaptic connection node column are 0 values ​​together, arranging rows in which all elements in each column transformation matrix corresponding to any synaptic connection node column are not all 0 values ​​together, and obtaining each row transformation matrix corresponding to any synaptic connection node; A matrix in which all elements in each row transformation matrix corresponding to any synaptic connection node are not all zero values ​​is determined as a non-zero submatrix in each row transformation matrix corresponding to any synaptic connection node. When the number of non-zero submatrices in each row transformation matrix corresponding to any synaptic connection node is 1, the row transformation matrices corresponding to any synaptic connection node are concatenated, and through row transformation, the non-zero submatrices in each row transformation matrix corresponding to any synaptic connection node are arranged along the main diagonal to obtain a weight matrix after row-column transformation of any synaptic connection node.

6. The brain-like chip compilation method according to any one of claims 1 to 5, characterized in that: The step of allocating routing coordinates for indicating the location of a computing core of each target routing group in the brain-like chip includes: Determining the number of computing cores required for each of the target routing groups; The routing coordinates are allocated to each of the target routing groups based on the topological relationship between the neuron nodes and the synaptic connection nodes in the target computing graph and the number of computing cores required for each of the target routing groups.

7. A brain-like chip compilation device, characterized in that: include: A routing grouping module, used for grouping each neuron unit node in the target computing graph to obtain multiple target routing groups, wherein any neuron node in the target computing graph represents a neuron unit, any synaptic connection node in the target computing graph represents a synaptic connection unit, and a one-way arrow in the target computing graph for connecting two hardware nodes represents an input-output relationship between the two hardware nodes; A weight optimization module, used to segment and optimize the weight matrix of the target synaptic connection node in the target calculation graph to obtain the optimized weight matrix of the target synaptic connection node; A configuration generation module, configured to assign routing coordinates for indicating the location of a computing core of each target routing group in the brain-like chip to each target routing group, and then generate configuration information of the computing core based on the neuron units included in each target routing group, the nested relationship between the target routing groups, the routing coordinates of each target routing group, and the optimized weight matrix of the target synaptic connection node; The file generation module is used to generate an executable file based on the configuration information of the computing core, and the executable file includes binary instructions recognizable by the brain-like chip.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the brain-like chip compilation method as described in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the brain-like chip compilation method as described in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the brain-like chip compilation method as described in any one of claims 1 to 6 is implemented.

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